Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 1 | /* |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 2 | * PowerPC version |
| 3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
| 4 | * |
| 5 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP |
| 6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> |
| 7 | * Adapted for Power Macintosh by Paul Mackerras. |
| 8 | * Low-level exception handlers and MMU support |
| 9 | * rewritten by Paul Mackerras. |
| 10 | * Copyright (C) 1996 Paul Mackerras. |
| 11 | * |
| 12 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and |
| 13 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com |
| 14 | * |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 15 | * This file contains the entry point for the 64-bit kernel along |
| 16 | * with some early initialization code common to all 64-bit powerpc |
| 17 | * variants. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 18 | * |
| 19 | * This program is free software; you can redistribute it and/or |
| 20 | * modify it under the terms of the GNU General Public License |
| 21 | * as published by the Free Software Foundation; either version |
| 22 | * 2 of the License, or (at your option) any later version. |
| 23 | */ |
| 24 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 25 | #include <linux/threads.h> |
Paul Gortmaker | c141611 | 2014-01-09 00:44:29 -0500 | [diff] [blame] | 26 | #include <linux/init.h> |
Paul Mackerras | b5bbeb2 | 2005-10-10 14:01:07 +1000 | [diff] [blame] | 27 | #include <asm/reg.h> |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 28 | #include <asm/page.h> |
| 29 | #include <asm/mmu.h> |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 30 | #include <asm/ppc_asm.h> |
| 31 | #include <asm/asm-offsets.h> |
| 32 | #include <asm/bug.h> |
| 33 | #include <asm/cputable.h> |
| 34 | #include <asm/setup.h> |
| 35 | #include <asm/hvcall.h> |
David Gibson | 6cb7bfe | 2005-10-21 15:45:50 +1000 | [diff] [blame] | 36 | #include <asm/thread_info.h> |
Stephen Rothwell | 3f639ee | 2006-09-25 18:19:00 +1000 | [diff] [blame] | 37 | #include <asm/firmware.h> |
Stephen Rothwell | 16a15a3 | 2007-08-20 14:58:36 +1000 | [diff] [blame] | 38 | #include <asm/page_64.h> |
Benjamin Herrenschmidt | 945feb1 | 2008-04-17 14:35:01 +1000 | [diff] [blame] | 39 | #include <asm/irqflags.h> |
Alexander Graf | 2191d657 | 2010-04-16 00:11:32 +0200 | [diff] [blame] | 40 | #include <asm/kvm_book3s_asm.h> |
Stephen Rothwell | 46f5221 | 2010-11-18 15:06:17 +0000 | [diff] [blame] | 41 | #include <asm/ptrace.h> |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 42 | #include <asm/hw_irq.h> |
chenhui zhao | 6becef7 | 2015-11-20 17:14:02 +0800 | [diff] [blame] | 43 | #include <asm/cputhreads.h> |
Scott Wood | 7a25d91 | 2016-03-15 01:47:38 -0500 | [diff] [blame] | 44 | #include <asm/ppc-opcode.h> |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 45 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 46 | /* The physical memory is laid out such that the secondary processor |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 47 | * spin code sits at 0x0000...0x00ff. On server, the vectors follow |
| 48 | * using the layout described in exceptions-64s.S |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 49 | */ |
| 50 | |
| 51 | /* |
| 52 | * Entering into this code we make the following assumptions: |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 53 | * |
| 54 | * For pSeries or server processors: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 55 | * 1. The MMU is off & open firmware is running in real mode. |
| 56 | * 2. The kernel is entered at __start |
Benjamin Herrenschmidt | 27f44888 | 2011-09-19 18:27:58 +0000 | [diff] [blame] | 57 | * -or- For OPAL entry: |
| 58 | * 1. The MMU is off, processor in HV mode, primary CPU enters at 0 |
Benjamin Herrenschmidt | daea117 | 2011-09-19 17:44:59 +0000 | [diff] [blame] | 59 | * with device-tree in gpr3. We also get OPAL base in r8 and |
| 60 | * entry in r9 for debugging purposes |
Benjamin Herrenschmidt | 27f44888 | 2011-09-19 18:27:58 +0000 | [diff] [blame] | 61 | * 2. Secondary processors enter at 0x60 with PIR in gpr3 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 62 | * |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 63 | * For Book3E processors: |
| 64 | * 1. The MMU is on running in AS0 in a state defined in ePAPR |
| 65 | * 2. The kernel is entered at __start |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 66 | */ |
| 67 | |
| 68 | .text |
| 69 | .globl _stext |
| 70 | _stext: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 71 | _GLOBAL(__start) |
| 72 | /* NOP this out unconditionally */ |
| 73 | BEGIN_FTR_SECTION |
Benjamin Herrenschmidt | 5c0484e | 2013-09-23 12:04:45 +1000 | [diff] [blame] | 74 | FIXUP_ENDIAN |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 75 | b __start_initialization_multiplatform |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 76 | END_FTR_SECTION(0, 1) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 77 | |
| 78 | /* Catch branch to 0 in real mode */ |
| 79 | trap |
| 80 | |
Anton Blanchard | 2751b62 | 2014-03-11 11:54:06 +1100 | [diff] [blame] | 81 | /* Secondary processors spin on this value until it becomes non-zero. |
| 82 | * When non-zero, it contains the real address of the function the cpu |
| 83 | * should jump to. |
Paul Mackerras | 1f6a93e | 2008-08-30 11:40:24 +1000 | [diff] [blame] | 84 | */ |
Olof Johansson | 7d4151b | 2013-12-28 13:01:47 -0800 | [diff] [blame] | 85 | .balign 8 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 86 | .globl __secondary_hold_spinloop |
| 87 | __secondary_hold_spinloop: |
| 88 | .llong 0x0 |
| 89 | |
| 90 | /* Secondary processors write this value with their cpu # */ |
| 91 | /* after they enter the spin loop immediately below. */ |
| 92 | .globl __secondary_hold_acknowledge |
| 93 | __secondary_hold_acknowledge: |
| 94 | .llong 0x0 |
| 95 | |
Sonny Rao | 928a319 | 2010-11-18 00:35:07 +0000 | [diff] [blame] | 96 | #ifdef CONFIG_RELOCATABLE |
Milton Miller | 8b8b0cc | 2008-10-23 18:41:09 +0000 | [diff] [blame] | 97 | /* This flag is set to 1 by a loader if the kernel should run |
| 98 | * at the loaded address instead of the linked address. This |
| 99 | * is used by kexec-tools to keep the the kdump kernel in the |
| 100 | * crash_kernel region. The loader is responsible for |
| 101 | * observing the alignment requirement. |
| 102 | */ |
| 103 | /* Do not move this variable as kexec-tools knows about it. */ |
| 104 | . = 0x5c |
| 105 | .globl __run_at_load |
| 106 | __run_at_load: |
| 107 | .long 0x72756e30 /* "run0" -- relocate to 0 by default */ |
| 108 | #endif |
| 109 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 110 | . = 0x60 |
| 111 | /* |
Geoff Levand | 75423b7 | 2007-06-16 08:06:23 +1000 | [diff] [blame] | 112 | * The following code is used to hold secondary processors |
| 113 | * in a spin loop after they have entered the kernel, but |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 114 | * before the bulk of the kernel has been relocated. This code |
| 115 | * is relocated to physical address 0x60 before prom_init is run. |
| 116 | * All of it must fit below the first exception vector at 0x100. |
Paul Mackerras | 1f6a93e | 2008-08-30 11:40:24 +1000 | [diff] [blame] | 117 | * Use .globl here not _GLOBAL because we want __secondary_hold |
| 118 | * to be the actual text address, not a descriptor. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 119 | */ |
Paul Mackerras | 1f6a93e | 2008-08-30 11:40:24 +1000 | [diff] [blame] | 120 | .globl __secondary_hold |
| 121 | __secondary_hold: |
Benjamin Herrenschmidt | 5c0484e | 2013-09-23 12:04:45 +1000 | [diff] [blame] | 122 | FIXUP_ENDIAN |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 123 | #ifndef CONFIG_PPC_BOOK3E |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 124 | mfmsr r24 |
| 125 | ori r24,r24,MSR_RI |
| 126 | mtmsrd r24 /* RI on */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 127 | #endif |
Anton Blanchard | f1870f7 | 2006-02-13 18:11:13 +1100 | [diff] [blame] | 128 | /* Grab our physical cpu number */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 129 | mr r24,r3 |
Jimi Xenidis | 96f013f | 2012-12-03 17:05:47 +0000 | [diff] [blame] | 130 | /* stash r4 for book3e */ |
| 131 | mr r25,r4 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 132 | |
| 133 | /* Tell the master cpu we're here */ |
| 134 | /* Relocation is off & we are located at an address less */ |
| 135 | /* than 0x100, so only need to grab low order offset. */ |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 136 | std r24,__secondary_hold_acknowledge-_stext(0) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 137 | sync |
| 138 | |
Jimi Xenidis | 96f013f | 2012-12-03 17:05:47 +0000 | [diff] [blame] | 139 | li r26,0 |
| 140 | #ifdef CONFIG_PPC_BOOK3E |
| 141 | tovirt(r26,r26) |
| 142 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 143 | /* All secondary cpus wait here until told to start. */ |
Anton Blanchard | cc7efbf | 2014-02-04 16:07:47 +1100 | [diff] [blame] | 144 | 100: ld r12,__secondary_hold_spinloop-_stext(r26) |
| 145 | cmpdi 0,r12,0 |
Paul Mackerras | 1f6a93e | 2008-08-30 11:40:24 +1000 | [diff] [blame] | 146 | beq 100b |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 147 | |
Anton Blanchard | f1870f7 | 2006-02-13 18:11:13 +1100 | [diff] [blame] | 148 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
Jimi Xenidis | 96f013f | 2012-12-03 17:05:47 +0000 | [diff] [blame] | 149 | #ifdef CONFIG_PPC_BOOK3E |
Anton Blanchard | cc7efbf | 2014-02-04 16:07:47 +1100 | [diff] [blame] | 150 | tovirt(r12,r12) |
Jimi Xenidis | 96f013f | 2012-12-03 17:05:47 +0000 | [diff] [blame] | 151 | #endif |
Anton Blanchard | cc7efbf | 2014-02-04 16:07:47 +1100 | [diff] [blame] | 152 | mtctr r12 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 153 | mr r3,r24 |
Jimi Xenidis | 96f013f | 2012-12-03 17:05:47 +0000 | [diff] [blame] | 154 | /* |
| 155 | * it may be the case that other platforms have r4 right to |
| 156 | * begin with, this gives us some safety in case it is not |
| 157 | */ |
| 158 | #ifdef CONFIG_PPC_BOOK3E |
| 159 | mr r4,r25 |
| 160 | #else |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 161 | li r4,0 |
Jimi Xenidis | 96f013f | 2012-12-03 17:05:47 +0000 | [diff] [blame] | 162 | #endif |
Benjamin Herrenschmidt | dd79773 | 2011-04-05 14:34:58 +1000 | [diff] [blame] | 163 | /* Make sure that patched code is visible */ |
| 164 | isync |
Michael Ellerman | 758438a | 2005-12-05 15:49:00 -0600 | [diff] [blame] | 165 | bctr |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 166 | #else |
| 167 | BUG_OPCODE |
| 168 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 169 | |
| 170 | /* This value is used to mark exception frames on the stack. */ |
| 171 | .section ".toc","aw" |
| 172 | exception_marker: |
| 173 | .tc ID_72656773_68657265[TC],0x7265677368657265 |
| 174 | .text |
| 175 | |
| 176 | /* |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 177 | * On server, we include the exception vectors code here as it |
| 178 | * relies on absolute addressing which is only possible within |
| 179 | * this compilation unit |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 180 | */ |
Benjamin Herrenschmidt | 0ebc4cd | 2009-06-02 21:17:38 +0000 | [diff] [blame] | 181 | #ifdef CONFIG_PPC_BOOK3S |
| 182 | #include "exceptions-64s.S" |
Paul Mackerras | 1f6a93e | 2008-08-30 11:40:24 +1000 | [diff] [blame] | 183 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 184 | |
Andy Fleming | e16c876 | 2011-12-08 01:20:27 -0600 | [diff] [blame] | 185 | #ifdef CONFIG_PPC_BOOK3E |
chenhui zhao | d17799f | 2015-11-20 17:13:59 +0800 | [diff] [blame] | 186 | /* |
chenhui zhao | 6becef7 | 2015-11-20 17:14:02 +0800 | [diff] [blame] | 187 | * The booting_thread_hwid holds the thread id we want to boot in cpu |
| 188 | * hotplug case. It is set by cpu hotplug code, and is invalid by default. |
| 189 | * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID] |
| 190 | * bit field. |
| 191 | */ |
| 192 | .globl booting_thread_hwid |
| 193 | booting_thread_hwid: |
| 194 | .long INVALID_THREAD_HWID |
| 195 | .align 3 |
| 196 | /* |
| 197 | * start a thread in the same core |
| 198 | * input parameters: |
| 199 | * r3 = the thread physical id |
| 200 | * r4 = the entry point where thread starts |
| 201 | */ |
| 202 | _GLOBAL(book3e_start_thread) |
| 203 | LOAD_REG_IMMEDIATE(r5, MSR_KERNEL) |
| 204 | cmpi 0, r3, 0 |
| 205 | beq 10f |
| 206 | cmpi 0, r3, 1 |
| 207 | beq 11f |
| 208 | /* If the thread id is invalid, just exit. */ |
| 209 | b 13f |
| 210 | 10: |
Scott Wood | 7a25d91 | 2016-03-15 01:47:38 -0500 | [diff] [blame] | 211 | MTTMR(TMRN_IMSR0, 5) |
| 212 | MTTMR(TMRN_INIA0, 4) |
chenhui zhao | 6becef7 | 2015-11-20 17:14:02 +0800 | [diff] [blame] | 213 | b 12f |
| 214 | 11: |
Scott Wood | 7a25d91 | 2016-03-15 01:47:38 -0500 | [diff] [blame] | 215 | MTTMR(TMRN_IMSR1, 5) |
| 216 | MTTMR(TMRN_INIA1, 4) |
chenhui zhao | 6becef7 | 2015-11-20 17:14:02 +0800 | [diff] [blame] | 217 | 12: |
| 218 | isync |
| 219 | li r6, 1 |
| 220 | sld r6, r6, r3 |
| 221 | mtspr SPRN_TENS, r6 |
| 222 | 13: |
| 223 | blr |
| 224 | |
| 225 | /* |
chenhui zhao | d17799f | 2015-11-20 17:13:59 +0800 | [diff] [blame] | 226 | * stop a thread in the same core |
| 227 | * input parameter: |
| 228 | * r3 = the thread physical id |
| 229 | */ |
| 230 | _GLOBAL(book3e_stop_thread) |
| 231 | cmpi 0, r3, 0 |
| 232 | beq 10f |
| 233 | cmpi 0, r3, 1 |
| 234 | beq 10f |
| 235 | /* If the thread id is invalid, just exit. */ |
| 236 | b 13f |
| 237 | 10: |
| 238 | li r4, 1 |
| 239 | sld r4, r4, r3 |
| 240 | mtspr SPRN_TENC, r4 |
| 241 | 13: |
| 242 | blr |
| 243 | |
Andy Fleming | e16c876 | 2011-12-08 01:20:27 -0600 | [diff] [blame] | 244 | _GLOBAL(fsl_secondary_thread_init) |
Scott Wood | f34b3e1 | 2015-10-06 22:48:12 -0500 | [diff] [blame] | 245 | mfspr r4,SPRN_BUCSR |
| 246 | |
Andy Fleming | e16c876 | 2011-12-08 01:20:27 -0600 | [diff] [blame] | 247 | /* Enable branch prediction */ |
| 248 | lis r3,BUCSR_INIT@h |
| 249 | ori r3,r3,BUCSR_INIT@l |
| 250 | mtspr SPRN_BUCSR,r3 |
| 251 | isync |
| 252 | |
| 253 | /* |
| 254 | * Fix PIR to match the linear numbering in the device tree. |
| 255 | * |
| 256 | * On e6500, the reset value of PIR uses the low three bits for |
| 257 | * the thread within a core, and the upper bits for the core |
| 258 | * number. There are two threads per core, so shift everything |
| 259 | * but the low bit right by two bits so that the cpu numbering is |
| 260 | * continuous. |
Scott Wood | f34b3e1 | 2015-10-06 22:48:12 -0500 | [diff] [blame] | 261 | * |
| 262 | * If the old value of BUCSR is non-zero, this thread has run |
| 263 | * before. Thus, we assume we are coming from kexec or a similar |
| 264 | * scenario, and PIR is already set to the correct value. This |
| 265 | * is a bit of a hack, but there are limited opportunities for |
| 266 | * getting information into the thread and the alternatives |
| 267 | * seemed like they'd be overkill. We can't tell just by looking |
| 268 | * at the old PIR value which state it's in, since the same value |
| 269 | * could be valid for one thread out of reset and for a different |
| 270 | * thread in Linux. |
Andy Fleming | e16c876 | 2011-12-08 01:20:27 -0600 | [diff] [blame] | 271 | */ |
Scott Wood | f34b3e1 | 2015-10-06 22:48:12 -0500 | [diff] [blame] | 272 | |
Andy Fleming | e16c876 | 2011-12-08 01:20:27 -0600 | [diff] [blame] | 273 | mfspr r3, SPRN_PIR |
Scott Wood | f34b3e1 | 2015-10-06 22:48:12 -0500 | [diff] [blame] | 274 | cmpwi r4,0 |
| 275 | bne 1f |
Andy Fleming | e16c876 | 2011-12-08 01:20:27 -0600 | [diff] [blame] | 276 | rlwimi r3, r3, 30, 2, 30 |
| 277 | mtspr SPRN_PIR, r3 |
Scott Wood | f34b3e1 | 2015-10-06 22:48:12 -0500 | [diff] [blame] | 278 | 1: |
Andy Fleming | e16c876 | 2011-12-08 01:20:27 -0600 | [diff] [blame] | 279 | #endif |
| 280 | |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 281 | _GLOBAL(generic_secondary_thread_init) |
| 282 | mr r24,r3 |
| 283 | |
| 284 | /* turn on 64-bit mode */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 285 | bl enable_64b_mode |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 286 | |
| 287 | /* get a valid TOC pointer, wherever we're mapped at */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 288 | bl relative_toc |
Anton Blanchard | 1fbe9cf | 2012-11-26 17:41:08 +0000 | [diff] [blame] | 289 | tovirt(r2,r2) |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 290 | |
| 291 | #ifdef CONFIG_PPC_BOOK3E |
| 292 | /* Book3E initialization */ |
| 293 | mr r3,r24 |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 294 | bl book3e_secondary_thread_init |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 295 | #endif |
| 296 | b generic_secondary_common_init |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 297 | |
| 298 | /* |
Olof Johansson | f39b7a5 | 2006-08-11 00:07:08 -0500 | [diff] [blame] | 299 | * On pSeries and most other platforms, secondary processors spin |
| 300 | * in the following code. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 301 | * At entry, r3 = this processor's number (physical cpu id) |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 302 | * |
| 303 | * On Book3E, r4 = 1 to indicate that the initial TLB entry for |
| 304 | * this core already exists (setup via some other mechanism such |
| 305 | * as SCOM before entry). |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 306 | */ |
Olof Johansson | f39b7a5 | 2006-08-11 00:07:08 -0500 | [diff] [blame] | 307 | _GLOBAL(generic_secondary_smp_init) |
Benjamin Herrenschmidt | 5c0484e | 2013-09-23 12:04:45 +1000 | [diff] [blame] | 308 | FIXUP_ENDIAN |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 309 | mr r24,r3 |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 310 | mr r25,r4 |
| 311 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 312 | /* turn on 64-bit mode */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 313 | bl enable_64b_mode |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 314 | |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 315 | /* get a valid TOC pointer, wherever we're mapped at */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 316 | bl relative_toc |
Anton Blanchard | 1fbe9cf | 2012-11-26 17:41:08 +0000 | [diff] [blame] | 317 | tovirt(r2,r2) |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 318 | |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 319 | #ifdef CONFIG_PPC_BOOK3E |
| 320 | /* Book3E initialization */ |
| 321 | mr r3,r24 |
| 322 | mr r4,r25 |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 323 | bl book3e_secondary_core_init |
chenhui zhao | 6becef7 | 2015-11-20 17:14:02 +0800 | [diff] [blame] | 324 | |
| 325 | /* |
| 326 | * After common core init has finished, check if the current thread is the |
| 327 | * one we wanted to boot. If not, start the specified thread and stop the |
| 328 | * current thread. |
| 329 | */ |
| 330 | LOAD_REG_ADDR(r4, booting_thread_hwid) |
| 331 | lwz r3, 0(r4) |
| 332 | li r5, INVALID_THREAD_HWID |
| 333 | cmpw r3, r5 |
| 334 | beq 20f |
| 335 | |
| 336 | /* |
| 337 | * The value of booting_thread_hwid has been stored in r3, |
| 338 | * so make it invalid. |
| 339 | */ |
| 340 | stw r5, 0(r4) |
| 341 | |
| 342 | /* |
| 343 | * Get the current thread id and check if it is the one we wanted. |
| 344 | * If not, start the one specified in booting_thread_hwid and stop |
| 345 | * the current thread. |
| 346 | */ |
| 347 | mfspr r8, SPRN_TIR |
| 348 | cmpw r3, r8 |
| 349 | beq 20f |
| 350 | |
| 351 | /* start the specified thread */ |
| 352 | LOAD_REG_ADDR(r5, fsl_secondary_thread_init) |
| 353 | ld r4, 0(r5) |
| 354 | bl book3e_start_thread |
| 355 | |
| 356 | /* stop the current thread */ |
| 357 | mr r3, r8 |
| 358 | bl book3e_stop_thread |
| 359 | 10: |
| 360 | b 10b |
| 361 | 20: |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 362 | #endif |
| 363 | |
| 364 | generic_secondary_common_init: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 365 | /* Set up a paca value for this processor. Since we have the |
| 366 | * physical cpu id in r24, we need to search the pacas to find |
| 367 | * which logical id maps to our physical one. |
| 368 | */ |
Michael Ellerman | 1426d5a | 2010-01-28 13:23:22 +0000 | [diff] [blame] | 369 | LOAD_REG_ADDR(r13, paca) /* Load paca pointer */ |
| 370 | ld r13,0(r13) /* Get base vaddr of paca array */ |
Milton Miller | 768d18a | 2011-05-10 19:28:37 +0000 | [diff] [blame] | 371 | #ifndef CONFIG_SMP |
| 372 | addi r13,r13,PACA_SIZE /* know r13 if used accidentally */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 373 | b kexec_wait /* wait for next kernel if !SMP */ |
Milton Miller | 768d18a | 2011-05-10 19:28:37 +0000 | [diff] [blame] | 374 | #else |
| 375 | LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ |
| 376 | lwz r7,0(r7) /* also the max paca allocated */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 377 | li r5,0 /* logical cpu id */ |
| 378 | 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ |
| 379 | cmpw r6,r24 /* Compare to our id */ |
| 380 | beq 2f |
| 381 | addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ |
| 382 | addi r5,r5,1 |
Milton Miller | 768d18a | 2011-05-10 19:28:37 +0000 | [diff] [blame] | 383 | cmpw r5,r7 /* Check if more pacas exist */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 384 | blt 1b |
| 385 | |
| 386 | mr r3,r24 /* not found, copy phys to r3 */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 387 | b kexec_wait /* next kernel might do better */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 388 | |
Benjamin Herrenschmidt | 2dd60d7 | 2011-01-20 17:50:21 +1100 | [diff] [blame] | 389 | 2: SET_PACA(r13) |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 390 | #ifdef CONFIG_PPC_BOOK3E |
| 391 | addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ |
| 392 | mtspr SPRN_SPRG_TLB_EXFRAME,r12 |
| 393 | #endif |
| 394 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 395 | /* From now on, r24 is expected to be logical cpuid */ |
| 396 | mr r24,r5 |
Sonny Rao | b6f6b98 | 2008-07-12 09:00:26 +1000 | [diff] [blame] | 397 | |
Olof Johansson | f39b7a5 | 2006-08-11 00:07:08 -0500 | [diff] [blame] | 398 | /* See if we need to call a cpu state restore handler */ |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 399 | LOAD_REG_ADDR(r23, cur_cpu_spec) |
Olof Johansson | f39b7a5 | 2006-08-11 00:07:08 -0500 | [diff] [blame] | 400 | ld r23,0(r23) |
Anton Blanchard | 2751b62 | 2014-03-11 11:54:06 +1100 | [diff] [blame] | 401 | ld r12,CPU_SPEC_RESTORE(r23) |
| 402 | cmpdi 0,r12,0 |
Benjamin Herrenschmidt | 9d07bc8 | 2011-03-16 14:54:35 +1100 | [diff] [blame] | 403 | beq 3f |
Anton Blanchard | 2751b62 | 2014-03-11 11:54:06 +1100 | [diff] [blame] | 404 | #if !defined(_CALL_ELF) || _CALL_ELF != 2 |
| 405 | ld r12,0(r12) |
| 406 | #endif |
Anton Blanchard | cc7efbf | 2014-02-04 16:07:47 +1100 | [diff] [blame] | 407 | mtctr r12 |
Olof Johansson | f39b7a5 | 2006-08-11 00:07:08 -0500 | [diff] [blame] | 408 | bctrl |
| 409 | |
Matt Evans | 7ac87ab | 2011-05-25 18:09:12 +0000 | [diff] [blame] | 410 | 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ |
Benjamin Herrenschmidt | 9d07bc8 | 2011-03-16 14:54:35 +1100 | [diff] [blame] | 411 | lwarx r4,0,r3 |
| 412 | subi r4,r4,1 |
| 413 | stwcx. r4,0,r3 |
| 414 | bne 3b |
| 415 | isync |
| 416 | |
| 417 | 4: HMT_LOW |
Benjamin Herrenschmidt | ad0693e | 2011-02-01 12:13:09 +1100 | [diff] [blame] | 418 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ |
| 419 | /* start. */ |
Benjamin Herrenschmidt | ad0693e | 2011-02-01 12:13:09 +1100 | [diff] [blame] | 420 | cmpwi 0,r23,0 |
Benjamin Herrenschmidt | 9d07bc8 | 2011-03-16 14:54:35 +1100 | [diff] [blame] | 421 | beq 4b /* Loop until told to go */ |
Benjamin Herrenschmidt | ad0693e | 2011-02-01 12:13:09 +1100 | [diff] [blame] | 422 | |
| 423 | sync /* order paca.run and cur_cpu_spec */ |
Benjamin Herrenschmidt | 9d07bc8 | 2011-03-16 14:54:35 +1100 | [diff] [blame] | 424 | isync /* In case code patching happened */ |
Benjamin Herrenschmidt | ad0693e | 2011-02-01 12:13:09 +1100 | [diff] [blame] | 425 | |
Benjamin Herrenschmidt | 9d07bc8 | 2011-03-16 14:54:35 +1100 | [diff] [blame] | 426 | /* Create a temp kernel stack for use before relocation is on. */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 427 | ld r1,PACAEMERGSP(r13) |
| 428 | subi r1,r1,STACK_FRAME_OVERHEAD |
| 429 | |
Stephen Rothwell | c705677 | 2006-11-27 14:59:50 +1100 | [diff] [blame] | 430 | b __secondary_start |
Milton Miller | 768d18a | 2011-05-10 19:28:37 +0000 | [diff] [blame] | 431 | #endif /* SMP */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 432 | |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 433 | /* |
| 434 | * Turn the MMU off. |
| 435 | * Assumes we're mapped EA == RA if the MMU is on. |
| 436 | */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 437 | #ifdef CONFIG_PPC_BOOK3S |
Anton Blanchard | 6a3bab9 | 2014-02-04 16:06:11 +1100 | [diff] [blame] | 438 | __mmu_off: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 439 | mfmsr r3 |
| 440 | andi. r0,r3,MSR_IR|MSR_DR |
| 441 | beqlr |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 442 | mflr r4 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 443 | andc r3,r3,r0 |
| 444 | mtspr SPRN_SRR0,r4 |
| 445 | mtspr SPRN_SRR1,r3 |
| 446 | sync |
| 447 | rfid |
| 448 | b . /* prevent speculative execution */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 449 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 450 | |
| 451 | |
| 452 | /* |
| 453 | * Here is our main kernel entry point. We support currently 2 kind of entries |
| 454 | * depending on the value of r5. |
| 455 | * |
| 456 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content |
| 457 | * in r3...r7 |
| 458 | * |
| 459 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the |
| 460 | * DT block, r4 is a physical pointer to the kernel itself |
| 461 | * |
| 462 | */ |
Anton Blanchard | 6a3bab9 | 2014-02-04 16:06:11 +1100 | [diff] [blame] | 463 | __start_initialization_multiplatform: |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 464 | /* Make sure we are running in 64 bits mode */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 465 | bl enable_64b_mode |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 466 | |
| 467 | /* Get TOC pointer (current runtime address) */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 468 | bl relative_toc |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 469 | |
| 470 | /* find out where we are now */ |
| 471 | bcl 20,31,$+4 |
| 472 | 0: mflr r26 /* r26 = runtime addr here */ |
| 473 | addis r26,r26,(_stext - 0b)@ha |
| 474 | addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ |
| 475 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 476 | /* |
| 477 | * Are we booted from a PROM Of-type client-interface ? |
| 478 | */ |
| 479 | cmpldi cr0,r5,0 |
Stephen Rothwell | 939e60f6 | 2007-07-31 16:44:13 +1000 | [diff] [blame] | 480 | beq 1f |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 481 | b __boot_from_prom /* yes -> prom */ |
Stephen Rothwell | 939e60f6 | 2007-07-31 16:44:13 +1000 | [diff] [blame] | 482 | 1: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 483 | /* Save parameters */ |
| 484 | mr r31,r3 |
| 485 | mr r30,r4 |
Benjamin Herrenschmidt | daea117 | 2011-09-19 17:44:59 +0000 | [diff] [blame] | 486 | #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL |
| 487 | /* Save OPAL entry */ |
| 488 | mr r28,r8 |
| 489 | mr r29,r9 |
| 490 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 491 | |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 492 | #ifdef CONFIG_PPC_BOOK3E |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 493 | bl start_initialization_book3e |
| 494 | b __after_prom_start |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 495 | #else |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 496 | /* Setup some critical 970 SPRs before switching MMU off */ |
Olof Johansson | f39b7a5 | 2006-08-11 00:07:08 -0500 | [diff] [blame] | 497 | mfspr r0,SPRN_PVR |
| 498 | srwi r0,r0,16 |
| 499 | cmpwi r0,0x39 /* 970 */ |
| 500 | beq 1f |
| 501 | cmpwi r0,0x3c /* 970FX */ |
| 502 | beq 1f |
| 503 | cmpwi r0,0x44 /* 970MP */ |
Olof Johansson | 190a24f | 2006-10-25 17:32:40 -0500 | [diff] [blame] | 504 | beq 1f |
| 505 | cmpwi r0,0x45 /* 970GX */ |
Olof Johansson | f39b7a5 | 2006-08-11 00:07:08 -0500 | [diff] [blame] | 506 | bne 2f |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 507 | 1: bl __cpu_preinit_ppc970 |
Olof Johansson | f39b7a5 | 2006-08-11 00:07:08 -0500 | [diff] [blame] | 508 | 2: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 509 | |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 510 | /* Switch off MMU if not already off */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 511 | bl __mmu_off |
| 512 | b __after_prom_start |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 513 | #endif /* CONFIG_PPC_BOOK3E */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 514 | |
Anton Blanchard | 6a3bab9 | 2014-02-04 16:06:11 +1100 | [diff] [blame] | 515 | __boot_from_prom: |
Benjamin Herrenschmidt | 28794d3 | 2009-03-10 17:53:27 +0000 | [diff] [blame] | 516 | #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 517 | /* Save parameters */ |
| 518 | mr r31,r3 |
| 519 | mr r30,r4 |
| 520 | mr r29,r5 |
| 521 | mr r28,r6 |
| 522 | mr r27,r7 |
| 523 | |
Olaf Hering | 6088857 | 2006-03-23 21:50:59 +0100 | [diff] [blame] | 524 | /* |
| 525 | * Align the stack to 16-byte boundary |
| 526 | * Depending on the size and layout of the ELF sections in the initial |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 527 | * boot binary, the stack pointer may be unaligned on PowerMac |
Olaf Hering | 6088857 | 2006-03-23 21:50:59 +0100 | [diff] [blame] | 528 | */ |
Linus Torvalds | c05b477 | 2006-03-04 15:00:45 -0800 | [diff] [blame] | 529 | rldicr r1,r1,0,59 |
| 530 | |
Paul Mackerras | 549e815 | 2008-08-30 11:43:47 +1000 | [diff] [blame] | 531 | #ifdef CONFIG_RELOCATABLE |
| 532 | /* Relocate code for where we are now */ |
| 533 | mr r3,r26 |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 534 | bl relocate |
Paul Mackerras | 549e815 | 2008-08-30 11:43:47 +1000 | [diff] [blame] | 535 | #endif |
| 536 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 537 | /* Restore parameters */ |
| 538 | mr r3,r31 |
| 539 | mr r4,r30 |
| 540 | mr r5,r29 |
| 541 | mr r6,r28 |
| 542 | mr r7,r27 |
| 543 | |
| 544 | /* Do all of the interaction with OF client interface */ |
Paul Mackerras | 549e815 | 2008-08-30 11:43:47 +1000 | [diff] [blame] | 545 | mr r8,r26 |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 546 | bl prom_init |
Benjamin Herrenschmidt | 28794d3 | 2009-03-10 17:53:27 +0000 | [diff] [blame] | 547 | #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ |
| 548 | |
| 549 | /* We never return. We also hit that trap if trying to boot |
| 550 | * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 551 | trap |
| 552 | |
Anton Blanchard | 6a3bab9 | 2014-02-04 16:06:11 +1100 | [diff] [blame] | 553 | __after_prom_start: |
Paul Mackerras | 549e815 | 2008-08-30 11:43:47 +1000 | [diff] [blame] | 554 | #ifdef CONFIG_RELOCATABLE |
| 555 | /* process relocations for the final address of the kernel */ |
| 556 | lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ |
| 557 | sldi r25,r25,32 |
Tiejun Chen | 1cb6e06 | 2015-10-06 22:48:15 -0500 | [diff] [blame] | 558 | #if defined(CONFIG_PPC_BOOK3E) |
| 559 | tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ |
| 560 | #endif |
Milton Miller | 8b8b0cc | 2008-10-23 18:41:09 +0000 | [diff] [blame] | 561 | lwz r7,__run_at_load-_stext(r26) |
Tiejun Chen | 1cb6e06 | 2015-10-06 22:48:15 -0500 | [diff] [blame] | 562 | #if defined(CONFIG_PPC_BOOK3E) |
| 563 | tophys(r26,r26) |
| 564 | #endif |
Sonny Rao | 928a319 | 2010-11-18 00:35:07 +0000 | [diff] [blame] | 565 | cmplwi cr0,r7,1 /* flagged to stay where we are ? */ |
Mohan Kumar M | 54622f1 | 2008-10-21 17:38:10 +0000 | [diff] [blame] | 566 | bne 1f |
| 567 | add r25,r25,r26 |
Mohan Kumar M | 54622f1 | 2008-10-21 17:38:10 +0000 | [diff] [blame] | 568 | 1: mr r3,r25 |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 569 | bl relocate |
Tiejun Chen | 1cb6e06 | 2015-10-06 22:48:15 -0500 | [diff] [blame] | 570 | #if defined(CONFIG_PPC_BOOK3E) |
| 571 | /* IVPR needs to be set after relocation. */ |
| 572 | bl init_core_book3e |
| 573 | #endif |
Paul Mackerras | 549e815 | 2008-08-30 11:43:47 +1000 | [diff] [blame] | 574 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 575 | |
| 576 | /* |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 577 | * We need to run with _stext at physical address PHYSICAL_START. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 578 | * This will leave some code in the first 256B of |
| 579 | * real memory, which are reserved for software use. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 580 | * |
| 581 | * Note: This process overwrites the OF exception vectors. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 582 | */ |
Paul Mackerras | 549e815 | 2008-08-30 11:43:47 +1000 | [diff] [blame] | 583 | li r3,0 /* target addr */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 584 | #ifdef CONFIG_PPC_BOOK3E |
Tiejun Chen | 835c031 | 2015-10-06 22:48:14 -0500 | [diff] [blame] | 585 | tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 586 | #endif |
Paul Mackerras | 549e815 | 2008-08-30 11:43:47 +1000 | [diff] [blame] | 587 | mr. r4,r26 /* In some cases the loader may */ |
Tiejun Chen | 835c031 | 2015-10-06 22:48:14 -0500 | [diff] [blame] | 588 | #if defined(CONFIG_PPC_BOOK3E) |
| 589 | tovirt(r4,r4) |
| 590 | #endif |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 591 | beq 9f /* have already put us at zero */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 592 | li r6,0x100 /* Start offset, the first 0x100 */ |
| 593 | /* bytes were copied earlier. */ |
| 594 | |
Anton Blanchard | 11ee7e9 | 2012-11-11 19:01:05 +0000 | [diff] [blame] | 595 | #ifdef CONFIG_RELOCATABLE |
Mohan Kumar M | 54622f1 | 2008-10-21 17:38:10 +0000 | [diff] [blame] | 596 | /* |
| 597 | * Check if the kernel has to be running as relocatable kernel based on the |
Milton Miller | 8b8b0cc | 2008-10-23 18:41:09 +0000 | [diff] [blame] | 598 | * variable __run_at_load, if it is set the kernel is treated as relocatable |
Mohan Kumar M | 54622f1 | 2008-10-21 17:38:10 +0000 | [diff] [blame] | 599 | * kernel, otherwise it will be moved to PHYSICAL_START |
| 600 | */ |
Tiejun Chen | 1cb6e06 | 2015-10-06 22:48:15 -0500 | [diff] [blame] | 601 | #if defined(CONFIG_PPC_BOOK3E) |
| 602 | tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ |
| 603 | #endif |
Milton Miller | 8b8b0cc | 2008-10-23 18:41:09 +0000 | [diff] [blame] | 604 | lwz r7,__run_at_load-_stext(r26) |
| 605 | cmplwi cr0,r7,1 |
Mohan Kumar M | 54622f1 | 2008-10-21 17:38:10 +0000 | [diff] [blame] | 606 | bne 3f |
| 607 | |
Tiejun Chen | 1cb6e06 | 2015-10-06 22:48:15 -0500 | [diff] [blame] | 608 | #ifdef CONFIG_PPC_BOOK3E |
| 609 | LOAD_REG_ADDR(r5, __end_interrupts) |
| 610 | LOAD_REG_ADDR(r11, _stext) |
| 611 | sub r5,r5,r11 |
| 612 | #else |
Michael Neuling | c1fb681 | 2012-11-02 17:21:43 +1100 | [diff] [blame] | 613 | /* just copy interrupts */ |
| 614 | LOAD_REG_IMMEDIATE(r5, __end_interrupts - _stext) |
Tiejun Chen | 1cb6e06 | 2015-10-06 22:48:15 -0500 | [diff] [blame] | 615 | #endif |
Mohan Kumar M | 54622f1 | 2008-10-21 17:38:10 +0000 | [diff] [blame] | 616 | b 5f |
| 617 | 3: |
| 618 | #endif |
| 619 | lis r5,(copy_to_here - _stext)@ha |
| 620 | addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ |
| 621 | |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 622 | bl copy_and_flush /* copy the first n bytes */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 623 | /* this includes the code being */ |
| 624 | /* executed here. */ |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 625 | addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */ |
Anton Blanchard | cc7efbf | 2014-02-04 16:07:47 +1100 | [diff] [blame] | 626 | addi r12,r8,(4f - _stext)@l /* that we just made */ |
| 627 | mtctr r12 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 628 | bctr |
| 629 | |
Anton Blanchard | 286e4f9 | 2013-12-23 12:19:51 +1100 | [diff] [blame] | 630 | .balign 8 |
Mohan Kumar M | 54622f1 | 2008-10-21 17:38:10 +0000 | [diff] [blame] | 631 | p_end: .llong _end - _stext |
| 632 | |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 633 | 4: /* Now copy the rest of the kernel up to _end */ |
| 634 | addis r5,r26,(p_end - _stext)@ha |
| 635 | ld r5,(p_end - _stext)@l(r5) /* get _end */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 636 | 5: bl copy_and_flush /* copy the rest */ |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 637 | |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 638 | 9: b start_here_multiplatform |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 639 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 640 | /* |
| 641 | * Copy routine used to copy the kernel to start at physical address 0 |
| 642 | * and flush and invalidate the caches as needed. |
| 643 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset |
| 644 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. |
| 645 | * |
| 646 | * Note: this routine *only* clobbers r0, r6 and lr |
| 647 | */ |
| 648 | _GLOBAL(copy_and_flush) |
| 649 | addi r5,r5,-8 |
| 650 | addi r6,r6,-8 |
Olof Johansson | 5a2fe38 | 2006-09-06 14:34:41 -0500 | [diff] [blame] | 651 | 4: li r0,8 /* Use the smallest common */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 652 | /* denominator cache line */ |
| 653 | /* size. This results in */ |
| 654 | /* extra cache line flushes */ |
| 655 | /* but operation is correct. */ |
| 656 | /* Can't get cache line size */ |
| 657 | /* from NACA as it is being */ |
| 658 | /* moved too. */ |
| 659 | |
| 660 | mtctr r0 /* put # words/line in ctr */ |
| 661 | 3: addi r6,r6,8 /* copy a cache line */ |
| 662 | ldx r0,r6,r4 |
| 663 | stdx r0,r6,r3 |
| 664 | bdnz 3b |
| 665 | dcbst r6,r3 /* write it to memory */ |
| 666 | sync |
| 667 | icbi r6,r3 /* flush the icache line */ |
| 668 | cmpld 0,r6,r5 |
| 669 | blt 4b |
| 670 | sync |
| 671 | addi r5,r5,8 |
| 672 | addi r6,r6,8 |
Michael Neuling | 29ce3c5 | 2013-04-24 00:30:09 +0000 | [diff] [blame] | 673 | isync |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 674 | blr |
| 675 | |
| 676 | .align 8 |
| 677 | copy_to_here: |
| 678 | |
| 679 | #ifdef CONFIG_SMP |
| 680 | #ifdef CONFIG_PPC_PMAC |
| 681 | /* |
| 682 | * On PowerMac, secondary processors starts from the reset vector, which |
| 683 | * is temporarily turned into a call to one of the functions below. |
| 684 | */ |
| 685 | .section ".text"; |
| 686 | .align 2 ; |
| 687 | |
Paul Mackerras | 35499c0 | 2005-10-22 16:02:39 +1000 | [diff] [blame] | 688 | .globl __secondary_start_pmac_0 |
| 689 | __secondary_start_pmac_0: |
| 690 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ |
| 691 | li r24,0 |
| 692 | b 1f |
| 693 | li r24,1 |
| 694 | b 1f |
| 695 | li r24,2 |
| 696 | b 1f |
| 697 | li r24,3 |
| 698 | 1: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 699 | |
| 700 | _GLOBAL(pmac_secondary_start) |
| 701 | /* turn on 64-bit mode */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 702 | bl enable_64b_mode |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 703 | |
Benjamin Herrenschmidt | c478b58 | 2009-01-11 19:03:45 +0000 | [diff] [blame] | 704 | li r0,0 |
| 705 | mfspr r3,SPRN_HID4 |
| 706 | rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ |
| 707 | sync |
| 708 | mtspr SPRN_HID4,r3 |
| 709 | isync |
| 710 | sync |
| 711 | slbia |
| 712 | |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 713 | /* get TOC pointer (real address) */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 714 | bl relative_toc |
Anton Blanchard | 1fbe9cf | 2012-11-26 17:41:08 +0000 | [diff] [blame] | 715 | tovirt(r2,r2) |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 716 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 717 | /* Copy some CPU settings from CPU 0 */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 718 | bl __restore_cpu_ppc970 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 719 | |
| 720 | /* pSeries do that early though I don't think we really need it */ |
| 721 | mfmsr r3 |
| 722 | ori r3,r3,MSR_RI |
| 723 | mtmsrd r3 /* RI on */ |
| 724 | |
| 725 | /* Set up a paca value for this processor. */ |
Michael Ellerman | 1426d5a | 2010-01-28 13:23:22 +0000 | [diff] [blame] | 726 | LOAD_REG_ADDR(r4,paca) /* Load paca pointer */ |
| 727 | ld r4,0(r4) /* Get base vaddr of paca array */ |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 728 | mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 729 | add r13,r13,r4 /* for this processor. */ |
Benjamin Herrenschmidt | 2dd60d7 | 2011-01-20 17:50:21 +1100 | [diff] [blame] | 730 | SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 731 | |
Benjamin Herrenschmidt | 62cc67b | 2011-02-21 16:49:58 +1100 | [diff] [blame] | 732 | /* Mark interrupts soft and hard disabled (they might be enabled |
| 733 | * in the PACA when doing hotplug) |
| 734 | */ |
| 735 | li r0,0 |
| 736 | stb r0,PACASOFTIRQEN(r13) |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 737 | li r0,PACA_IRQ_HARD_DIS |
| 738 | stb r0,PACAIRQHAPPENED(r13) |
Benjamin Herrenschmidt | 62cc67b | 2011-02-21 16:49:58 +1100 | [diff] [blame] | 739 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 740 | /* Create a temp kernel stack for use before relocation is on. */ |
| 741 | ld r1,PACAEMERGSP(r13) |
| 742 | subi r1,r1,STACK_FRAME_OVERHEAD |
| 743 | |
Stephen Rothwell | c705677 | 2006-11-27 14:59:50 +1100 | [diff] [blame] | 744 | b __secondary_start |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 745 | |
| 746 | #endif /* CONFIG_PPC_PMAC */ |
| 747 | |
| 748 | /* |
| 749 | * This function is called after the master CPU has released the |
| 750 | * secondary processors. The execution environment is relocation off. |
| 751 | * The paca for this processor has the following fields initialized at |
| 752 | * this point: |
| 753 | * 1. Processor number |
| 754 | * 2. Segment table pointer (virtual address) |
| 755 | * On entry the following are set: |
Benjamin Herrenschmidt | 4f8cf36 | 2012-02-28 13:44:58 +1100 | [diff] [blame] | 756 | * r1 = stack pointer (real addr of temp stack) |
Benjamin Herrenschmidt | ee43eb7 | 2009-07-14 20:52:54 +0000 | [diff] [blame] | 757 | * r24 = cpu# (in Linux terms) |
| 758 | * r13 = paca virtual address |
| 759 | * SPRG_PACA = paca virtual address |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 760 | */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 761 | .section ".text"; |
| 762 | .align 2 ; |
| 763 | |
Stephen Rothwell | fc68e86 | 2007-08-22 13:44:58 +1000 | [diff] [blame] | 764 | .globl __secondary_start |
Stephen Rothwell | c705677 | 2006-11-27 14:59:50 +1100 | [diff] [blame] | 765 | __secondary_start: |
Paul Mackerras | 799d604 | 2005-11-10 13:37:51 +1100 | [diff] [blame] | 766 | /* Set thread priority to MEDIUM */ |
| 767 | HMT_MEDIUM |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 768 | |
Benjamin Herrenschmidt | 4f8cf36 | 2012-02-28 13:44:58 +1100 | [diff] [blame] | 769 | /* Initialize the kernel stack */ |
David Gibson | e58c349 | 2006-01-13 14:56:25 +1100 | [diff] [blame] | 770 | LOAD_REG_ADDR(r3, current_set) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 771 | sldi r28,r24,3 /* get current_set[cpu#] */ |
Michael Neuling | 54a8340 | 2010-08-25 21:04:25 +0000 | [diff] [blame] | 772 | ldx r14,r3,r28 |
| 773 | addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD |
| 774 | std r14,PACAKSAVE(r13) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 775 | |
Michael Ellerman | 376af59 | 2014-07-10 12:29:19 +1000 | [diff] [blame] | 776 | /* Do early setup for that CPU (SLB and hash table pointer) */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 777 | bl early_setup_secondary |
Matt Evans | f761622 | 2010-08-12 20:58:28 +0000 | [diff] [blame] | 778 | |
Michael Neuling | 54a8340 | 2010-08-25 21:04:25 +0000 | [diff] [blame] | 779 | /* |
| 780 | * setup the new stack pointer, but *don't* use this until |
| 781 | * translation is on. |
| 782 | */ |
| 783 | mr r1, r14 |
| 784 | |
Paul Mackerras | 799d604 | 2005-11-10 13:37:51 +1100 | [diff] [blame] | 785 | /* Clear backchain so we get nice backtraces */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 786 | li r7,0 |
| 787 | mtlr r7 |
| 788 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 789 | /* Mark interrupts soft and hard disabled (they might be enabled |
| 790 | * in the PACA when doing hotplug) |
| 791 | */ |
Benjamin Herrenschmidt | 4f8cf36 | 2012-02-28 13:44:58 +1100 | [diff] [blame] | 792 | stb r7,PACASOFTIRQEN(r13) |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 793 | li r0,PACA_IRQ_HARD_DIS |
| 794 | stb r0,PACAIRQHAPPENED(r13) |
Benjamin Herrenschmidt | 4f8cf36 | 2012-02-28 13:44:58 +1100 | [diff] [blame] | 795 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 796 | /* enable MMU and jump to start_secondary */ |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 797 | LOAD_REG_ADDR(r3, start_secondary_prolog) |
David Gibson | e58c349 | 2006-01-13 14:56:25 +1100 | [diff] [blame] | 798 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) |
Paul Mackerras | d04c56f | 2006-10-04 16:47:49 +1000 | [diff] [blame] | 799 | |
Paul Mackerras | b5bbeb2 | 2005-10-10 14:01:07 +1000 | [diff] [blame] | 800 | mtspr SPRN_SRR0,r3 |
| 801 | mtspr SPRN_SRR1,r4 |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 802 | RFI |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 803 | b . /* prevent speculative execution */ |
| 804 | |
| 805 | /* |
| 806 | * Running with relocation on at this point. All we want to do is |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 807 | * zero the stack back-chain pointer and get the TOC virtual address |
| 808 | * before going into C code. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 809 | */ |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 810 | start_secondary_prolog: |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 811 | ld r2,PACATOC(r13) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 812 | li r3,0 |
| 813 | std r3,0(r1) /* Zero the stack frame pointer */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 814 | bl start_secondary |
Paul Mackerras | 799d604 | 2005-11-10 13:37:51 +1100 | [diff] [blame] | 815 | b . |
Vaidyanathan Srinivasan | 8dbce53 | 2010-03-01 02:58:09 +0000 | [diff] [blame] | 816 | /* |
| 817 | * Reset stack pointer and call start_secondary |
| 818 | * to continue with online operation when woken up |
| 819 | * from cede in cpu offline. |
| 820 | */ |
| 821 | _GLOBAL(start_secondary_resume) |
| 822 | ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ |
| 823 | li r3,0 |
| 824 | std r3,0(r1) /* Zero the stack frame pointer */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 825 | bl start_secondary |
Vaidyanathan Srinivasan | 8dbce53 | 2010-03-01 02:58:09 +0000 | [diff] [blame] | 826 | b . |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 827 | #endif |
| 828 | |
| 829 | /* |
| 830 | * This subroutine clobbers r11 and r12 |
| 831 | */ |
Anton Blanchard | 6a3bab9 | 2014-02-04 16:06:11 +1100 | [diff] [blame] | 832 | enable_64b_mode: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 833 | mfmsr r11 /* grab the current MSR */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 834 | #ifdef CONFIG_PPC_BOOK3E |
| 835 | oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ |
| 836 | mtmsr r11 |
| 837 | #else /* CONFIG_PPC_BOOK3E */ |
Michael Ellerman | 9f0b079 | 2011-04-07 21:56:03 +0000 | [diff] [blame] | 838 | li r12,(MSR_64BIT | MSR_ISF)@highest |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 839 | sldi r12,r12,48 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 840 | or r11,r11,r12 |
| 841 | mtmsrd r11 |
| 842 | isync |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 843 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 844 | blr |
| 845 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 846 | /* |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 847 | * This puts the TOC pointer into r2, offset by 0x8000 (as expected |
| 848 | * by the toolchain). It computes the correct value for wherever we |
| 849 | * are running at the moment, using position-independent code. |
Anton Blanchard | 1fbe9cf | 2012-11-26 17:41:08 +0000 | [diff] [blame] | 850 | * |
| 851 | * Note: The compiler constructs pointers using offsets from the |
| 852 | * TOC in -mcmodel=medium mode. After we relocate to 0 but before |
| 853 | * the MMU is on we need our TOC to be a virtual address otherwise |
| 854 | * these pointers will be real addresses which may get stored and |
| 855 | * accessed later with the MMU on. We use tovirt() at the call |
| 856 | * sites to handle this. |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 857 | */ |
| 858 | _GLOBAL(relative_toc) |
| 859 | mflr r0 |
| 860 | bcl 20,31,$+4 |
Benjamin Herrenschmidt | e550592 | 2011-09-19 17:44:51 +0000 | [diff] [blame] | 861 | 0: mflr r11 |
| 862 | ld r2,(p_toc - 0b)(r11) |
| 863 | add r2,r2,r11 |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 864 | mtlr r0 |
| 865 | blr |
| 866 | |
Anton Blanchard | 5b63fee | 2013-08-07 02:01:18 +1000 | [diff] [blame] | 867 | .balign 8 |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 868 | p_toc: .llong __toc_start + 0x8000 - 0b |
| 869 | |
| 870 | /* |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 871 | * This is where the main kernel code starts. |
| 872 | */ |
Anton Blanchard | 6a3bab9 | 2014-02-04 16:06:11 +1100 | [diff] [blame] | 873 | start_here_multiplatform: |
Anton Blanchard | 1fbe9cf | 2012-11-26 17:41:08 +0000 | [diff] [blame] | 874 | /* set up the TOC */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 875 | bl relative_toc |
Anton Blanchard | 1fbe9cf | 2012-11-26 17:41:08 +0000 | [diff] [blame] | 876 | tovirt(r2,r2) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 877 | |
| 878 | /* Clear out the BSS. It may have been done in prom_init, |
| 879 | * already but that's irrelevant since prom_init will soon |
| 880 | * be detached from the kernel completely. Besides, we need |
| 881 | * to clear it now for kexec-style entry. |
| 882 | */ |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 883 | LOAD_REG_ADDR(r11,__bss_stop) |
| 884 | LOAD_REG_ADDR(r8,__bss_start) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 885 | sub r11,r11,r8 /* bss size */ |
| 886 | addi r11,r11,7 /* round up to an even double word */ |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 887 | srdi. r11,r11,3 /* shift right by 3 */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 888 | beq 4f |
| 889 | addi r8,r8,-8 |
| 890 | li r0,0 |
| 891 | mtctr r11 /* zero this many doublewords */ |
| 892 | 3: stdu r0,8(r8) |
| 893 | bdnz 3b |
| 894 | 4: |
| 895 | |
Benjamin Herrenschmidt | daea117 | 2011-09-19 17:44:59 +0000 | [diff] [blame] | 896 | #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL |
| 897 | /* Setup OPAL entry */ |
Benjamin Herrenschmidt | ab7f961 | 2012-10-21 14:30:52 +0000 | [diff] [blame] | 898 | LOAD_REG_ADDR(r11, opal) |
Benjamin Herrenschmidt | daea117 | 2011-09-19 17:44:59 +0000 | [diff] [blame] | 899 | std r28,0(r11); |
| 900 | std r29,8(r11); |
| 901 | #endif |
| 902 | |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 903 | #ifndef CONFIG_PPC_BOOK3E |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 904 | mfmsr r6 |
| 905 | ori r6,r6,MSR_RI |
| 906 | mtmsrd r6 /* RI on */ |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 907 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 908 | |
Paul Mackerras | 549e815 | 2008-08-30 11:43:47 +1000 | [diff] [blame] | 909 | #ifdef CONFIG_RELOCATABLE |
| 910 | /* Save the physical address we're running at in kernstart_addr */ |
| 911 | LOAD_REG_ADDR(r4, kernstart_addr) |
| 912 | clrldi r0,r25,2 |
| 913 | std r0,0(r4) |
| 914 | #endif |
| 915 | |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 916 | /* The following gets the stack set up with the regs */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 917 | /* pointing to the real addr of the kernel stack. This is */ |
| 918 | /* all done to support the C function call below which sets */ |
| 919 | /* up the htab. This is done because we have relocated the */ |
| 920 | /* kernel but are still running in real mode. */ |
| 921 | |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 922 | LOAD_REG_ADDR(r3,init_thread_union) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 923 | |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 924 | /* set up a stack pointer */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 925 | addi r1,r3,THREAD_SIZE |
| 926 | li r0,0 |
| 927 | stdu r0,-STACK_FRAME_OVERHEAD(r1) |
| 928 | |
Michael Ellerman | 376af59 | 2014-07-10 12:29:19 +1000 | [diff] [blame] | 929 | /* |
| 930 | * Do very early kernel initializations, including initial hash table |
| 931 | * and SLB setup before we turn on relocation. |
| 932 | */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 933 | |
| 934 | /* Restore parameters passed from prom_init/kexec */ |
| 935 | mr r3,r31 |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 936 | bl early_setup /* also sets r13 and SPRG_PACA */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 937 | |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 938 | LOAD_REG_ADDR(r3, start_here_common) |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 939 | ld r4,PACAKMSR(r13) |
Paul Mackerras | b5bbeb2 | 2005-10-10 14:01:07 +1000 | [diff] [blame] | 940 | mtspr SPRN_SRR0,r3 |
| 941 | mtspr SPRN_SRR1,r4 |
Benjamin Herrenschmidt | 2d27cfd | 2009-07-23 23:15:59 +0000 | [diff] [blame] | 942 | RFI |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 943 | b . /* prevent speculative execution */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 944 | |
| 945 | /* This is where all platforms converge execution */ |
Anton Blanchard | ad0289e | 2014-02-04 16:04:52 +1100 | [diff] [blame] | 946 | |
| 947 | start_here_common: |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 948 | /* relocation is on at this point */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 949 | std r1,PACAKSAVE(r13) |
| 950 | |
Paul Mackerras | e31aa45 | 2008-08-30 11:41:12 +1000 | [diff] [blame] | 951 | /* Load the TOC (virtual address) */ |
| 952 | ld r2,PACATOC(r13) |
| 953 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 954 | /* Do more system initializations in virtual mode */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 955 | bl setup_system |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 956 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 957 | /* Mark interrupts soft and hard disabled (they might be enabled |
| 958 | * in the PACA when doing hotplug) |
| 959 | */ |
| 960 | li r0,0 |
| 961 | stb r0,PACASOFTIRQEN(r13) |
| 962 | li r0,PACA_IRQ_HARD_DIS |
| 963 | stb r0,PACAIRQHAPPENED(r13) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 964 | |
Benjamin Herrenschmidt | 7230c56 | 2012-03-06 18:27:59 +1100 | [diff] [blame] | 965 | /* Generic kernel entry */ |
Anton Blanchard | b1576fe | 2014-02-04 16:04:35 +1100 | [diff] [blame] | 966 | bl start_kernel |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 967 | |
Anton Blanchard | f1870f7 | 2006-02-13 18:11:13 +1100 | [diff] [blame] | 968 | /* Not reached */ |
| 969 | BUG_OPCODE |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 970 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 971 | /* |
| 972 | * We put a few things here that have to be page-aligned. |
| 973 | * This stuff goes at the beginning of the bss, which is page-aligned. |
| 974 | */ |
| 975 | .section ".bss" |
Aneesh Kumar K.V | 43a5c68 | 2016-04-29 23:26:26 +1000 | [diff] [blame] | 976 | /* |
| 977 | * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K. |
| 978 | * We will need to find a better way to fix this |
| 979 | */ |
| 980 | .align 16 |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 981 | |
| 982 | .globl swapper_pg_dir |
| 983 | swapper_pg_dir: |
Stephen Rothwell | ee7a76d | 2007-09-18 17:22:59 +1000 | [diff] [blame] | 984 | .space PGD_TABLE_SIZE |
Aneesh Kumar K.V | 43a5c68 | 2016-04-29 23:26:26 +1000 | [diff] [blame] | 985 | |
| 986 | .globl empty_zero_page |
| 987 | empty_zero_page: |
| 988 | .space PAGE_SIZE |