blob: b947e82bbeb1c287c60c24ee86a3f59936d2c821 [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
Arto Merilainende2ba662013-03-22 16:34:08 +02002 * Copyright (C) 2012-2013 Avionic Design GmbH
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00003 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
Arto Merilainende2ba662013-03-22 16:34:08 +02005 * Based on the KMS/FB CMA helpers
6 * Copyright (C) 2012 Analog Device Inc.
7 *
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
Thierry Reding986c58d2015-08-11 13:11:49 +020013#include <linux/console.h>
14
Arto Merilainende2ba662013-03-22 16:34:08 +020015#include "drm.h"
16#include "gem.h"
Daniel Stone0bc6af02018-03-30 15:11:26 +010017#include <drm/drm_gem_framebuffer_helper.h>
Arto Merilainende2ba662013-03-22 16:34:08 +020018
Archit Tanejab110ef32015-10-27 13:40:59 +053019#ifdef CONFIG_DRM_FBDEV_EMULATION
Arto Merilainende2ba662013-03-22 16:34:08 +020020static inline struct tegra_fbdev *to_tegra_fbdev(struct drm_fb_helper *helper)
21{
22 return container_of(helper, struct tegra_fbdev, base);
23}
Thierry Reding60c2f702013-10-31 13:28:50 +010024#endif
Arto Merilainende2ba662013-03-22 16:34:08 +020025
26struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
27 unsigned int index)
28{
Daniel Stone0bc6af02018-03-30 15:11:26 +010029 return to_tegra_bo(drm_gem_fb_get_obj(framebuffer, index));
Arto Merilainende2ba662013-03-22 16:34:08 +020030}
31
Thierry Redingdb7fbdf2013-10-07 09:47:58 +020032bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer)
33{
Daniel Stone0bc6af02018-03-30 15:11:26 +010034 struct tegra_bo *bo = tegra_fb_get_plane(framebuffer, 0);
Thierry Redingdb7fbdf2013-10-07 09:47:58 +020035
Daniel Stone0bc6af02018-03-30 15:11:26 +010036 if (bo->flags & TEGRA_BO_BOTTOM_UP)
Thierry Redingdb7fbdf2013-10-07 09:47:58 +020037 return true;
38
39 return false;
40}
41
Thierry Redingc134f012014-06-03 14:48:12 +020042int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
43 struct tegra_bo_tiling *tiling)
Thierry Reding773af772013-10-04 22:34:01 +020044{
Daniel Stone0bc6af02018-03-30 15:11:26 +010045 uint64_t modifier = framebuffer->modifier;
Thierry Reding773af772013-10-04 22:34:01 +020046
Thierry Reding268892c2017-10-12 16:39:20 +020047 switch (modifier) {
Thierry Reding4ae4b5c2018-03-15 16:45:45 +010048 case DRM_FORMAT_MOD_LINEAR:
49 tiling->mode = TEGRA_BO_TILING_MODE_PITCH;
50 tiling->value = 0;
51 break;
52
Thierry Reding268892c2017-10-12 16:39:20 +020053 case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED:
Alexandre Courbot5e911442016-11-08 16:50:42 +090054 tiling->mode = TEGRA_BO_TILING_MODE_TILED;
55 tiling->value = 0;
56 break;
57
Thierry Reding268892c2017-10-12 16:39:20 +020058 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0):
Alexandre Courbot5e911442016-11-08 16:50:42 +090059 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
Thierry Reding268892c2017-10-12 16:39:20 +020060 tiling->value = 0;
61 break;
62
63 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1):
64 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
65 tiling->value = 1;
66 break;
67
68 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2):
69 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
70 tiling->value = 2;
71 break;
72
73 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3):
74 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
75 tiling->value = 3;
76 break;
77
78 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4):
79 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
80 tiling->value = 4;
81 break;
82
83 case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5):
84 tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
85 tiling->value = 5;
Alexandre Courbot5e911442016-11-08 16:50:42 +090086 break;
87
88 default:
Thierry Reding4ae4b5c2018-03-15 16:45:45 +010089 return -EINVAL;
Alexandre Courbot5e911442016-11-08 16:50:42 +090090 }
Thierry Reding773af772013-10-04 22:34:01 +020091
Thierry Redingc134f012014-06-03 14:48:12 +020092 return 0;
Thierry Reding773af772013-10-04 22:34:01 +020093}
94
Ville Syrjälä4ecae782015-12-15 12:21:13 +010095static const struct drm_framebuffer_funcs tegra_fb_funcs = {
Daniel Stone5cb8b992018-03-30 15:11:29 +010096 .destroy = drm_gem_fb_destroy,
Daniel Stone0bc6af02018-03-30 15:11:26 +010097 .create_handle = drm_gem_fb_create_handle,
Arto Merilainende2ba662013-03-22 16:34:08 +020098};
99
Daniel Stonedbc33c72018-03-30 15:11:27 +0100100static struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm,
101 const struct drm_mode_fb_cmd2 *mode_cmd,
102 struct tegra_bo **planes,
103 unsigned int num_planes)
Arto Merilainende2ba662013-03-22 16:34:08 +0200104{
Daniel Stonedbc33c72018-03-30 15:11:27 +0100105 struct drm_framebuffer *fb;
Arto Merilainende2ba662013-03-22 16:34:08 +0200106 unsigned int i;
107 int err;
108
109 fb = kzalloc(sizeof(*fb), GFP_KERNEL);
110 if (!fb)
111 return ERR_PTR(-ENOMEM);
112
Daniel Stonedbc33c72018-03-30 15:11:27 +0100113 drm_helper_mode_fill_fb_struct(drm, fb, mode_cmd);
Arto Merilainende2ba662013-03-22 16:34:08 +0200114
Daniel Stonedbc33c72018-03-30 15:11:27 +0100115 for (i = 0; i < fb->format->num_planes; i++)
116 fb->obj[i] = &planes[i]->gem;
Arto Merilainende2ba662013-03-22 16:34:08 +0200117
Daniel Stonedbc33c72018-03-30 15:11:27 +0100118 err = drm_framebuffer_init(drm, fb, &tegra_fb_funcs);
Arto Merilainende2ba662013-03-22 16:34:08 +0200119 if (err < 0) {
120 dev_err(drm->dev, "failed to initialize framebuffer: %d\n",
121 err);
Arto Merilainende2ba662013-03-22 16:34:08 +0200122 kfree(fb);
123 return ERR_PTR(err);
124 }
125
126 return fb;
127}
128
Thierry Redingf9914212014-11-26 13:03:57 +0100129struct drm_framebuffer *tegra_fb_create(struct drm_device *drm,
130 struct drm_file *file,
Ville Syrjälä1eb834512015-11-11 19:11:29 +0200131 const struct drm_mode_fb_cmd2 *cmd)
Arto Merilainende2ba662013-03-22 16:34:08 +0200132{
133 unsigned int hsub, vsub, i;
134 struct tegra_bo *planes[4];
135 struct drm_gem_object *gem;
Daniel Stonedbc33c72018-03-30 15:11:27 +0100136 struct drm_framebuffer *fb;
Arto Merilainende2ba662013-03-22 16:34:08 +0200137 int err;
138
139 hsub = drm_format_horz_chroma_subsampling(cmd->pixel_format);
140 vsub = drm_format_vert_chroma_subsampling(cmd->pixel_format);
141
142 for (i = 0; i < drm_format_num_planes(cmd->pixel_format); i++) {
143 unsigned int width = cmd->width / (i ? hsub : 1);
144 unsigned int height = cmd->height / (i ? vsub : 1);
145 unsigned int size, bpp;
146
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100147 gem = drm_gem_object_lookup(file, cmd->handles[i]);
Arto Merilainende2ba662013-03-22 16:34:08 +0200148 if (!gem) {
149 err = -ENXIO;
150 goto unreference;
151 }
152
153 bpp = drm_format_plane_cpp(cmd->pixel_format, i);
154
155 size = (height - 1) * cmd->pitches[i] +
156 width * bpp + cmd->offsets[i];
157
158 if (gem->size < size) {
159 err = -EINVAL;
160 goto unreference;
161 }
162
163 planes[i] = to_tegra_bo(gem);
164 }
165
166 fb = tegra_fb_alloc(drm, cmd, planes, i);
167 if (IS_ERR(fb)) {
168 err = PTR_ERR(fb);
169 goto unreference;
170 }
171
Daniel Stonedbc33c72018-03-30 15:11:27 +0100172 return fb;
Arto Merilainende2ba662013-03-22 16:34:08 +0200173
174unreference:
175 while (i--)
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300176 drm_gem_object_put_unlocked(&planes[i]->gem);
Arto Merilainende2ba662013-03-22 16:34:08 +0200177
178 return ERR_PTR(err);
179}
180
Archit Tanejab110ef32015-10-27 13:40:59 +0530181#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingb8f3f502018-02-07 18:45:56 +0100182static int tegra_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
183{
184 struct drm_fb_helper *helper = info->par;
185 struct tegra_bo *bo;
186 int err;
187
188 bo = tegra_fb_get_plane(helper->fb, 0);
189
190 err = drm_gem_mmap_obj(&bo->gem, bo->gem.size, vma);
191 if (err < 0)
192 return err;
193
194 return __tegra_gem_mmap(&bo->gem, vma);
195}
196
Arto Merilainende2ba662013-03-22 16:34:08 +0200197static struct fb_ops tegra_fb_ops = {
198 .owner = THIS_MODULE,
Stefan Christ902c2552016-11-14 00:03:22 +0100199 DRM_FB_HELPER_DEFAULT_OPS,
Archit Taneja0f7d9052015-07-22 14:58:07 +0530200 .fb_fillrect = drm_fb_helper_sys_fillrect,
201 .fb_copyarea = drm_fb_helper_sys_copyarea,
202 .fb_imageblit = drm_fb_helper_sys_imageblit,
Thierry Redingb8f3f502018-02-07 18:45:56 +0100203 .fb_mmap = tegra_fb_mmap,
Arto Merilainende2ba662013-03-22 16:34:08 +0200204};
205
206static int tegra_fbdev_probe(struct drm_fb_helper *helper,
207 struct drm_fb_helper_surface_size *sizes)
208{
209 struct tegra_fbdev *fbdev = to_tegra_fbdev(helper);
Thierry Redingd1f3e1e2014-07-11 08:29:14 +0200210 struct tegra_drm *tegra = helper->dev->dev_private;
Arto Merilainende2ba662013-03-22 16:34:08 +0200211 struct drm_device *drm = helper->dev;
212 struct drm_mode_fb_cmd2 cmd = { 0 };
213 unsigned int bytes_per_pixel;
214 struct drm_framebuffer *fb;
215 unsigned long offset;
216 struct fb_info *info;
217 struct tegra_bo *bo;
218 size_t size;
219 int err;
220
221 bytes_per_pixel = DIV_ROUND_UP(sizes->surface_bpp, 8);
222
223 cmd.width = sizes->surface_width;
224 cmd.height = sizes->surface_height;
Thierry Redingd1f3e1e2014-07-11 08:29:14 +0200225 cmd.pitches[0] = round_up(sizes->surface_width * bytes_per_pixel,
226 tegra->pitch_align);
Thierry Reding71835ca2017-11-14 16:09:30 +0100227
Arto Merilainende2ba662013-03-22 16:34:08 +0200228 cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
229 sizes->surface_depth);
230
231 size = cmd.pitches[0] * cmd.height;
232
Thierry Reding773af772013-10-04 22:34:01 +0200233 bo = tegra_bo_create(drm, size, 0);
Arto Merilainende2ba662013-03-22 16:34:08 +0200234 if (IS_ERR(bo))
235 return PTR_ERR(bo);
236
Archit Taneja0f7d9052015-07-22 14:58:07 +0530237 info = drm_fb_helper_alloc_fbi(helper);
238 if (IS_ERR(info)) {
Arto Merilainende2ba662013-03-22 16:34:08 +0200239 dev_err(drm->dev, "failed to allocate framebuffer info\n");
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300240 drm_gem_object_put_unlocked(&bo->gem);
Archit Taneja0f7d9052015-07-22 14:58:07 +0530241 return PTR_ERR(info);
Arto Merilainende2ba662013-03-22 16:34:08 +0200242 }
243
244 fbdev->fb = tegra_fb_alloc(drm, &cmd, &bo, 1);
245 if (IS_ERR(fbdev->fb)) {
Arto Merilainende2ba662013-03-22 16:34:08 +0200246 err = PTR_ERR(fbdev->fb);
Thierry Redingcb10c812014-11-06 14:36:19 +0100247 dev_err(drm->dev, "failed to allocate DRM framebuffer: %d\n",
248 err);
Cihangir Akturk7664b2f2017-08-11 15:33:07 +0300249 drm_gem_object_put_unlocked(&bo->gem);
Daniel Vetterda7bdda2017-02-07 17:16:03 +0100250 return PTR_ERR(fbdev->fb);
Arto Merilainende2ba662013-03-22 16:34:08 +0200251 }
252
Daniel Stonedbc33c72018-03-30 15:11:27 +0100253 fb = fbdev->fb;
Arto Merilainende2ba662013-03-22 16:34:08 +0200254 helper->fb = fb;
255 helper->fbdev = info;
256
257 info->par = helper;
258 info->flags = FBINFO_FLAG_DEFAULT;
259 info->fbops = &tegra_fb_ops;
260
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200261 drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
Arto Merilainende2ba662013-03-22 16:34:08 +0200262 drm_fb_helper_fill_var(info, helper, fb->width, fb->height);
263
264 offset = info->var.xoffset * bytes_per_pixel +
265 info->var.yoffset * fb->pitches[0];
266
Thierry Redingdf06b752014-06-26 21:41:53 +0200267 if (bo->pages) {
268 bo->vaddr = vmap(bo->pages, bo->num_pages, VM_MAP,
269 pgprot_writecombine(PAGE_KERNEL));
270 if (!bo->vaddr) {
271 dev_err(drm->dev, "failed to vmap() framebuffer\n");
272 err = -ENOMEM;
273 goto destroy;
274 }
275 }
276
Arto Merilainende2ba662013-03-22 16:34:08 +0200277 drm->mode_config.fb_base = (resource_size_t)bo->paddr;
Thierry Reding9ab34152013-11-08 13:18:14 +0100278 info->screen_base = (void __iomem *)bo->vaddr + offset;
Arto Merilainende2ba662013-03-22 16:34:08 +0200279 info->screen_size = size;
280 info->fix.smem_start = (unsigned long)(bo->paddr + offset);
281 info->fix.smem_len = size;
282
283 return 0;
284
285destroy:
Daniel Vetter3e7d2fdd2016-12-27 11:49:25 +0100286 drm_framebuffer_remove(fb);
Arto Merilainende2ba662013-03-22 16:34:08 +0200287 return err;
288}
289
Thierry Reding3a493872014-06-27 17:19:23 +0200290static const struct drm_fb_helper_funcs tegra_fb_helper_funcs = {
Arto Merilainende2ba662013-03-22 16:34:08 +0200291 .fb_probe = tegra_fbdev_probe,
292};
293
Thierry Redinge2215321f2014-06-27 17:19:25 +0200294static struct tegra_fbdev *tegra_fbdev_create(struct drm_device *drm)
Arto Merilainende2ba662013-03-22 16:34:08 +0200295{
Arto Merilainende2ba662013-03-22 16:34:08 +0200296 struct tegra_fbdev *fbdev;
Arto Merilainende2ba662013-03-22 16:34:08 +0200297
298 fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
299 if (!fbdev) {
300 dev_err(drm->dev, "failed to allocate DRM fbdev\n");
301 return ERR_PTR(-ENOMEM);
302 }
303
Thierry Reding10a23102014-06-27 17:19:24 +0200304 drm_fb_helper_prepare(drm, &fbdev->base, &tegra_fb_helper_funcs);
Arto Merilainende2ba662013-03-22 16:34:08 +0200305
Thierry Redinge2215321f2014-06-27 17:19:25 +0200306 return fbdev;
307}
308
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100309static void tegra_fbdev_free(struct tegra_fbdev *fbdev)
310{
311 kfree(fbdev);
312}
313
Thierry Redinge2215321f2014-06-27 17:19:25 +0200314static int tegra_fbdev_init(struct tegra_fbdev *fbdev,
315 unsigned int preferred_bpp,
316 unsigned int num_crtc,
317 unsigned int max_connectors)
318{
319 struct drm_device *drm = fbdev->base.dev;
320 int err;
321
Gabriel Krisman Bertazie4563f62017-02-02 14:26:40 -0200322 err = drm_fb_helper_init(drm, &fbdev->base, max_connectors);
Arto Merilainende2ba662013-03-22 16:34:08 +0200323 if (err < 0) {
Thierry Redingcb10c812014-11-06 14:36:19 +0100324 dev_err(drm->dev, "failed to initialize DRM FB helper: %d\n",
325 err);
Thierry Redinge2215321f2014-06-27 17:19:25 +0200326 return err;
Arto Merilainende2ba662013-03-22 16:34:08 +0200327 }
328
329 err = drm_fb_helper_single_add_all_connectors(&fbdev->base);
330 if (err < 0) {
Thierry Redingcb10c812014-11-06 14:36:19 +0100331 dev_err(drm->dev, "failed to add connectors: %d\n", err);
Arto Merilainende2ba662013-03-22 16:34:08 +0200332 goto fini;
333 }
334
Arto Merilainende2ba662013-03-22 16:34:08 +0200335 err = drm_fb_helper_initial_config(&fbdev->base, preferred_bpp);
336 if (err < 0) {
Thierry Redingcb10c812014-11-06 14:36:19 +0100337 dev_err(drm->dev, "failed to set initial configuration: %d\n",
338 err);
Arto Merilainende2ba662013-03-22 16:34:08 +0200339 goto fini;
340 }
341
Thierry Redinge2215321f2014-06-27 17:19:25 +0200342 return 0;
Arto Merilainende2ba662013-03-22 16:34:08 +0200343
344fini:
345 drm_fb_helper_fini(&fbdev->base);
Thierry Redinge2215321f2014-06-27 17:19:25 +0200346 return err;
Arto Merilainende2ba662013-03-22 16:34:08 +0200347}
348
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100349static void tegra_fbdev_exit(struct tegra_fbdev *fbdev)
Arto Merilainende2ba662013-03-22 16:34:08 +0200350{
Archit Taneja0f7d9052015-07-22 14:58:07 +0530351 drm_fb_helper_unregister_fbi(&fbdev->base);
Arto Merilainende2ba662013-03-22 16:34:08 +0200352
Daniel Stonec34a9972018-03-30 15:11:28 +0100353 if (fbdev->fb) {
354 struct tegra_bo *bo = tegra_fb_get_plane(fbdev->fb, 0);
355
356 /* Undo the special mapping we made in fbdev probe. */
357 if (bo && bo->pages) {
358 vunmap(bo->vaddr);
Souptick Joarder53f1e062018-08-01 01:37:05 +0530359 bo->vaddr = NULL;
Daniel Stonec34a9972018-03-30 15:11:28 +0100360 }
361
Daniel Stonedbc33c72018-03-30 15:11:27 +0100362 drm_framebuffer_remove(fbdev->fb);
Daniel Stonec34a9972018-03-30 15:11:28 +0100363 }
Arto Merilainende2ba662013-03-22 16:34:08 +0200364
365 drm_fb_helper_fini(&fbdev->base);
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100366 tegra_fbdev_free(fbdev);
Arto Merilainende2ba662013-03-22 16:34:08 +0200367}
Thierry Reding60c2f702013-10-31 13:28:50 +0100368#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000369
Thierry Redinge2215321f2014-06-27 17:19:25 +0200370int tegra_drm_fb_prepare(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000371{
Archit Tanejab110ef32015-10-27 13:40:59 +0530372#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200373 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000374
Thierry Redinge2215321f2014-06-27 17:19:25 +0200375 tegra->fbdev = tegra_fbdev_create(drm);
Thierry Reding60c2f702013-10-31 13:28:50 +0100376 if (IS_ERR(tegra->fbdev))
377 return PTR_ERR(tegra->fbdev);
378#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000379
380 return 0;
381}
382
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100383void tegra_drm_fb_free(struct drm_device *drm)
384{
Archit Tanejab110ef32015-10-27 13:40:59 +0530385#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100386 struct tegra_drm *tegra = drm->dev_private;
387
388 tegra_fbdev_free(tegra->fbdev);
389#endif
390}
391
Thierry Redinge2215321f2014-06-27 17:19:25 +0200392int tegra_drm_fb_init(struct drm_device *drm)
393{
Archit Tanejab110ef32015-10-27 13:40:59 +0530394#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redinge2215321f2014-06-27 17:19:25 +0200395 struct tegra_drm *tegra = drm->dev_private;
396 int err;
397
398 err = tegra_fbdev_init(tegra->fbdev, 32, drm->mode_config.num_crtc,
399 drm->mode_config.num_connector);
400 if (err < 0)
401 return err;
402#endif
403
404 return 0;
405}
406
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000407void tegra_drm_fb_exit(struct drm_device *drm)
408{
Archit Tanejab110ef32015-10-27 13:40:59 +0530409#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200410 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000411
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100412 tegra_fbdev_exit(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100413#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000414}