Thomas Gleixner | c942fdd | 2019-05-27 08:55:06 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 2 | /* |
Roland Stigge | da03d74 | 2012-06-11 10:12:40 +0200 | [diff] [blame] | 3 | * GPIO driver for LPC32xx SoC |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 4 | * |
| 5 | * Author: Kevin Wells <kevin.wells@nxp.com> |
| 6 | * |
| 7 | * Copyright (C) 2010 NXP Semiconductors |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <linux/kernel.h> |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/io.h> |
| 13 | #include <linux/errno.h> |
Linus Walleij | 11975f9 | 2018-04-13 14:47:59 +0200 | [diff] [blame] | 14 | #include <linux/gpio/driver.h> |
Sachin Kamat | 831cbd7 | 2013-10-16 15:35:01 +0530 | [diff] [blame] | 15 | #include <linux/of.h> |
Roland Stigge | e92935e | 2012-05-18 10:19:52 +0200 | [diff] [blame] | 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/module.h> |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 18 | |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 19 | #define LPC32XX_GPIO_P3_INP_STATE (0x000) |
| 20 | #define LPC32XX_GPIO_P3_OUTP_SET (0x004) |
| 21 | #define LPC32XX_GPIO_P3_OUTP_CLR (0x008) |
| 22 | #define LPC32XX_GPIO_P3_OUTP_STATE (0x00C) |
| 23 | #define LPC32XX_GPIO_P2_DIR_SET (0x010) |
| 24 | #define LPC32XX_GPIO_P2_DIR_CLR (0x014) |
| 25 | #define LPC32XX_GPIO_P2_DIR_STATE (0x018) |
| 26 | #define LPC32XX_GPIO_P2_INP_STATE (0x01C) |
| 27 | #define LPC32XX_GPIO_P2_OUTP_SET (0x020) |
| 28 | #define LPC32XX_GPIO_P2_OUTP_CLR (0x024) |
| 29 | #define LPC32XX_GPIO_P2_MUX_SET (0x028) |
| 30 | #define LPC32XX_GPIO_P2_MUX_CLR (0x02C) |
| 31 | #define LPC32XX_GPIO_P2_MUX_STATE (0x030) |
| 32 | #define LPC32XX_GPIO_P0_INP_STATE (0x040) |
| 33 | #define LPC32XX_GPIO_P0_OUTP_SET (0x044) |
| 34 | #define LPC32XX_GPIO_P0_OUTP_CLR (0x048) |
| 35 | #define LPC32XX_GPIO_P0_OUTP_STATE (0x04C) |
| 36 | #define LPC32XX_GPIO_P0_DIR_SET (0x050) |
| 37 | #define LPC32XX_GPIO_P0_DIR_CLR (0x054) |
| 38 | #define LPC32XX_GPIO_P0_DIR_STATE (0x058) |
| 39 | #define LPC32XX_GPIO_P1_INP_STATE (0x060) |
| 40 | #define LPC32XX_GPIO_P1_OUTP_SET (0x064) |
| 41 | #define LPC32XX_GPIO_P1_OUTP_CLR (0x068) |
| 42 | #define LPC32XX_GPIO_P1_OUTP_STATE (0x06C) |
| 43 | #define LPC32XX_GPIO_P1_DIR_SET (0x070) |
| 44 | #define LPC32XX_GPIO_P1_DIR_CLR (0x074) |
| 45 | #define LPC32XX_GPIO_P1_DIR_STATE (0x078) |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 46 | |
| 47 | #define GPIO012_PIN_TO_BIT(x) (1 << (x)) |
| 48 | #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) |
| 49 | #define GPO3_PIN_TO_BIT(x) (1 << (x)) |
| 50 | #define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) |
| 51 | #define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x)) |
Roland Stigge | 8e5fb37 | 2012-03-05 23:01:10 +0100 | [diff] [blame] | 52 | #define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1) |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 53 | #define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1) |
| 54 | #define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) |
Roland Stigge | 46158aa | 2012-03-05 23:01:11 +0100 | [diff] [blame] | 55 | #define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 56 | |
Vladimir Zapolskiy | 14bf873 | 2016-09-08 02:58:32 +0300 | [diff] [blame] | 57 | #define LPC32XX_GPIO_P0_MAX 8 |
| 58 | #define LPC32XX_GPIO_P1_MAX 24 |
| 59 | #define LPC32XX_GPIO_P2_MAX 13 |
| 60 | #define LPC32XX_GPIO_P3_MAX 6 |
| 61 | #define LPC32XX_GPI_P3_MAX 29 |
| 62 | #define LPC32XX_GPO_P3_MAX 24 |
| 63 | |
| 64 | #define LPC32XX_GPIO_P0_GRP 0 |
| 65 | #define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX) |
| 66 | #define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX) |
| 67 | #define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX) |
| 68 | #define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX) |
| 69 | #define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX) |
| 70 | |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 71 | struct gpio_regs { |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 72 | unsigned long inp_state; |
| 73 | unsigned long outp_state; |
| 74 | unsigned long outp_set; |
| 75 | unsigned long outp_clr; |
| 76 | unsigned long dir_set; |
| 77 | unsigned long dir_clr; |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 78 | }; |
| 79 | |
| 80 | /* |
| 81 | * GPIO names |
| 82 | */ |
| 83 | static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = { |
| 84 | "p0.0", "p0.1", "p0.2", "p0.3", |
| 85 | "p0.4", "p0.5", "p0.6", "p0.7" |
| 86 | }; |
| 87 | |
| 88 | static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = { |
| 89 | "p1.0", "p1.1", "p1.2", "p1.3", |
| 90 | "p1.4", "p1.5", "p1.6", "p1.7", |
| 91 | "p1.8", "p1.9", "p1.10", "p1.11", |
| 92 | "p1.12", "p1.13", "p1.14", "p1.15", |
| 93 | "p1.16", "p1.17", "p1.18", "p1.19", |
| 94 | "p1.20", "p1.21", "p1.22", "p1.23", |
| 95 | }; |
| 96 | |
| 97 | static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = { |
| 98 | "p2.0", "p2.1", "p2.2", "p2.3", |
| 99 | "p2.4", "p2.5", "p2.6", "p2.7", |
| 100 | "p2.8", "p2.9", "p2.10", "p2.11", |
| 101 | "p2.12" |
| 102 | }; |
| 103 | |
| 104 | static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = { |
Roland Stigge | 95120d5 | 2012-01-22 18:57:57 +0100 | [diff] [blame] | 105 | "gpio00", "gpio01", "gpio02", "gpio03", |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 106 | "gpio04", "gpio05" |
| 107 | }; |
| 108 | |
| 109 | static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = { |
| 110 | "gpi00", "gpi01", "gpi02", "gpi03", |
| 111 | "gpi04", "gpi05", "gpi06", "gpi07", |
| 112 | "gpi08", "gpi09", NULL, NULL, |
| 113 | NULL, NULL, NULL, "gpi15", |
| 114 | "gpi16", "gpi17", "gpi18", "gpi19", |
| 115 | "gpi20", "gpi21", "gpi22", "gpi23", |
Roland Stigge | 71fde00 | 2012-09-25 09:56:13 +0200 | [diff] [blame] | 116 | "gpi24", "gpi25", "gpi26", "gpi27", |
| 117 | "gpi28" |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 118 | }; |
| 119 | |
| 120 | static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = { |
| 121 | "gpo00", "gpo01", "gpo02", "gpo03", |
| 122 | "gpo04", "gpo05", "gpo06", "gpo07", |
| 123 | "gpo08", "gpo09", "gpo10", "gpo11", |
| 124 | "gpo12", "gpo13", "gpo14", "gpo15", |
| 125 | "gpo16", "gpo17", "gpo18", "gpo19", |
| 126 | "gpo20", "gpo21", "gpo22", "gpo23" |
| 127 | }; |
| 128 | |
| 129 | static struct gpio_regs gpio_grp_regs_p0 = { |
| 130 | .inp_state = LPC32XX_GPIO_P0_INP_STATE, |
| 131 | .outp_set = LPC32XX_GPIO_P0_OUTP_SET, |
| 132 | .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR, |
| 133 | .dir_set = LPC32XX_GPIO_P0_DIR_SET, |
| 134 | .dir_clr = LPC32XX_GPIO_P0_DIR_CLR, |
| 135 | }; |
| 136 | |
| 137 | static struct gpio_regs gpio_grp_regs_p1 = { |
| 138 | .inp_state = LPC32XX_GPIO_P1_INP_STATE, |
| 139 | .outp_set = LPC32XX_GPIO_P1_OUTP_SET, |
| 140 | .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR, |
| 141 | .dir_set = LPC32XX_GPIO_P1_DIR_SET, |
| 142 | .dir_clr = LPC32XX_GPIO_P1_DIR_CLR, |
| 143 | }; |
| 144 | |
| 145 | static struct gpio_regs gpio_grp_regs_p2 = { |
| 146 | .inp_state = LPC32XX_GPIO_P2_INP_STATE, |
| 147 | .outp_set = LPC32XX_GPIO_P2_OUTP_SET, |
| 148 | .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR, |
| 149 | .dir_set = LPC32XX_GPIO_P2_DIR_SET, |
| 150 | .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, |
| 151 | }; |
| 152 | |
| 153 | static struct gpio_regs gpio_grp_regs_p3 = { |
| 154 | .inp_state = LPC32XX_GPIO_P3_INP_STATE, |
Roland Stigge | 46158aa | 2012-03-05 23:01:11 +0100 | [diff] [blame] | 155 | .outp_state = LPC32XX_GPIO_P3_OUTP_STATE, |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 156 | .outp_set = LPC32XX_GPIO_P3_OUTP_SET, |
| 157 | .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR, |
| 158 | .dir_set = LPC32XX_GPIO_P2_DIR_SET, |
| 159 | .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, |
| 160 | }; |
| 161 | |
| 162 | struct lpc32xx_gpio_chip { |
| 163 | struct gpio_chip chip; |
| 164 | struct gpio_regs *gpio_grp; |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 165 | void __iomem *reg_base; |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 166 | }; |
| 167 | |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 168 | static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset) |
| 169 | { |
| 170 | return __raw_readl(group->reg_base + offset); |
| 171 | } |
| 172 | |
| 173 | static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset) |
| 174 | { |
| 175 | __raw_writel(val, group->reg_base + offset); |
| 176 | } |
| 177 | |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 178 | static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, |
| 179 | unsigned pin, int input) |
| 180 | { |
| 181 | if (input) |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 182 | gpreg_write(group, GPIO012_PIN_TO_BIT(pin), |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 183 | group->gpio_grp->dir_clr); |
| 184 | else |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 185 | gpreg_write(group, GPIO012_PIN_TO_BIT(pin), |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 186 | group->gpio_grp->dir_set); |
| 187 | } |
| 188 | |
| 189 | static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, |
| 190 | unsigned pin, int input) |
| 191 | { |
| 192 | u32 u = GPIO3_PIN_TO_BIT(pin); |
| 193 | |
| 194 | if (input) |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 195 | gpreg_write(group, u, group->gpio_grp->dir_clr); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 196 | else |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 197 | gpreg_write(group, u, group->gpio_grp->dir_set); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, |
| 201 | unsigned pin, int high) |
| 202 | { |
| 203 | if (high) |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 204 | gpreg_write(group, GPIO012_PIN_TO_BIT(pin), |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 205 | group->gpio_grp->outp_set); |
| 206 | else |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 207 | gpreg_write(group, GPIO012_PIN_TO_BIT(pin), |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 208 | group->gpio_grp->outp_clr); |
| 209 | } |
| 210 | |
| 211 | static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, |
| 212 | unsigned pin, int high) |
| 213 | { |
| 214 | u32 u = GPIO3_PIN_TO_BIT(pin); |
| 215 | |
| 216 | if (high) |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 217 | gpreg_write(group, u, group->gpio_grp->outp_set); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 218 | else |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 219 | gpreg_write(group, u, group->gpio_grp->outp_clr); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 220 | } |
| 221 | |
| 222 | static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, |
| 223 | unsigned pin, int high) |
| 224 | { |
| 225 | if (high) |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 226 | gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 227 | else |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 228 | gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 229 | } |
| 230 | |
| 231 | static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, |
| 232 | unsigned pin) |
| 233 | { |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 234 | return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 235 | pin); |
| 236 | } |
| 237 | |
| 238 | static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, |
| 239 | unsigned pin) |
| 240 | { |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 241 | int state = gpreg_read(group, group->gpio_grp->inp_state); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 242 | |
| 243 | /* |
| 244 | * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped |
| 245 | * to bits 10..14, while GPIOP3-5 is mapped to bit 24. |
| 246 | */ |
| 247 | return GPIO3_PIN_IN_SEL(state, pin); |
| 248 | } |
| 249 | |
| 250 | static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, |
| 251 | unsigned pin) |
| 252 | { |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 253 | return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 254 | } |
| 255 | |
Roland Stigge | 46158aa | 2012-03-05 23:01:11 +0100 | [diff] [blame] | 256 | static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, |
| 257 | unsigned pin) |
| 258 | { |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 259 | return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin); |
Roland Stigge | 46158aa | 2012-03-05 23:01:11 +0100 | [diff] [blame] | 260 | } |
| 261 | |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 262 | /* |
Alexandre Courbot | 7fd2bf3 | 2013-03-28 05:07:46 -0700 | [diff] [blame] | 263 | * GPIO primitives. |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 264 | */ |
| 265 | static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip, |
| 266 | unsigned pin) |
| 267 | { |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 268 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 269 | |
| 270 | __set_gpio_dir_p012(group, pin, 1); |
| 271 | |
| 272 | return 0; |
| 273 | } |
| 274 | |
| 275 | static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip, |
| 276 | unsigned pin) |
| 277 | { |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 278 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 279 | |
| 280 | __set_gpio_dir_p3(group, pin, 1); |
| 281 | |
| 282 | return 0; |
| 283 | } |
| 284 | |
| 285 | static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip, |
| 286 | unsigned pin) |
| 287 | { |
| 288 | return 0; |
| 289 | } |
| 290 | |
| 291 | static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin) |
| 292 | { |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 293 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 294 | |
Linus Walleij | 2e6d845 | 2015-12-21 11:10:06 +0100 | [diff] [blame] | 295 | return !!__get_gpio_state_p012(group, pin); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 296 | } |
| 297 | |
| 298 | static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin) |
| 299 | { |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 300 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 301 | |
Linus Walleij | 2e6d845 | 2015-12-21 11:10:06 +0100 | [diff] [blame] | 302 | return !!__get_gpio_state_p3(group, pin); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 303 | } |
| 304 | |
| 305 | static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin) |
| 306 | { |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 307 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 308 | |
Linus Walleij | 2e6d845 | 2015-12-21 11:10:06 +0100 | [diff] [blame] | 309 | return !!__get_gpi_state_p3(group, pin); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 310 | } |
| 311 | |
| 312 | static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin, |
| 313 | int value) |
| 314 | { |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 315 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 316 | |
Roland Stigge | b1268d3 | 2012-09-20 10:48:03 +0200 | [diff] [blame] | 317 | __set_gpio_level_p012(group, pin, value); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 318 | __set_gpio_dir_p012(group, pin, 0); |
| 319 | |
| 320 | return 0; |
| 321 | } |
| 322 | |
| 323 | static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin, |
| 324 | int value) |
| 325 | { |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 326 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 327 | |
Roland Stigge | b1268d3 | 2012-09-20 10:48:03 +0200 | [diff] [blame] | 328 | __set_gpio_level_p3(group, pin, value); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 329 | __set_gpio_dir_p3(group, pin, 0); |
| 330 | |
| 331 | return 0; |
| 332 | } |
| 333 | |
| 334 | static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin, |
| 335 | int value) |
| 336 | { |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 337 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
Roland Stigge | b1268d3 | 2012-09-20 10:48:03 +0200 | [diff] [blame] | 338 | |
| 339 | __set_gpo_level_p3(group, pin, value); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 340 | return 0; |
| 341 | } |
| 342 | |
| 343 | static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin, |
| 344 | int value) |
| 345 | { |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 346 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 347 | |
| 348 | __set_gpio_level_p012(group, pin, value); |
| 349 | } |
| 350 | |
| 351 | static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin, |
| 352 | int value) |
| 353 | { |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 354 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 355 | |
| 356 | __set_gpio_level_p3(group, pin, value); |
| 357 | } |
| 358 | |
| 359 | static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin, |
| 360 | int value) |
| 361 | { |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 362 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 363 | |
| 364 | __set_gpo_level_p3(group, pin, value); |
| 365 | } |
| 366 | |
Roland Stigge | 46158aa | 2012-03-05 23:01:11 +0100 | [diff] [blame] | 367 | static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin) |
| 368 | { |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 369 | struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); |
Roland Stigge | 46158aa | 2012-03-05 23:01:11 +0100 | [diff] [blame] | 370 | |
Linus Walleij | 2e6d845 | 2015-12-21 11:10:06 +0100 | [diff] [blame] | 371 | return !!__get_gpo_state_p3(group, pin); |
Roland Stigge | 46158aa | 2012-03-05 23:01:11 +0100 | [diff] [blame] | 372 | } |
| 373 | |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 374 | static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin) |
| 375 | { |
| 376 | if (pin < chip->ngpio) |
| 377 | return 0; |
| 378 | |
| 379 | return -EINVAL; |
| 380 | } |
| 381 | |
Roland Stigge | 0bdfedd | 2012-06-20 16:33:52 +0200 | [diff] [blame] | 382 | static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset) |
| 383 | { |
Roland Stigge | 0bdfedd | 2012-06-20 16:33:52 +0200 | [diff] [blame] | 384 | return -ENXIO; |
| 385 | } |
| 386 | |
Sylvain Lemieux | 320a648 | 2016-05-11 13:40:00 -0400 | [diff] [blame] | 387 | static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset) |
| 388 | { |
| 389 | return -ENXIO; |
| 390 | } |
Roland Stigge | 0bdfedd | 2012-06-20 16:33:52 +0200 | [diff] [blame] | 391 | |
| 392 | static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset) |
| 393 | { |
Roland Stigge | 0bdfedd | 2012-06-20 16:33:52 +0200 | [diff] [blame] | 394 | return -ENXIO; |
| 395 | } |
| 396 | |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 397 | static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = { |
| 398 | { |
| 399 | .chip = { |
| 400 | .label = "gpio_p0", |
| 401 | .direction_input = lpc32xx_gpio_dir_input_p012, |
| 402 | .get = lpc32xx_gpio_get_value_p012, |
| 403 | .direction_output = lpc32xx_gpio_dir_output_p012, |
| 404 | .set = lpc32xx_gpio_set_value_p012, |
| 405 | .request = lpc32xx_gpio_request, |
Roland Stigge | 0bdfedd | 2012-06-20 16:33:52 +0200 | [diff] [blame] | 406 | .to_irq = lpc32xx_gpio_to_irq_p01, |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 407 | .base = LPC32XX_GPIO_P0_GRP, |
| 408 | .ngpio = LPC32XX_GPIO_P0_MAX, |
| 409 | .names = gpio_p0_names, |
Linus Walleij | 9fb1f39 | 2013-12-04 14:42:46 +0100 | [diff] [blame] | 410 | .can_sleep = false, |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 411 | }, |
| 412 | .gpio_grp = &gpio_grp_regs_p0, |
| 413 | }, |
| 414 | { |
| 415 | .chip = { |
| 416 | .label = "gpio_p1", |
| 417 | .direction_input = lpc32xx_gpio_dir_input_p012, |
| 418 | .get = lpc32xx_gpio_get_value_p012, |
| 419 | .direction_output = lpc32xx_gpio_dir_output_p012, |
| 420 | .set = lpc32xx_gpio_set_value_p012, |
| 421 | .request = lpc32xx_gpio_request, |
Roland Stigge | 0bdfedd | 2012-06-20 16:33:52 +0200 | [diff] [blame] | 422 | .to_irq = lpc32xx_gpio_to_irq_p01, |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 423 | .base = LPC32XX_GPIO_P1_GRP, |
| 424 | .ngpio = LPC32XX_GPIO_P1_MAX, |
| 425 | .names = gpio_p1_names, |
Linus Walleij | 9fb1f39 | 2013-12-04 14:42:46 +0100 | [diff] [blame] | 426 | .can_sleep = false, |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 427 | }, |
| 428 | .gpio_grp = &gpio_grp_regs_p1, |
| 429 | }, |
| 430 | { |
| 431 | .chip = { |
| 432 | .label = "gpio_p2", |
| 433 | .direction_input = lpc32xx_gpio_dir_input_p012, |
| 434 | .get = lpc32xx_gpio_get_value_p012, |
| 435 | .direction_output = lpc32xx_gpio_dir_output_p012, |
| 436 | .set = lpc32xx_gpio_set_value_p012, |
| 437 | .request = lpc32xx_gpio_request, |
| 438 | .base = LPC32XX_GPIO_P2_GRP, |
| 439 | .ngpio = LPC32XX_GPIO_P2_MAX, |
| 440 | .names = gpio_p2_names, |
Linus Walleij | 9fb1f39 | 2013-12-04 14:42:46 +0100 | [diff] [blame] | 441 | .can_sleep = false, |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 442 | }, |
| 443 | .gpio_grp = &gpio_grp_regs_p2, |
| 444 | }, |
| 445 | { |
| 446 | .chip = { |
| 447 | .label = "gpio_p3", |
| 448 | .direction_input = lpc32xx_gpio_dir_input_p3, |
| 449 | .get = lpc32xx_gpio_get_value_p3, |
| 450 | .direction_output = lpc32xx_gpio_dir_output_p3, |
| 451 | .set = lpc32xx_gpio_set_value_p3, |
| 452 | .request = lpc32xx_gpio_request, |
Roland Stigge | 0bdfedd | 2012-06-20 16:33:52 +0200 | [diff] [blame] | 453 | .to_irq = lpc32xx_gpio_to_irq_gpio_p3, |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 454 | .base = LPC32XX_GPIO_P3_GRP, |
| 455 | .ngpio = LPC32XX_GPIO_P3_MAX, |
| 456 | .names = gpio_p3_names, |
Linus Walleij | 9fb1f39 | 2013-12-04 14:42:46 +0100 | [diff] [blame] | 457 | .can_sleep = false, |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 458 | }, |
| 459 | .gpio_grp = &gpio_grp_regs_p3, |
| 460 | }, |
| 461 | { |
| 462 | .chip = { |
| 463 | .label = "gpi_p3", |
| 464 | .direction_input = lpc32xx_gpio_dir_in_always, |
| 465 | .get = lpc32xx_gpi_get_value, |
| 466 | .request = lpc32xx_gpio_request, |
Roland Stigge | 0bdfedd | 2012-06-20 16:33:52 +0200 | [diff] [blame] | 467 | .to_irq = lpc32xx_gpio_to_irq_gpi_p3, |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 468 | .base = LPC32XX_GPI_P3_GRP, |
| 469 | .ngpio = LPC32XX_GPI_P3_MAX, |
| 470 | .names = gpi_p3_names, |
Linus Walleij | 9fb1f39 | 2013-12-04 14:42:46 +0100 | [diff] [blame] | 471 | .can_sleep = false, |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 472 | }, |
| 473 | .gpio_grp = &gpio_grp_regs_p3, |
| 474 | }, |
| 475 | { |
| 476 | .chip = { |
| 477 | .label = "gpo_p3", |
| 478 | .direction_output = lpc32xx_gpio_dir_out_always, |
| 479 | .set = lpc32xx_gpo_set_value, |
Roland Stigge | 46158aa | 2012-03-05 23:01:11 +0100 | [diff] [blame] | 480 | .get = lpc32xx_gpo_get_value, |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 481 | .request = lpc32xx_gpio_request, |
| 482 | .base = LPC32XX_GPO_P3_GRP, |
| 483 | .ngpio = LPC32XX_GPO_P3_MAX, |
| 484 | .names = gpo_p3_names, |
Linus Walleij | 9fb1f39 | 2013-12-04 14:42:46 +0100 | [diff] [blame] | 485 | .can_sleep = false, |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 486 | }, |
| 487 | .gpio_grp = &gpio_grp_regs_p3, |
| 488 | }, |
| 489 | }; |
| 490 | |
Roland Stigge | e92935e | 2012-05-18 10:19:52 +0200 | [diff] [blame] | 491 | static int lpc32xx_of_xlate(struct gpio_chip *gc, |
| 492 | const struct of_phandle_args *gpiospec, u32 *flags) |
| 493 | { |
| 494 | /* Is this the correct bank? */ |
| 495 | u32 bank = gpiospec->args[0]; |
Axel Lin | fdc7a9f | 2013-04-07 20:28:20 +0800 | [diff] [blame] | 496 | if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) || |
Roland Stigge | e92935e | 2012-05-18 10:19:52 +0200 | [diff] [blame] | 497 | (gc != &lpc32xx_gpiochip[bank].chip))) |
| 498 | return -EINVAL; |
| 499 | |
| 500 | if (flags) |
| 501 | *flags = gpiospec->args[2]; |
| 502 | return gpiospec->args[1]; |
| 503 | } |
| 504 | |
Bill Pemberton | 3836309 | 2012-11-19 13:22:34 -0500 | [diff] [blame] | 505 | static int lpc32xx_gpio_probe(struct platform_device *pdev) |
Roland Stigge | e92935e | 2012-05-18 10:19:52 +0200 | [diff] [blame] | 506 | { |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 507 | int i; |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 508 | void __iomem *reg_base; |
| 509 | |
| 510 | reg_base = devm_platform_ioremap_resource(pdev, 0); |
| 511 | if (IS_ERR(reg_base)) |
| 512 | return PTR_ERR(reg_base); |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 513 | |
Roland Stigge | e92935e | 2012-05-18 10:19:52 +0200 | [diff] [blame] | 514 | for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) { |
Andy Shevchenko | 45a541a | 2021-12-06 15:18:51 +0200 | [diff] [blame] | 515 | lpc32xx_gpiochip[i].chip.parent = &pdev->dev; |
Roland Stigge | e92935e | 2012-05-18 10:19:52 +0200 | [diff] [blame] | 516 | if (pdev->dev.of_node) { |
| 517 | lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate; |
| 518 | lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3; |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 519 | lpc32xx_gpiochip[i].reg_base = reg_base; |
Roland Stigge | e92935e | 2012-05-18 10:19:52 +0200 | [diff] [blame] | 520 | } |
Laxman Dewangan | 69c0a0a | 2016-02-22 17:43:28 +0530 | [diff] [blame] | 521 | devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip, |
Linus Walleij | a9bc97e | 2015-12-07 09:18:23 +0100 | [diff] [blame] | 522 | &lpc32xx_gpiochip[i]); |
Roland Stigge | e92935e | 2012-05-18 10:19:52 +0200 | [diff] [blame] | 523 | } |
| 524 | |
| 525 | return 0; |
Kevin Wells | c4a0208 | 2010-02-26 15:53:41 -0800 | [diff] [blame] | 526 | } |
Roland Stigge | e92935e | 2012-05-18 10:19:52 +0200 | [diff] [blame] | 527 | |
Jingoo Han | e95c7c4 | 2014-06-03 21:09:02 +0900 | [diff] [blame] | 528 | static const struct of_device_id lpc32xx_gpio_of_match[] = { |
Roland Stigge | e92935e | 2012-05-18 10:19:52 +0200 | [diff] [blame] | 529 | { .compatible = "nxp,lpc3220-gpio", }, |
| 530 | { }, |
| 531 | }; |
Roland Stigge | e92935e | 2012-05-18 10:19:52 +0200 | [diff] [blame] | 532 | |
| 533 | static struct platform_driver lpc32xx_gpio_driver = { |
| 534 | .driver = { |
| 535 | .name = "lpc32xx-gpio", |
Zhu Wang | bcb6b9e | 2023-08-02 11:17:49 +0800 | [diff] [blame] | 536 | .of_match_table = lpc32xx_gpio_of_match, |
Roland Stigge | e92935e | 2012-05-18 10:19:52 +0200 | [diff] [blame] | 537 | }, |
| 538 | .probe = lpc32xx_gpio_probe, |
| 539 | }; |
| 540 | |
| 541 | module_platform_driver(lpc32xx_gpio_driver); |
Arnd Bergmann | f2ee731 | 2019-08-09 16:40:31 +0200 | [diff] [blame] | 542 | |
| 543 | MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); |
| 544 | MODULE_LICENSE("GPL"); |
| 545 | MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC"); |