Thor Thayer | 3dab6bd | 2018-04-27 13:37:17 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Thor Thayer | 143f4a5 | 2015-06-04 09:28:46 -0500 | [diff] [blame] | 2 | /* |
Thor Thayer | 3dab6bd | 2018-04-27 13:37:17 -0500 | [diff] [blame] | 3 | * Copyright (C) 2017-2018, Intel Corporation |
Thor Thayer | 143f4a5 | 2015-06-04 09:28:46 -0500 | [diff] [blame] | 4 | * Copyright (C) 2015 Altera Corporation |
Thor Thayer | 143f4a5 | 2015-06-04 09:28:46 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _ALTERA_EDAC_H |
| 8 | #define _ALTERA_EDAC_H |
| 9 | |
Thor Thayer | 3dab6bd | 2018-04-27 13:37:17 -0500 | [diff] [blame] | 10 | #include <linux/arm-smccc.h> |
Thor Thayer | 143f4a5 | 2015-06-04 09:28:46 -0500 | [diff] [blame] | 11 | #include <linux/edac.h> |
| 12 | #include <linux/types.h> |
| 13 | |
| 14 | /* SDRAM Controller CtrlCfg Register */ |
| 15 | #define CV_CTLCFG_OFST 0x00 |
| 16 | |
| 17 | /* SDRAM Controller CtrlCfg Register Bit Masks */ |
| 18 | #define CV_CTLCFG_ECC_EN 0x400 |
| 19 | #define CV_CTLCFG_ECC_CORR_EN 0x800 |
| 20 | #define CV_CTLCFG_GEN_SB_ERR 0x2000 |
| 21 | #define CV_CTLCFG_GEN_DB_ERR 0x4000 |
| 22 | |
Dinh Nguyen | 941fd2e | 2015-10-14 18:14:16 -0500 | [diff] [blame] | 23 | #define CV_CTLCFG_ECC_AUTO_EN (CV_CTLCFG_ECC_EN) |
Thor Thayer | 143f4a5 | 2015-06-04 09:28:46 -0500 | [diff] [blame] | 24 | |
| 25 | /* SDRAM Controller Address Width Register */ |
| 26 | #define CV_DRAMADDRW_OFST 0x2C |
| 27 | |
| 28 | /* SDRAM Controller Address Widths Field Register */ |
| 29 | #define DRAMADDRW_COLBIT_MASK 0x001F |
| 30 | #define DRAMADDRW_COLBIT_SHIFT 0 |
| 31 | #define DRAMADDRW_ROWBIT_MASK 0x03E0 |
| 32 | #define DRAMADDRW_ROWBIT_SHIFT 5 |
| 33 | #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00 |
| 34 | #define CV_DRAMADDRW_BANKBIT_SHIFT 10 |
| 35 | #define CV_DRAMADDRW_CSBIT_MASK 0xE000 |
| 36 | #define CV_DRAMADDRW_CSBIT_SHIFT 13 |
| 37 | |
| 38 | /* SDRAM Controller Interface Data Width Register */ |
| 39 | #define CV_DRAMIFWIDTH_OFST 0x30 |
| 40 | |
| 41 | /* SDRAM Controller Interface Data Width Defines */ |
| 42 | #define CV_DRAMIFWIDTH_16B_ECC 24 |
| 43 | #define CV_DRAMIFWIDTH_32B_ECC 40 |
| 44 | |
| 45 | /* SDRAM Controller DRAM Status Register */ |
| 46 | #define CV_DRAMSTS_OFST 0x38 |
| 47 | |
| 48 | /* SDRAM Controller DRAM Status Register Bit Masks */ |
| 49 | #define CV_DRAMSTS_SBEERR 0x04 |
| 50 | #define CV_DRAMSTS_DBEERR 0x08 |
| 51 | #define CV_DRAMSTS_CORR_DROP 0x10 |
| 52 | |
| 53 | /* SDRAM Controller DRAM IRQ Register */ |
| 54 | #define CV_DRAMINTR_OFST 0x3C |
| 55 | |
| 56 | /* SDRAM Controller DRAM IRQ Register Bit Masks */ |
| 57 | #define CV_DRAMINTR_INTREN 0x01 |
| 58 | #define CV_DRAMINTR_SBEMASK 0x02 |
| 59 | #define CV_DRAMINTR_DBEMASK 0x04 |
| 60 | #define CV_DRAMINTR_CORRDROPMASK 0x08 |
| 61 | #define CV_DRAMINTR_INTRCLR 0x10 |
| 62 | |
| 63 | /* SDRAM Controller Single Bit Error Count Register */ |
| 64 | #define CV_SBECOUNT_OFST 0x40 |
| 65 | |
| 66 | /* SDRAM Controller Double Bit Error Count Register */ |
| 67 | #define CV_DBECOUNT_OFST 0x44 |
| 68 | |
| 69 | /* SDRAM Controller ECC Error Address Register */ |
| 70 | #define CV_ERRADDR_OFST 0x48 |
| 71 | |
Thor Thayer | 73bcc94 | 2015-06-04 09:28:47 -0500 | [diff] [blame] | 72 | /*-----------------------------------------*/ |
| 73 | |
| 74 | /* SDRAM Controller EccCtrl Register */ |
| 75 | #define A10_ECCCTRL1_OFST 0x00 |
| 76 | |
| 77 | /* SDRAM Controller EccCtrl Register Bit Masks */ |
| 78 | #define A10_ECCCTRL1_ECC_EN 0x001 |
| 79 | #define A10_ECCCTRL1_CNT_RST 0x010 |
| 80 | #define A10_ECCCTRL1_AWB_CNT_RST 0x100 |
| 81 | #define A10_ECC_CNT_RESET_MASK (A10_ECCCTRL1_CNT_RST | \ |
| 82 | A10_ECCCTRL1_AWB_CNT_RST) |
| 83 | |
| 84 | /* SDRAM Controller Address Width Register */ |
| 85 | #define CV_DRAMADDRW 0xFFC2502C |
| 86 | #define A10_DRAMADDRW 0xFFCFA0A8 |
Thor Thayer | 3dab6bd | 2018-04-27 13:37:17 -0500 | [diff] [blame] | 87 | #define S10_DRAMADDRW 0xF80110E0 |
Thor Thayer | 73bcc94 | 2015-06-04 09:28:47 -0500 | [diff] [blame] | 88 | |
| 89 | /* SDRAM Controller Address Widths Field Register */ |
| 90 | #define DRAMADDRW_COLBIT_MASK 0x001F |
| 91 | #define DRAMADDRW_COLBIT_SHIFT 0 |
| 92 | #define DRAMADDRW_ROWBIT_MASK 0x03E0 |
| 93 | #define DRAMADDRW_ROWBIT_SHIFT 5 |
| 94 | #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00 |
| 95 | #define CV_DRAMADDRW_BANKBIT_SHIFT 10 |
| 96 | #define CV_DRAMADDRW_CSBIT_MASK 0xE000 |
| 97 | #define CV_DRAMADDRW_CSBIT_SHIFT 13 |
| 98 | |
| 99 | #define A10_DRAMADDRW_BANKBIT_MASK 0x3C00 |
| 100 | #define A10_DRAMADDRW_BANKBIT_SHIFT 10 |
| 101 | #define A10_DRAMADDRW_GRPBIT_MASK 0xC000 |
| 102 | #define A10_DRAMADDRW_GRPBIT_SHIFT 14 |
| 103 | #define A10_DRAMADDRW_CSBIT_MASK 0x70000 |
| 104 | #define A10_DRAMADDRW_CSBIT_SHIFT 16 |
| 105 | |
| 106 | /* SDRAM Controller Interface Data Width Register */ |
| 107 | #define CV_DRAMIFWIDTH 0xFFC25030 |
| 108 | #define A10_DRAMIFWIDTH 0xFFCFB008 |
Thor Thayer | 3dab6bd | 2018-04-27 13:37:17 -0500 | [diff] [blame] | 109 | #define S10_DRAMIFWIDTH 0xF8011008 |
Thor Thayer | 73bcc94 | 2015-06-04 09:28:47 -0500 | [diff] [blame] | 110 | |
| 111 | /* SDRAM Controller Interface Data Width Defines */ |
| 112 | #define CV_DRAMIFWIDTH_16B_ECC 24 |
| 113 | #define CV_DRAMIFWIDTH_32B_ECC 40 |
| 114 | |
| 115 | #define A10_DRAMIFWIDTH_16B 0x0 |
| 116 | #define A10_DRAMIFWIDTH_32B 0x1 |
| 117 | #define A10_DRAMIFWIDTH_64B 0x2 |
| 118 | |
| 119 | /* SDRAM Controller DRAM IRQ Register */ |
| 120 | #define A10_ERRINTEN_OFST 0x10 |
| 121 | |
| 122 | /* SDRAM Controller DRAM IRQ Register Bit Masks */ |
| 123 | #define A10_ERRINTEN_SERRINTEN 0x01 |
| 124 | #define A10_ERRINTEN_DERRINTEN 0x02 |
| 125 | #define A10_ECC_IRQ_EN_MASK (A10_ERRINTEN_SERRINTEN | \ |
| 126 | A10_ERRINTEN_DERRINTEN) |
| 127 | |
| 128 | /* SDRAM Interrupt Mode Register */ |
| 129 | #define A10_INTMODE_OFST 0x1C |
| 130 | #define A10_INTMODE_SB_INT 1 |
| 131 | |
| 132 | /* SDRAM Controller Error Status Register */ |
| 133 | #define A10_INTSTAT_OFST 0x20 |
| 134 | |
| 135 | /* SDRAM Controller Error Status Register Bit Masks */ |
| 136 | #define A10_INTSTAT_SBEERR 0x01 |
| 137 | #define A10_INTSTAT_DBEERR 0x02 |
| 138 | |
| 139 | /* SDRAM Controller ECC Error Address Register */ |
| 140 | #define A10_DERRADDR_OFST 0x2C |
| 141 | #define A10_SERRADDR_OFST 0x30 |
| 142 | |
| 143 | /* SDRAM Controller ECC Diagnostic Register */ |
| 144 | #define A10_DIAGINTTEST_OFST 0x24 |
| 145 | |
| 146 | #define A10_DIAGINT_TSERRA_MASK 0x0001 |
| 147 | #define A10_DIAGINT_TDERRA_MASK 0x0100 |
| 148 | |
| 149 | #define A10_SBERR_IRQ 34 |
| 150 | #define A10_DBERR_IRQ 32 |
| 151 | |
| 152 | /* SDRAM Single Bit Error Count Compare Set Register */ |
| 153 | #define A10_SERRCNTREG_OFST 0x3C |
| 154 | |
| 155 | #define A10_SYMAN_INTMASK_CLR 0xFFD06098 |
| 156 | #define A10_INTMASK_CLR_OFST 0x10 |
| 157 | #define A10_DDR0_IRQ_MASK BIT(17) |
| 158 | |
Thor Thayer | 3dab6bd | 2018-04-27 13:37:17 -0500 | [diff] [blame] | 159 | /************* Stratix10 Defines **************/ |
| 160 | |
| 161 | /* SDRAM Controller EccCtrl Register */ |
| 162 | #define S10_ECCCTRL1_OFST 0xF8011100 |
| 163 | |
| 164 | /* SDRAM Controller DRAM IRQ Register */ |
| 165 | #define S10_ERRINTEN_OFST 0xF8011110 |
| 166 | |
| 167 | /* SDRAM Interrupt Mode Register */ |
| 168 | #define S10_INTMODE_OFST 0xF801111C |
| 169 | |
| 170 | /* SDRAM Controller Error Status Register */ |
| 171 | #define S10_INTSTAT_OFST 0xF8011120 |
| 172 | |
| 173 | /* SDRAM Controller ECC Error Address Register */ |
| 174 | #define S10_DERRADDR_OFST 0xF801112C |
| 175 | #define S10_SERRADDR_OFST 0xF8011130 |
| 176 | |
| 177 | /* SDRAM Controller ECC Diagnostic Register */ |
| 178 | #define S10_DIAGINTTEST_OFST 0xF8011124 |
| 179 | |
| 180 | /* SDRAM Single Bit Error Count Compare Set Register */ |
| 181 | #define S10_SERRCNTREG_OFST 0xF801113C |
| 182 | |
Thor Thayer | e9918d7 | 2018-05-11 18:00:10 -0500 | [diff] [blame] | 183 | /* Sticky registers for Uncorrected Errors */ |
| 184 | #define S10_SYSMGR_UE_VAL_OFST 0xFFD12220 |
| 185 | #define S10_SYSMGR_UE_ADDR_OFST 0xFFD12224 |
| 186 | |
Thor Thayer | 143f4a5 | 2015-06-04 09:28:46 -0500 | [diff] [blame] | 187 | struct altr_sdram_prv_data { |
| 188 | int ecc_ctrl_offset; |
| 189 | int ecc_ctl_en_mask; |
| 190 | int ecc_cecnt_offset; |
| 191 | int ecc_uecnt_offset; |
| 192 | int ecc_stat_offset; |
| 193 | int ecc_stat_ce_mask; |
| 194 | int ecc_stat_ue_mask; |
| 195 | int ecc_saddr_offset; |
| 196 | int ecc_daddr_offset; |
| 197 | int ecc_irq_en_offset; |
| 198 | int ecc_irq_en_mask; |
| 199 | int ecc_irq_clr_offset; |
| 200 | int ecc_irq_clr_mask; |
| 201 | int ecc_cnt_rst_offset; |
| 202 | int ecc_cnt_rst_mask; |
Thor Thayer | 143f4a5 | 2015-06-04 09:28:46 -0500 | [diff] [blame] | 203 | struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr; |
| 204 | int ecc_enable_mask; |
| 205 | int ce_set_mask; |
| 206 | int ue_set_mask; |
| 207 | int ce_ue_trgr_offset; |
Thor Thayer | 143f4a5 | 2015-06-04 09:28:46 -0500 | [diff] [blame] | 208 | }; |
| 209 | |
| 210 | /* Altera SDRAM Memory Controller data */ |
| 211 | struct altr_sdram_mc_data { |
| 212 | struct regmap *mc_vbase; |
| 213 | int sb_irq; |
| 214 | int db_irq; |
| 215 | const struct altr_sdram_prv_data *data; |
| 216 | }; |
| 217 | |
Thor Thayer | 05b088b | 2016-03-21 11:01:39 -0500 | [diff] [blame] | 218 | /************************** EDAC Device Defines **************************/ |
| 219 | /***** General Device Trigger Defines *****/ |
| 220 | #define ALTR_UE_TRIGGER_CHAR 'U' /* Trigger for UE */ |
| 221 | #define ALTR_TRIGGER_READ_WRD_CNT 32 /* Line size x 4 */ |
| 222 | #define ALTR_TRIG_OCRAM_BYTE_SIZE 128 /* Line size x 4 */ |
| 223 | #define ALTR_TRIG_L2C_BYTE_SIZE 4096 /* Full Page */ |
| 224 | |
| 225 | /******* Cyclone5 and Arria5 Defines *******/ |
| 226 | /* OCRAM ECC Management Group Defines */ |
| 227 | #define ALTR_MAN_GRP_OCRAM_ECC_OFFSET 0x04 |
Thor Thayer | 811fce4 | 2016-03-21 11:01:42 -0500 | [diff] [blame] | 228 | #define ALTR_OCR_ECC_REG_OFFSET 0x00 |
Thor Thayer | 05b088b | 2016-03-21 11:01:39 -0500 | [diff] [blame] | 229 | #define ALTR_OCR_ECC_EN BIT(0) |
| 230 | #define ALTR_OCR_ECC_INJS BIT(1) |
| 231 | #define ALTR_OCR_ECC_INJD BIT(2) |
| 232 | #define ALTR_OCR_ECC_SERR BIT(3) |
| 233 | #define ALTR_OCR_ECC_DERR BIT(4) |
| 234 | |
| 235 | /* L2 ECC Management Group Defines */ |
| 236 | #define ALTR_MAN_GRP_L2_ECC_OFFSET 0x00 |
Thor Thayer | 811fce4 | 2016-03-21 11:01:42 -0500 | [diff] [blame] | 237 | #define ALTR_L2_ECC_REG_OFFSET 0x00 |
Thor Thayer | 05b088b | 2016-03-21 11:01:39 -0500 | [diff] [blame] | 238 | #define ALTR_L2_ECC_EN BIT(0) |
| 239 | #define ALTR_L2_ECC_INJS BIT(1) |
| 240 | #define ALTR_L2_ECC_INJD BIT(2) |
| 241 | |
Thor Thayer | 588cb03 | 2016-03-21 11:01:44 -0500 | [diff] [blame] | 242 | /* Arria10 General ECC Block Module Defines */ |
Thor Thayer | c7b4be8 | 2016-04-06 20:22:54 -0500 | [diff] [blame] | 243 | #define ALTR_A10_ECC_CTRL_OFST 0x08 |
| 244 | #define ALTR_A10_ECC_EN BIT(0) |
| 245 | #define ALTR_A10_ECC_INITA BIT(16) |
| 246 | #define ALTR_A10_ECC_INITB BIT(24) |
| 247 | |
| 248 | #define ALTR_A10_ECC_INITSTAT_OFST 0x0C |
| 249 | #define ALTR_A10_ECC_INITCOMPLETEA BIT(0) |
| 250 | #define ALTR_A10_ECC_INITCOMPLETEB BIT(8) |
| 251 | |
| 252 | #define ALTR_A10_ECC_ERRINTEN_OFST 0x10 |
Thor Thayer | 1166fde9 | 2016-06-22 08:58:57 -0500 | [diff] [blame] | 253 | #define ALTR_A10_ECC_ERRINTENS_OFST 0x14 |
| 254 | #define ALTR_A10_ECC_ERRINTENR_OFST 0x18 |
Thor Thayer | c7b4be8 | 2016-04-06 20:22:54 -0500 | [diff] [blame] | 255 | #define ALTR_A10_ECC_SERRINTEN BIT(0) |
| 256 | |
Thor Thayer | 1166fde9 | 2016-06-22 08:58:57 -0500 | [diff] [blame] | 257 | #define ALTR_A10_ECC_INTMODE_OFST 0x1C |
| 258 | #define ALTR_A10_ECC_INTMODE BIT(0) |
| 259 | |
Thor Thayer | c7b4be8 | 2016-04-06 20:22:54 -0500 | [diff] [blame] | 260 | #define ALTR_A10_ECC_INTSTAT_OFST 0x20 |
| 261 | #define ALTR_A10_ECC_SERRPENA BIT(0) |
| 262 | #define ALTR_A10_ECC_DERRPENA BIT(8) |
| 263 | #define ALTR_A10_ECC_ERRPENA_MASK (ALTR_A10_ECC_SERRPENA | \ |
| 264 | ALTR_A10_ECC_DERRPENA) |
| 265 | #define ALTR_A10_ECC_SERRPENB BIT(16) |
| 266 | #define ALTR_A10_ECC_DERRPENB BIT(24) |
| 267 | #define ALTR_A10_ECC_ERRPENB_MASK (ALTR_A10_ECC_SERRPENB | \ |
| 268 | ALTR_A10_ECC_DERRPENB) |
| 269 | |
| 270 | #define ALTR_A10_ECC_INTTEST_OFST 0x24 |
| 271 | #define ALTR_A10_ECC_TSERRA BIT(0) |
| 272 | #define ALTR_A10_ECC_TDERRA BIT(8) |
Thor Thayer | 9110498 | 2016-08-09 09:40:52 -0500 | [diff] [blame] | 273 | #define ALTR_A10_ECC_TSERRB BIT(16) |
| 274 | #define ALTR_A10_ECC_TDERRB BIT(24) |
Thor Thayer | c7b4be8 | 2016-04-06 20:22:54 -0500 | [diff] [blame] | 275 | |
| 276 | /* ECC Manager Defines */ |
| 277 | #define A10_SYSMGR_ECC_INTMASK_SET_OFST 0x94 |
| 278 | #define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98 |
| 279 | #define A10_SYSMGR_ECC_INTMASK_OCRAM BIT(1) |
| 280 | |
Thor Thayer | 588cb03 | 2016-03-21 11:01:44 -0500 | [diff] [blame] | 281 | #define A10_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9C |
| 282 | #define A10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0 |
| 283 | #define A10_SYSMGR_ECC_INTSTAT_L2 BIT(0) |
Thor Thayer | c7b4be8 | 2016-04-06 20:22:54 -0500 | [diff] [blame] | 284 | #define A10_SYSMGR_ECC_INTSTAT_OCRAM BIT(1) |
Thor Thayer | 588cb03 | 2016-03-21 11:01:44 -0500 | [diff] [blame] | 285 | |
| 286 | #define A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST 0xA8 |
| 287 | #define A10_SYSGMR_MPU_CLEAR_L2_ECC_SB BIT(15) |
| 288 | #define A10_SYSGMR_MPU_CLEAR_L2_ECC_MB BIT(31) |
| 289 | |
| 290 | /* Arria 10 L2 ECC Management Group Defines */ |
| 291 | #define ALTR_A10_L2_ECC_CTL_OFST 0x0 |
| 292 | #define ALTR_A10_L2_ECC_EN_CTL BIT(0) |
| 293 | |
| 294 | #define ALTR_A10_L2_ECC_STATUS 0xFFD060A4 |
| 295 | #define ALTR_A10_L2_ECC_STAT_OFST 0xA4 |
| 296 | #define ALTR_A10_L2_ECC_SERR_PEND BIT(0) |
| 297 | #define ALTR_A10_L2_ECC_MERR_PEND BIT(0) |
| 298 | |
| 299 | #define ALTR_A10_L2_ECC_CLR_OFST 0x4 |
| 300 | #define ALTR_A10_L2_ECC_SERR_CLR BIT(15) |
| 301 | #define ALTR_A10_L2_ECC_MERR_CLR BIT(31) |
| 302 | |
| 303 | #define ALTR_A10_L2_ECC_INJ_OFST ALTR_A10_L2_ECC_CTL_OFST |
| 304 | #define ALTR_A10_L2_ECC_CE_INJ_MASK 0x00000101 |
| 305 | #define ALTR_A10_L2_ECC_UE_INJ_MASK 0x00010101 |
| 306 | |
Thor Thayer | c7b4be8 | 2016-04-06 20:22:54 -0500 | [diff] [blame] | 307 | /* Arria 10 OCRAM ECC Management Group Defines */ |
| 308 | #define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0)) |
| 309 | |
Thor Thayer | ab8c1e0 | 2016-06-22 08:58:58 -0500 | [diff] [blame] | 310 | /* Arria 10 Ethernet ECC Management Group Defines */ |
| 311 | #define ALTR_A10_COMMON_ECC_EN_CTL BIT(0) |
| 312 | |
Thor Thayer | 9110498 | 2016-08-09 09:40:52 -0500 | [diff] [blame] | 313 | /* Arria 10 SDMMC ECC Management Group Defines */ |
| 314 | #define ALTR_A10_SDMMC_IRQ_MASK (BIT(16) | BIT(15)) |
| 315 | |
Thor Thayer | 1166fde9 | 2016-06-22 08:58:57 -0500 | [diff] [blame] | 316 | /* A10 ECC Controller memory initialization timeout */ |
| 317 | #define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000 |
| 318 | |
Thor Thayer | 3dab6bd | 2018-04-27 13:37:17 -0500 | [diff] [blame] | 319 | /************* Stratix10 Defines **************/ |
| 320 | |
| 321 | /* Stratix10 ECC Manager Defines */ |
| 322 | #define S10_SYSMGR_ECC_INTMASK_VAL_OFST 0xFFD12090 |
| 323 | #define S10_SYSMGR_ECC_INTMASK_SET_OFST 0xFFD12094 |
| 324 | #define S10_SYSMGR_ECC_INTMASK_CLR_OFST 0xFFD12098 |
| 325 | |
| 326 | #define S10_SYSMGR_ECC_INTSTAT_SERR_OFST 0xFFD1209C |
| 327 | #define S10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xFFD120A0 |
| 328 | |
Thor Thayer | e9918d7 | 2018-05-11 18:00:10 -0500 | [diff] [blame] | 329 | #define S10_DDR0_IRQ_MASK BIT(16) |
| 330 | |
Thor Thayer | 328ca7a | 2016-03-21 11:01:40 -0500 | [diff] [blame] | 331 | struct altr_edac_device_dev; |
| 332 | |
Thor Thayer | 05b088b | 2016-03-21 11:01:39 -0500 | [diff] [blame] | 333 | struct edac_device_prv_data { |
Thor Thayer | 328ca7a | 2016-03-21 11:01:40 -0500 | [diff] [blame] | 334 | int (*setup)(struct altr_edac_device_dev *device); |
Thor Thayer | 05b088b | 2016-03-21 11:01:39 -0500 | [diff] [blame] | 335 | int ce_clear_mask; |
| 336 | int ue_clear_mask; |
Thor Thayer | 588cb03 | 2016-03-21 11:01:44 -0500 | [diff] [blame] | 337 | int irq_status_mask; |
Thor Thayer | 05b088b | 2016-03-21 11:01:39 -0500 | [diff] [blame] | 338 | void * (*alloc_mem)(size_t size, void **other); |
| 339 | void (*free_mem)(void *p, size_t size, void *other); |
| 340 | int ecc_enable_mask; |
Thor Thayer | 943ad91 | 2016-03-31 13:48:02 -0500 | [diff] [blame] | 341 | int ecc_en_ofst; |
Thor Thayer | 05b088b | 2016-03-21 11:01:39 -0500 | [diff] [blame] | 342 | int ce_set_mask; |
| 343 | int ue_set_mask; |
Thor Thayer | 811fce4 | 2016-03-21 11:01:42 -0500 | [diff] [blame] | 344 | int set_err_ofst; |
Thor Thayer | 13ab844 | 2016-06-07 15:35:57 -0500 | [diff] [blame] | 345 | irqreturn_t (*ecc_irq_handler)(int irq, void *dev_id); |
Thor Thayer | 05b088b | 2016-03-21 11:01:39 -0500 | [diff] [blame] | 346 | int trig_alloc_sz; |
Thor Thayer | e17ced2 | 2016-03-31 13:48:01 -0500 | [diff] [blame] | 347 | const struct file_operations *inject_fops; |
Thor Thayer | 2b083d6 | 2016-06-22 08:58:53 -0500 | [diff] [blame] | 348 | bool panic; |
Thor Thayer | 05b088b | 2016-03-21 11:01:39 -0500 | [diff] [blame] | 349 | }; |
| 350 | |
| 351 | struct altr_edac_device_dev { |
Thor Thayer | 588cb03 | 2016-03-21 11:01:44 -0500 | [diff] [blame] | 352 | struct list_head next; |
Thor Thayer | 05b088b | 2016-03-21 11:01:39 -0500 | [diff] [blame] | 353 | void __iomem *base; |
| 354 | int sb_irq; |
| 355 | int db_irq; |
| 356 | const struct edac_device_prv_data *data; |
| 357 | struct dentry *debugfs_dir; |
| 358 | char *edac_dev_name; |
Thor Thayer | 588cb03 | 2016-03-21 11:01:44 -0500 | [diff] [blame] | 359 | struct altr_arria10_edac *edac; |
| 360 | struct edac_device_ctl_info *edac_dev; |
| 361 | struct device ddev; |
| 362 | int edac_idx; |
| 363 | }; |
| 364 | |
| 365 | struct altr_arria10_edac { |
| 366 | struct device *dev; |
| 367 | struct regmap *ecc_mgr_map; |
| 368 | int sb_irq; |
| 369 | int db_irq; |
Thor Thayer | 13ab844 | 2016-06-07 15:35:57 -0500 | [diff] [blame] | 370 | struct irq_domain *domain; |
| 371 | struct irq_chip irq_chip; |
Thor Thayer | 588cb03 | 2016-03-21 11:01:44 -0500 | [diff] [blame] | 372 | struct list_head a10_ecc_devices; |
Thor Thayer | 05b088b | 2016-03-21 11:01:39 -0500 | [diff] [blame] | 373 | }; |
| 374 | |
Thor Thayer | 3dab6bd | 2018-04-27 13:37:17 -0500 | [diff] [blame] | 375 | /* |
| 376 | * Functions specified by ARM SMC Calling convention: |
| 377 | * |
| 378 | * FAST call executes atomic operations, returns when the requested operation |
| 379 | * has completed. |
| 380 | * STD call starts a operation which can be preempted by a non-secure |
| 381 | * interrupt. The call can return before the requested operation has |
| 382 | * completed. |
| 383 | * |
| 384 | * a0..a7 is used as register names in the descriptions below, on arm32 |
| 385 | * that translates to r0..r7 and on arm64 to w0..w7. |
| 386 | */ |
| 387 | |
| 388 | #define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \ |
| 389 | ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \ |
| 390 | ARM_SMCCC_OWNER_SIP, (func_num)) |
| 391 | |
| 392 | #define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \ |
| 393 | ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \ |
| 394 | ARM_SMCCC_OWNER_SIP, (func_num)) |
| 395 | |
| 396 | #define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF |
| 397 | #define INTEL_SIP_SMC_STATUS_OK 0x0 |
| 398 | #define INTEL_SIP_SMC_REG_ERROR 0x5 |
| 399 | |
| 400 | /* |
| 401 | * Request INTEL_SIP_SMC_REG_READ |
| 402 | * |
| 403 | * Read a protected register using SMCCC |
| 404 | * |
| 405 | * Call register usage: |
| 406 | * a0: INTEL_SIP_SMC_REG_READ. |
| 407 | * a1: register address. |
| 408 | * a2-7: not used. |
| 409 | * |
| 410 | * Return status: |
| 411 | * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or |
| 412 | * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION |
| 413 | * a1: Value in the register |
| 414 | * a2-3: not used. |
| 415 | */ |
| 416 | #define INTEL_SIP_SMC_FUNCID_REG_READ 7 |
| 417 | #define INTEL_SIP_SMC_REG_READ \ |
| 418 | INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ) |
| 419 | |
| 420 | /* |
| 421 | * Request INTEL_SIP_SMC_REG_WRITE |
| 422 | * |
| 423 | * Write a protected register using SMCCC |
| 424 | * |
| 425 | * Call register usage: |
| 426 | * a0: INTEL_SIP_SMC_REG_WRITE. |
| 427 | * a1: register address |
| 428 | * a2: value to program into register. |
| 429 | * a3-7: not used. |
| 430 | * |
| 431 | * Return status: |
| 432 | * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or |
| 433 | * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION |
| 434 | * a1-3: not used. |
| 435 | */ |
| 436 | #define INTEL_SIP_SMC_FUNCID_REG_WRITE 8 |
| 437 | #define INTEL_SIP_SMC_REG_WRITE \ |
| 438 | INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE) |
| 439 | |
| 440 | struct altr_stratix10_edac { |
| 441 | struct device *dev; |
| 442 | int sb_irq; |
Thor Thayer | 3dab6bd | 2018-04-27 13:37:17 -0500 | [diff] [blame] | 443 | struct irq_domain *domain; |
| 444 | struct irq_chip irq_chip; |
| 445 | struct list_head s10_ecc_devices; |
Thor Thayer | e9918d7 | 2018-05-11 18:00:10 -0500 | [diff] [blame] | 446 | struct notifier_block panic_notifier; |
Thor Thayer | 3dab6bd | 2018-04-27 13:37:17 -0500 | [diff] [blame] | 447 | }; |
| 448 | |
Thor Thayer | 143f4a5 | 2015-06-04 09:28:46 -0500 | [diff] [blame] | 449 | #endif /* #ifndef _ALTERA_EDAC_H */ |