Thomas Gleixner | 82c2981 | 2019-05-28 09:57:05 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 2 | /* |
Grant Likely | c103de2 | 2011-06-04 18:38:28 -0600 | [diff] [blame] | 3 | * Timberdale FPGA GPIO driver |
Paul Gortmaker | 52ad905 | 2016-05-09 19:59:57 -0400 | [diff] [blame] | 4 | * Author: Mocean Laboratories |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 5 | * Copyright (c) 2009 Intel Corporation |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* Supports: |
| 9 | * Timberdale FPGA GPIO |
| 10 | */ |
| 11 | |
Paul Gortmaker | 52ad905 | 2016-05-09 19:59:57 -0400 | [diff] [blame] | 12 | #include <linux/init.h> |
Linus Walleij | 50fe83a | 2018-08-06 17:42:46 +0200 | [diff] [blame] | 13 | #include <linux/gpio/driver.h> |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 14 | #include <linux/platform_device.h> |
David Miller | e3cb91c | 2010-03-05 13:41:36 -0800 | [diff] [blame] | 15 | #include <linux/irq.h> |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 16 | #include <linux/io.h> |
| 17 | #include <linux/timb_gpio.h> |
| 18 | #include <linux/interrupt.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 19 | #include <linux/slab.h> |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 20 | |
| 21 | #define DRIVER_NAME "timb-gpio" |
| 22 | |
| 23 | #define TGPIOVAL 0x00 |
| 24 | #define TGPIODIR 0x04 |
| 25 | #define TGPIO_IER 0x08 |
| 26 | #define TGPIO_ISR 0x0c |
| 27 | #define TGPIO_IPR 0x10 |
| 28 | #define TGPIO_ICR 0x14 |
| 29 | #define TGPIO_FLR 0x18 |
| 30 | #define TGPIO_LVR 0x1c |
Richard Röjfors | 8c35c89 | 2010-03-05 13:44:35 -0800 | [diff] [blame] | 31 | #define TGPIO_VER 0x20 |
| 32 | #define TGPIO_BFLR 0x24 |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 33 | |
| 34 | struct timbgpio { |
| 35 | void __iomem *membase; |
| 36 | spinlock_t lock; /* mutual exclusion */ |
| 37 | struct gpio_chip gpio; |
| 38 | int irq_base; |
Tomas Hallenberg | 76d800a | 2010-10-27 15:33:17 -0700 | [diff] [blame] | 39 | unsigned long last_ier; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 40 | }; |
| 41 | |
| 42 | static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index, |
| 43 | unsigned offset, bool enabled) |
| 44 | { |
Linus Walleij | 92a41e2 | 2015-12-07 14:43:28 +0100 | [diff] [blame] | 45 | struct timbgpio *tgpio = gpiochip_get_data(gpio); |
Chengfeng Ye | 9e8bc2d | 2023-09-26 10:29:14 +0000 | [diff] [blame] | 46 | unsigned long flags; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 47 | u32 reg; |
| 48 | |
Chengfeng Ye | 9e8bc2d | 2023-09-26 10:29:14 +0000 | [diff] [blame] | 49 | spin_lock_irqsave(&tgpio->lock, flags); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 50 | reg = ioread32(tgpio->membase + offset); |
| 51 | |
| 52 | if (enabled) |
| 53 | reg |= (1 << index); |
| 54 | else |
| 55 | reg &= ~(1 << index); |
| 56 | |
| 57 | iowrite32(reg, tgpio->membase + offset); |
Chengfeng Ye | 9e8bc2d | 2023-09-26 10:29:14 +0000 | [diff] [blame] | 58 | spin_unlock_irqrestore(&tgpio->lock, flags); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 59 | |
| 60 | return 0; |
| 61 | } |
| 62 | |
| 63 | static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) |
| 64 | { |
| 65 | return timbgpio_update_bit(gpio, nr, TGPIODIR, true); |
| 66 | } |
| 67 | |
| 68 | static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr) |
| 69 | { |
Linus Walleij | 92a41e2 | 2015-12-07 14:43:28 +0100 | [diff] [blame] | 70 | struct timbgpio *tgpio = gpiochip_get_data(gpio); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 71 | u32 value; |
| 72 | |
| 73 | value = ioread32(tgpio->membase + TGPIOVAL); |
| 74 | return (value & (1 << nr)) ? 1 : 0; |
| 75 | } |
| 76 | |
| 77 | static int timbgpio_gpio_direction_output(struct gpio_chip *gpio, |
| 78 | unsigned nr, int val) |
| 79 | { |
| 80 | return timbgpio_update_bit(gpio, nr, TGPIODIR, false); |
| 81 | } |
| 82 | |
| 83 | static void timbgpio_gpio_set(struct gpio_chip *gpio, |
| 84 | unsigned nr, int val) |
| 85 | { |
| 86 | timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0); |
| 87 | } |
| 88 | |
| 89 | static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset) |
| 90 | { |
Linus Walleij | 92a41e2 | 2015-12-07 14:43:28 +0100 | [diff] [blame] | 91 | struct timbgpio *tgpio = gpiochip_get_data(gpio); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 92 | |
| 93 | if (tgpio->irq_base <= 0) |
| 94 | return -EINVAL; |
| 95 | |
| 96 | return tgpio->irq_base + offset; |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * GPIO IRQ |
| 101 | */ |
Lennert Buytenhek | a1f5f22 | 2011-01-12 17:00:19 -0800 | [diff] [blame] | 102 | static void timbgpio_irq_disable(struct irq_data *d) |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 103 | { |
Lennert Buytenhek | a1f5f22 | 2011-01-12 17:00:19 -0800 | [diff] [blame] | 104 | struct timbgpio *tgpio = irq_data_get_irq_chip_data(d); |
| 105 | int offset = d->irq - tgpio->irq_base; |
Tomas Hallenberg | 76d800a | 2010-10-27 15:33:17 -0700 | [diff] [blame] | 106 | unsigned long flags; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 107 | |
Tomas Hallenberg | 76d800a | 2010-10-27 15:33:17 -0700 | [diff] [blame] | 108 | spin_lock_irqsave(&tgpio->lock, flags); |
Dan Carpenter | d79550a | 2012-10-11 09:56:35 +0300 | [diff] [blame] | 109 | tgpio->last_ier &= ~(1UL << offset); |
Tomas Hallenberg | 76d800a | 2010-10-27 15:33:17 -0700 | [diff] [blame] | 110 | iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); |
| 111 | spin_unlock_irqrestore(&tgpio->lock, flags); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 112 | } |
| 113 | |
Lennert Buytenhek | a1f5f22 | 2011-01-12 17:00:19 -0800 | [diff] [blame] | 114 | static void timbgpio_irq_enable(struct irq_data *d) |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 115 | { |
Lennert Buytenhek | a1f5f22 | 2011-01-12 17:00:19 -0800 | [diff] [blame] | 116 | struct timbgpio *tgpio = irq_data_get_irq_chip_data(d); |
| 117 | int offset = d->irq - tgpio->irq_base; |
Tomas Hallenberg | 76d800a | 2010-10-27 15:33:17 -0700 | [diff] [blame] | 118 | unsigned long flags; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 119 | |
Tomas Hallenberg | 76d800a | 2010-10-27 15:33:17 -0700 | [diff] [blame] | 120 | spin_lock_irqsave(&tgpio->lock, flags); |
Dan Carpenter | d79550a | 2012-10-11 09:56:35 +0300 | [diff] [blame] | 121 | tgpio->last_ier |= 1UL << offset; |
Tomas Hallenberg | 76d800a | 2010-10-27 15:33:17 -0700 | [diff] [blame] | 122 | iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); |
| 123 | spin_unlock_irqrestore(&tgpio->lock, flags); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 124 | } |
| 125 | |
Lennert Buytenhek | a1f5f22 | 2011-01-12 17:00:19 -0800 | [diff] [blame] | 126 | static int timbgpio_irq_type(struct irq_data *d, unsigned trigger) |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 127 | { |
Lennert Buytenhek | a1f5f22 | 2011-01-12 17:00:19 -0800 | [diff] [blame] | 128 | struct timbgpio *tgpio = irq_data_get_irq_chip_data(d); |
| 129 | int offset = d->irq - tgpio->irq_base; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 130 | unsigned long flags; |
Richard Röjfors | 8c35c89 | 2010-03-05 13:44:35 -0800 | [diff] [blame] | 131 | u32 lvr, flr, bflr = 0; |
| 132 | u32 ver; |
Julia Lawall | 2a48180 | 2010-04-06 14:34:48 -0700 | [diff] [blame] | 133 | int ret = 0; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 134 | |
| 135 | if (offset < 0 || offset > tgpio->gpio.ngpio) |
| 136 | return -EINVAL; |
| 137 | |
Richard Röjfors | 8c35c89 | 2010-03-05 13:44:35 -0800 | [diff] [blame] | 138 | ver = ioread32(tgpio->membase + TGPIO_VER); |
| 139 | |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 140 | spin_lock_irqsave(&tgpio->lock, flags); |
| 141 | |
| 142 | lvr = ioread32(tgpio->membase + TGPIO_LVR); |
| 143 | flr = ioread32(tgpio->membase + TGPIO_FLR); |
Richard Röjfors | 8c35c89 | 2010-03-05 13:44:35 -0800 | [diff] [blame] | 144 | if (ver > 2) |
| 145 | bflr = ioread32(tgpio->membase + TGPIO_BFLR); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 146 | |
| 147 | if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
Richard Röjfors | 8c35c89 | 2010-03-05 13:44:35 -0800 | [diff] [blame] | 148 | bflr &= ~(1 << offset); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 149 | flr &= ~(1 << offset); |
| 150 | if (trigger & IRQ_TYPE_LEVEL_HIGH) |
| 151 | lvr |= 1 << offset; |
| 152 | else |
| 153 | lvr &= ~(1 << offset); |
| 154 | } |
| 155 | |
Richard Röjfors | 8c35c89 | 2010-03-05 13:44:35 -0800 | [diff] [blame] | 156 | if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { |
Julia Lawall | 2a48180 | 2010-04-06 14:34:48 -0700 | [diff] [blame] | 157 | if (ver < 3) { |
| 158 | ret = -EINVAL; |
| 159 | goto out; |
Laurent Navet | 8a29a40 | 2013-03-20 13:16:03 +0100 | [diff] [blame] | 160 | } else { |
Richard Röjfors | 8c35c89 | 2010-03-05 13:44:35 -0800 | [diff] [blame] | 161 | flr |= 1 << offset; |
| 162 | bflr |= 1 << offset; |
| 163 | } |
| 164 | } else { |
| 165 | bflr &= ~(1 << offset); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 166 | flr |= 1 << offset; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 167 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 168 | lvr &= ~(1 << offset); |
Richard Röjfors | 8c35c89 | 2010-03-05 13:44:35 -0800 | [diff] [blame] | 169 | else |
| 170 | lvr |= 1 << offset; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 171 | } |
| 172 | |
| 173 | iowrite32(lvr, tgpio->membase + TGPIO_LVR); |
| 174 | iowrite32(flr, tgpio->membase + TGPIO_FLR); |
Richard Röjfors | 8c35c89 | 2010-03-05 13:44:35 -0800 | [diff] [blame] | 175 | if (ver > 2) |
| 176 | iowrite32(bflr, tgpio->membase + TGPIO_BFLR); |
| 177 | |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 178 | iowrite32(1 << offset, tgpio->membase + TGPIO_ICR); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 179 | |
Julia Lawall | 2a48180 | 2010-04-06 14:34:48 -0700 | [diff] [blame] | 180 | out: |
| 181 | spin_unlock_irqrestore(&tgpio->lock, flags); |
| 182 | return ret; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 183 | } |
| 184 | |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 185 | static void timbgpio_irq(struct irq_desc *desc) |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 186 | { |
Jiang Liu | 476f8b4 | 2015-06-04 12:13:15 +0800 | [diff] [blame] | 187 | struct timbgpio *tgpio = irq_desc_get_handler_data(desc); |
| 188 | struct irq_data *data = irq_desc_get_irq_data(desc); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 189 | unsigned long ipr; |
| 190 | int offset; |
| 191 | |
Jiang Liu | 476f8b4 | 2015-06-04 12:13:15 +0800 | [diff] [blame] | 192 | data->chip->irq_ack(data); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 193 | ipr = ioread32(tgpio->membase + TGPIO_IPR); |
| 194 | iowrite32(ipr, tgpio->membase + TGPIO_ICR); |
| 195 | |
Tomas Hallenberg | 76d800a | 2010-10-27 15:33:17 -0700 | [diff] [blame] | 196 | /* |
| 197 | * Some versions of the hardware trash the IER register if more than |
| 198 | * one interrupt is received simultaneously. |
| 199 | */ |
| 200 | iowrite32(0, tgpio->membase + TGPIO_IER); |
| 201 | |
Akinobu Mita | 984b3f5 | 2010-03-05 13:41:37 -0800 | [diff] [blame] | 202 | for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio) |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 203 | generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset)); |
Tomas Hallenberg | 76d800a | 2010-10-27 15:33:17 -0700 | [diff] [blame] | 204 | |
| 205 | iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 206 | } |
| 207 | |
| 208 | static struct irq_chip timbgpio_irqchip = { |
| 209 | .name = "GPIO", |
Lennert Buytenhek | a1f5f22 | 2011-01-12 17:00:19 -0800 | [diff] [blame] | 210 | .irq_enable = timbgpio_irq_enable, |
| 211 | .irq_disable = timbgpio_irq_disable, |
| 212 | .irq_set_type = timbgpio_irq_type, |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 213 | }; |
| 214 | |
Bill Pemberton | 3836309 | 2012-11-19 13:22:34 -0500 | [diff] [blame] | 215 | static int timbgpio_probe(struct platform_device *pdev) |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 216 | { |
| 217 | int err, i; |
abdoulaye berthe | 0ed3398 | 2014-05-13 03:21:42 +0200 | [diff] [blame] | 218 | struct device *dev = &pdev->dev; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 219 | struct gpio_chip *gc; |
| 220 | struct timbgpio *tgpio; |
Jingoo Han | e56aee1 | 2013-07-30 17:08:05 +0900 | [diff] [blame] | 221 | struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 222 | int irq = platform_get_irq(pdev, 0); |
| 223 | |
| 224 | if (!pdata || pdata->nr_pins > 32) { |
abdoulaye berthe | 0ed3398 | 2014-05-13 03:21:42 +0200 | [diff] [blame] | 225 | dev_err(dev, "Invalid platform data\n"); |
| 226 | return -EINVAL; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 227 | } |
| 228 | |
Markus Elfring | 2c3087e | 2018-02-10 21:13:28 +0100 | [diff] [blame] | 229 | tgpio = devm_kzalloc(dev, sizeof(*tgpio), GFP_KERNEL); |
Markus Elfring | 587ca5e | 2018-02-10 21:09:08 +0100 | [diff] [blame] | 230 | if (!tgpio) |
abdoulaye berthe | 0ed3398 | 2014-05-13 03:21:42 +0200 | [diff] [blame] | 231 | return -EINVAL; |
Markus Elfring | 587ca5e | 2018-02-10 21:09:08 +0100 | [diff] [blame] | 232 | |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 233 | tgpio->irq_base = pdata->irq_base; |
| 234 | |
| 235 | spin_lock_init(&tgpio->lock); |
| 236 | |
Enrico Weigelt, metux IT consult | aa6c9b9 | 2019-03-11 19:55:13 +0100 | [diff] [blame] | 237 | tgpio->membase = devm_platform_ioremap_resource(pdev, 0); |
Amitoj Kaur Chawla | fa283db | 2016-02-28 18:00:56 +0530 | [diff] [blame] | 238 | if (IS_ERR(tgpio->membase)) |
| 239 | return PTR_ERR(tgpio->membase); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 240 | |
| 241 | gc = &tgpio->gpio; |
| 242 | |
| 243 | gc->label = dev_name(&pdev->dev); |
| 244 | gc->owner = THIS_MODULE; |
Linus Walleij | 58383c78 | 2015-11-04 09:56:26 +0100 | [diff] [blame] | 245 | gc->parent = &pdev->dev; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 246 | gc->direction_input = timbgpio_gpio_direction_input; |
| 247 | gc->get = timbgpio_gpio_get; |
| 248 | gc->direction_output = timbgpio_gpio_direction_output; |
| 249 | gc->set = timbgpio_gpio_set; |
| 250 | gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL; |
| 251 | gc->dbg_show = NULL; |
| 252 | gc->base = pdata->gpio_base; |
| 253 | gc->ngpio = pdata->nr_pins; |
Linus Walleij | 9fb1f39 | 2013-12-04 14:42:46 +0100 | [diff] [blame] | 254 | gc->can_sleep = false; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 255 | |
Laxman Dewangan | 43fad83 | 2016-02-22 17:43:28 +0530 | [diff] [blame] | 256 | err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 257 | if (err) |
abdoulaye berthe | 0ed3398 | 2014-05-13 03:21:42 +0200 | [diff] [blame] | 258 | return err; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 259 | |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 260 | /* make sure to disable interrupts */ |
| 261 | iowrite32(0x0, tgpio->membase + TGPIO_IER); |
| 262 | |
| 263 | if (irq < 0 || tgpio->irq_base <= 0) |
| 264 | return 0; |
| 265 | |
| 266 | for (i = 0; i < pdata->nr_pins; i++) { |
Linus Walleij | e5428a6 | 2013-11-26 14:28:32 +0100 | [diff] [blame] | 267 | irq_set_chip_and_handler(tgpio->irq_base + i, |
| 268 | &timbgpio_irqchip, handle_simple_irq); |
Thomas Gleixner | b51804b | 2011-03-24 21:27:36 +0000 | [diff] [blame] | 269 | irq_set_chip_data(tgpio->irq_base + i, tgpio); |
Rob Herring | 23393d4 | 2015-07-27 15:55:16 -0500 | [diff] [blame] | 270 | irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 271 | } |
| 272 | |
Thomas Gleixner | 8a52211 | 2015-06-21 21:10:47 +0200 | [diff] [blame] | 273 | irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio); |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 274 | |
| 275 | return 0; |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 276 | } |
| 277 | |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 278 | static struct platform_driver timbgpio_platform_driver = { |
| 279 | .driver = { |
Paul Gortmaker | 52ad905 | 2016-05-09 19:59:57 -0400 | [diff] [blame] | 280 | .name = DRIVER_NAME, |
| 281 | .suppress_bind_attrs = true, |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 282 | }, |
| 283 | .probe = timbgpio_probe, |
Richard Röjfors | 35570ac | 2009-12-15 16:46:18 -0800 | [diff] [blame] | 284 | }; |
| 285 | |
| 286 | /*--------------------------------------------------------------------------*/ |
| 287 | |
Paul Gortmaker | 52ad905 | 2016-05-09 19:59:57 -0400 | [diff] [blame] | 288 | builtin_platform_driver(timbgpio_platform_driver); |