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Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Neil Zhang75b1bdf2012-05-03 14:19:13 +08002/*
3 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
Neil Zhang75b1bdf2012-05-03 14:19:13 +08004 */
5
6#ifndef __ASM_ARCH_REGS_USB_H
7#define __ASM_ARCH_REGS_USB_H
8
9#define PXA168_U2O_REGBASE (0xd4208000)
10#define PXA168_U2O_PHYBASE (0xd4207000)
11
12#define PXA168_U2H_REGBASE (0xd4209000)
13#define PXA168_U2H_PHYBASE (0xd4206000)
14
15#define MMP3_HSIC1_REGBASE (0xf0001000)
16#define MMP3_HSIC1_PHYBASE (0xf0001800)
17
18#define MMP3_HSIC2_REGBASE (0xf0002000)
19#define MMP3_HSIC2_PHYBASE (0xf0002800)
20
21#define MMP3_FSIC_REGBASE (0xf0003000)
22#define MMP3_FSIC_PHYBASE (0xf0003800)
23
24
25#define USB_REG_RANGE (0x1ff)
26#define USB_PHY_RANGE (0xff)
27
28/* registers */
29#define U2x_CAPREGS_OFFSET 0x100
30
31/* phy regs */
32#define UTMI_REVISION 0x0
33#define UTMI_CTRL 0x4
34#define UTMI_PLL 0x8
35#define UTMI_TX 0xc
36#define UTMI_RX 0x10
37#define UTMI_IVREF 0x14
38#define UTMI_T0 0x18
39#define UTMI_T1 0x1c
40#define UTMI_T2 0x20
41#define UTMI_T3 0x24
42#define UTMI_T4 0x28
43#define UTMI_T5 0x2c
44#define UTMI_RESERVE 0x30
45#define UTMI_USB_INT 0x34
46#define UTMI_DBG_CTL 0x38
47#define UTMI_OTG_ADDON 0x3c
48
49/* For UTMICTRL Register */
50#define UTMI_CTRL_USB_CLK_EN (1 << 31)
51/* pxa168 */
52#define UTMI_CTRL_SUSPEND_SET1 (1 << 30)
53#define UTMI_CTRL_SUSPEND_SET2 (1 << 29)
54#define UTMI_CTRL_RXBUF_PDWN (1 << 24)
55#define UTMI_CTRL_TXBUF_PDWN (1 << 11)
56
57#define UTMI_CTRL_INPKT_DELAY_SHIFT 30
58#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT 28
59#define UTMI_CTRL_PU_REF_SHIFT 20
60#define UTMI_CTRL_ARC_PULLDN_SHIFT 12
61#define UTMI_CTRL_PLL_PWR_UP_SHIFT 1
62#define UTMI_CTRL_PWR_UP_SHIFT 0
63
64/* For UTMI_PLL Register */
65#define UTMI_PLL_PLLCALI12_SHIFT 29
66#define UTMI_PLL_PLLCALI12_MASK (0x3 << 29)
67
68#define UTMI_PLL_PLLVDD18_SHIFT 27
69#define UTMI_PLL_PLLVDD18_MASK (0x3 << 27)
70
71#define UTMI_PLL_PLLVDD12_SHIFT 25
72#define UTMI_PLL_PLLVDD12_MASK (0x3 << 25)
73
74#define UTMI_PLL_CLK_BLK_EN_SHIFT 24
75#define CLK_BLK_EN (0x1 << 24)
76#define PLL_READY (0x1 << 23)
77#define KVCO_EXT (0x1 << 22)
78#define VCOCAL_START (0x1 << 21)
79
80#define UTMI_PLL_KVCO_SHIFT 15
81#define UTMI_PLL_KVCO_MASK (0x7 << 15)
82
83#define UTMI_PLL_ICP_SHIFT 12
84#define UTMI_PLL_ICP_MASK (0x7 << 12)
85
86#define UTMI_PLL_FBDIV_SHIFT 4
87#define UTMI_PLL_FBDIV_MASK (0xFF << 4)
88
89#define UTMI_PLL_REFDIV_SHIFT 0
90#define UTMI_PLL_REFDIV_MASK (0xF << 0)
91
92/* For UTMI_TX Register */
93#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT 27
94#define UTMI_TX_REG_EXT_FS_RCAL_MASK (0xf << 27)
95
96#define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT 26
97#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK (0x1 << 26)
98
99#define UTMI_TX_TXVDD12_SHIFT 22
100#define UTMI_TX_TXVDD12_MASK (0x3 << 22)
101
102#define UTMI_TX_CK60_PHSEL_SHIFT 17
103#define UTMI_TX_CK60_PHSEL_MASK (0xf << 17)
104
105#define UTMI_TX_IMPCAL_VTH_SHIFT 14
106#define UTMI_TX_IMPCAL_VTH_MASK (0x7 << 14)
107
108#define REG_RCAL_START (0x1 << 12)
109
110#define UTMI_TX_LOW_VDD_EN_SHIFT 11
111
112#define UTMI_TX_AMP_SHIFT 0
113#define UTMI_TX_AMP_MASK (0x7 << 0)
114
115/* For UTMI_RX Register */
116#define UTMI_REG_SQ_LENGTH_SHIFT 15
117#define UTMI_REG_SQ_LENGTH_MASK (0x3 << 15)
118
119#define UTMI_RX_SQ_THRESH_SHIFT 4
120#define UTMI_RX_SQ_THRESH_MASK (0xf << 4)
121
122#define UTMI_OTG_ADDON_OTG_ON (1 << 0)
123
Neil Zhang75b1bdf2012-05-03 14:19:13 +0800124/* fsic registers */
125#define FSIC_MISC 0x4
126#define FSIC_INT 0x28
127#define FSIC_CTRL 0x30
128
129/* HSIC registers */
130#define HSIC_PAD_CTRL 0x4
131
132#define HSIC_CTRL 0x8
133#define HSIC_CTRL_HSIC_ENABLE (1<<7)
134#define HSIC_CTRL_PLL_BYPASS (1<<4)
135
136#define TEST_GRP_0 0xc
137#define TEST_GRP_1 0x10
138
139#define HSIC_INT 0x14
140#define HSIC_INT_READY_INT_EN (1<<10)
141#define HSIC_INT_CONNECT_INT_EN (1<<9)
142#define HSIC_INT_CORE_INT_EN (1<<8)
143#define HSIC_INT_HS_READY (1<<2)
144#define HSIC_INT_CONNECT (1<<1)
145#define HSIC_INT_CORE (1<<0)
146
147#define HSIC_CONFIG 0x18
148#define USBHSIC_CTRL 0x20
149
150#define HSIC_USB_CTRL 0x28
151#define HSIC_USB_CTRL_CLKEN 1
152#define HSIC_USB_CLK_PHY 0x0
153#define HSIC_USB_CLK_PMU 0x1
154
155#endif /* __ASM_ARCH_PXA_U2O_H */