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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Russell King4baa9922008-08-02 10:55:55 +01002 * arch/arm/include/asm/io.h
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Copyright (C) 1996-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Modifications:
11 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
12 * constant addresses and variable addresses.
13 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
14 * specific IO header files.
15 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
16 * 04-Apr-1999 PJB Added check_signature.
17 * 12-Dec-1999 RMK More cleanups
18 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
19 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
20 */
21#ifndef __ASM_ARM_IO_H
22#define __ASM_ARM_IO_H
23
24#ifdef __KERNEL__
25
Russell King7ddfe622015-05-07 14:22:40 +010026#include <linux/string.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#include <linux/types.h>
Stefano Stabellini3d1975b2013-10-25 10:33:26 +000028#include <linux/blk_types.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <asm/byteorder.h>
30#include <asm/memory.h>
Michael S. Tsirkine5bfb722011-11-24 20:57:23 +020031#include <asm-generic/pci_iomap.h>
Stefano Stabellini3d1975b2013-10-25 10:33:26 +000032#include <xen/xen.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
34/*
35 * ISA I/O bus memory addresses are 1:1 with the physical address.
36 */
37#define isa_virt_to_bus virt_to_phys
38#define isa_page_to_bus page_to_phys
39#define isa_bus_to_virt phys_to_virt
40
41/*
Ezequiel Garciac5ca95b2013-12-18 23:08:52 +010042 * Atomic MMIO-wide IO modify
43 */
44extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set);
45extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
46
47/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070048 * Generic IO read/write. These perform native-endian accesses. Note
49 * that some architectures will want to re-define __raw_{read,write}w.
50 */
Thierry Reding84c4d3a2014-07-28 16:34:18 +020051void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen);
52void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen);
53void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen);
Linus Torvalds1da177e2005-04-16 15:20:36 -070054
Thierry Reding84c4d3a2014-07-28 16:34:18 +020055void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen);
56void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen);
57void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
Linus Torvalds1da177e2005-04-16 15:20:36 -070058
Will Deacon195bbcac2012-08-24 15:18:45 +010059#if __LINUX_ARM_ARCH__ < 6
60/*
61 * Half-word accesses are problematic with RiscPC due to limitations of
62 * the bus. Rather than special-case the machine, just let the compiler
63 * generate the access for CPUs prior to ARMv6.
64 */
65#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
66#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
67#else
68/*
69 * When running under a hypervisor, we want to avoid I/O accesses with
70 * writeback addressing modes as these incur a significant performance
71 * overhead (the address generation must be emulated in software).
72 */
Thierry Reding84c4d3a2014-07-28 16:34:18 +020073#define __raw_writew __raw_writew
Will Deacon195bbcac2012-08-24 15:18:45 +010074static inline void __raw_writew(u16 val, volatile void __iomem *addr)
75{
76 asm volatile("strh %1, %0"
Peter Hurley5bb5d662015-04-13 14:18:50 +010077 : : "Q" (*(volatile u16 __force *)addr), "r" (val));
Will Deacon195bbcac2012-08-24 15:18:45 +010078}
Linus Torvalds1da177e2005-04-16 15:20:36 -070079
Thierry Reding84c4d3a2014-07-28 16:34:18 +020080#define __raw_readw __raw_readw
Will Deacon195bbcac2012-08-24 15:18:45 +010081static inline u16 __raw_readw(const volatile void __iomem *addr)
82{
83 u16 val;
Peter Hurley5bb5d662015-04-13 14:18:50 +010084 asm volatile("ldrh %0, %1"
85 : "=r" (val)
86 : "Q" (*(volatile u16 __force *)addr));
Will Deacon195bbcac2012-08-24 15:18:45 +010087 return val;
88}
89#endif
90
Thierry Reding84c4d3a2014-07-28 16:34:18 +020091#define __raw_writeb __raw_writeb
Will Deacon195bbcac2012-08-24 15:18:45 +010092static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
93{
94 asm volatile("strb %1, %0"
Peter Hurley5bb5d662015-04-13 14:18:50 +010095 : : "Qo" (*(volatile u8 __force *)addr), "r" (val));
Will Deacon195bbcac2012-08-24 15:18:45 +010096}
97
Thierry Reding84c4d3a2014-07-28 16:34:18 +020098#define __raw_writel __raw_writel
Will Deacon195bbcac2012-08-24 15:18:45 +010099static inline void __raw_writel(u32 val, volatile void __iomem *addr)
100{
101 asm volatile("str %1, %0"
Peter Hurley5bb5d662015-04-13 14:18:50 +0100102 : : "Qo" (*(volatile u32 __force *)addr), "r" (val));
Will Deacon195bbcac2012-08-24 15:18:45 +0100103}
104
Thierry Reding84c4d3a2014-07-28 16:34:18 +0200105#define __raw_readb __raw_readb
Will Deacon195bbcac2012-08-24 15:18:45 +0100106static inline u8 __raw_readb(const volatile void __iomem *addr)
107{
108 u8 val;
Peter Hurley5bb5d662015-04-13 14:18:50 +0100109 asm volatile("ldrb %0, %1"
110 : "=r" (val)
111 : "Qo" (*(volatile u8 __force *)addr));
Will Deacon195bbcac2012-08-24 15:18:45 +0100112 return val;
113}
114
Thierry Reding84c4d3a2014-07-28 16:34:18 +0200115#define __raw_readl __raw_readl
Will Deacon195bbcac2012-08-24 15:18:45 +0100116static inline u32 __raw_readl(const volatile void __iomem *addr)
117{
118 u32 val;
Peter Hurley5bb5d662015-04-13 14:18:50 +0100119 asm volatile("ldr %0, %1"
120 : "=r" (val)
121 : "Qo" (*(volatile u32 __force *)addr));
Will Deacon195bbcac2012-08-24 15:18:45 +0100122 return val;
123}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124
125/*
Russell King67a19012005-11-17 16:48:00 +0000126 * Architecture ioremap implementation.
127 */
Russell King3603ab22007-05-05 20:59:27 +0100128#define MT_DEVICE 0
129#define MT_DEVICE_NONSHARED 1
130#define MT_DEVICE_CACHED 2
Russell Kingdb5b7162008-09-07 12:42:51 +0100131#define MT_DEVICE_WC 3
Russell King3603ab22007-05-05 20:59:27 +0100132/*
Russell Kingdb5b7162008-09-07 12:42:51 +0100133 * types 4 onwards can be found in asm/mach/map.h and are undefined
Russell King3603ab22007-05-05 20:59:27 +0100134 * for ioremap
135 */
136
137/*
138 * __arm_ioremap takes CPU physical address.
139 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
Russell King31aa8fd2009-12-18 11:10:03 +0000140 * The _caller variety takes a __builtin_return_address(0) value for
141 * /proc/vmalloc to use - and should only be used in non-inline functions.
Russell King3603ab22007-05-05 20:59:27 +0100142 */
Laura Abbott9b971732013-05-16 19:40:22 +0100143extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
Russell King31aa8fd2009-12-18 11:10:03 +0000144 void *);
Russell King31aa8fd2009-12-18 11:10:03 +0000145extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
Laura Abbott9b971732013-05-16 19:40:22 +0100146extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
Al Viro16226052006-10-09 02:09:49 +0100147extern void __iounmap(volatile void __iomem *addr);
Rob Herring4fe7ef32012-02-10 17:05:13 -0600148
Laura Abbott9b971732013-05-16 19:40:22 +0100149extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
Rob Herring4fe7ef32012-02-10 17:05:13 -0600150 unsigned int, void *);
151extern void (*arch_iounmap)(volatile void __iomem *);
Russell King67a19012005-11-17 16:48:00 +0000152
153/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154 * Bad read/write accesses...
155 */
156extern void __readwrite_bug(const char *fn);
157
158/*
Russell King0560cf52008-11-30 11:45:54 +0000159 * A typesafe __io() helper
160 */
161static inline void __iomem *__typesafe_io(unsigned long addr)
162{
163 return (void __iomem *)addr;
164}
165
Rob Herring6f6f6a72012-03-10 10:30:31 -0600166#define IOMEM(x) ((void __force __iomem *)(x))
167
Russell Kingc1928022011-01-30 11:29:40 +0000168/* IO barriers */
169#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
David Howells9f97da72012-03-28 18:30:01 +0100170#include <asm/barrier.h>
Russell Kingc1928022011-01-30 11:29:40 +0000171#define __iormb() rmb()
172#define __iowmb() wmb()
173#else
174#define __iormb() do { } while (0)
175#define __iowmb() do { } while (0)
176#endif
177
Rob Herringc2794432012-02-29 18:10:58 -0600178/* PCI fixed i/o mapping */
179#define PCI_IO_VIRT_BASE 0xfee00000
Liviu Dudaudad13e32014-09-29 15:29:22 +0100180#define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)
Rob Herringc2794432012-02-29 18:10:58 -0600181
Thomas Petazzoni1c8c3cf02014-05-19 11:04:39 +0100182#if defined(CONFIG_PCI)
183void pci_ioremap_set_mem_type(int mem_type);
184#else
185static inline void pci_ioremap_set_mem_type(int mem_type) {}
186#endif
187
Rob Herringc2794432012-02-29 18:10:58 -0600188extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
189
Russell King0560cf52008-11-30 11:45:54 +0000190/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191 * Now, pick up the machine-defined IO definitions
192 */
Rob Herringc334bc12012-03-04 22:03:33 -0600193#ifdef CONFIG_NEED_MACH_IO_H
Russell Kinga09e64f2008-08-05 16:14:15 +0100194#include <mach/io.h>
Rob Herringc2794432012-02-29 18:10:58 -0600195#elif defined(CONFIG_PCI)
196#define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
197#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
Rob Herringc334bc12012-03-04 22:03:33 -0600198#else
Rob Herring1ac02d72012-04-04 17:48:04 -0500199#define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
Rob Herringc334bc12012-03-04 22:03:33 -0600200#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202/*
Russell King04e1c832011-07-06 12:49:59 +0100203 * This is the limit of PC card/PCI/ISA IO space, which is by default
204 * 64K if we have PC card, PCI or ISA support. Otherwise, default to
205 * zero to prevent ISA/PCI drivers claiming IO space (and potentially
206 * oopsing.)
207 *
208 * Only set this larger if you really need inb() et.al. to operate over
209 * a larger address space. Note that SOC_COMMON ioremaps each sockets
210 * IO space area, and so inb() et.al. must be defined to operate as per
211 * readb() et.al. on such platforms.
212 */
213#ifndef IO_SPACE_LIMIT
214#if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
215#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
216#elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
217#define IO_SPACE_LIMIT ((resource_size_t)0xffff)
218#else
219#define IO_SPACE_LIMIT ((resource_size_t)0)
220#endif
221#endif
222
223/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 * IO port access primitives
225 * -------------------------
226 *
227 * The ARM doesn't have special IO access instructions; all IO is memory
228 * mapped. Note that these are defined to perform little endian accesses
229 * only. Their primary purpose is to access PCI and ISA peripherals.
230 *
231 * Note that for a big endian machine, this implies that the following
Russell Kingc79ebfa2005-06-27 14:23:38 +0100232 * big endian mode connectivity is in place, as described by numerous
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 * ARM documents:
234 *
235 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
236 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
237 *
238 * The machine specific io.h include defines __io to translate an "IO"
239 * address to a memory address.
240 *
241 * Note that we prevent GCC re-ordering or caching values in expressions
242 * by introducing sequence points into the in*() definitions. Note that
243 * __raw_* do not guarantee this behaviour.
244 *
245 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
246 */
247#ifdef __io
Russell Kingc1928022011-01-30 11:29:40 +0000248#define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
249#define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
250 cpu_to_le16(v),__io(p)); })
251#define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
252 cpu_to_le32(v),__io(p)); })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253
Russell Kingc1928022011-01-30 11:29:40 +0000254#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
Olav Kongas05f98692005-04-29 22:08:34 +0100255#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
Russell Kingc1928022011-01-30 11:29:40 +0000256 __raw_readw(__io(p))); __iormb(); __v; })
Olav Kongas05f98692005-04-29 22:08:34 +0100257#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
Russell Kingc1928022011-01-30 11:29:40 +0000258 __raw_readl(__io(p))); __iormb(); __v; })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259
260#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
261#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
262#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
263
264#define insb(p,d,l) __raw_readsb(__io(p),d,l)
265#define insw(p,d,l) __raw_readsw(__io(p),d,l)
266#define insl(p,d,l) __raw_readsl(__io(p),d,l)
267#endif
268
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269/*
270 * String version of IO memory access ops:
271 */
Russell Kingd2f60742005-09-24 10:42:06 +0100272extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
273extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
274extern void _memset_io(volatile void __iomem *, int, size_t);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275
276#define mmiowb()
277
278/*
279 * Memory access primitives
280 * ------------------------
281 *
282 * These perform PCI memory accesses via an ioremap region. They don't
283 * take an address as such, but a cookie.
284 *
285 * Again, this are defined to perform little endian accesses. See the
286 * IO port primitives for more information.
287 */
Rob Herring5621caa2012-02-10 20:04:56 -0600288#ifndef readl
289#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
Olof Johanssonb0c12642011-10-04 03:44:07 +0100290#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
Rob Herring5621caa2012-02-10 20:04:56 -0600291 __raw_readw(c)); __r; })
Olof Johanssonb0c12642011-10-04 03:44:07 +0100292#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
Rob Herring5621caa2012-02-10 20:04:56 -0600293 __raw_readl(c)); __r; })
Catalin Marinase9367712010-07-28 22:00:54 +0100294
Russell Kingaf06bb92012-05-25 08:39:25 +0100295#define writeb_relaxed(v,c) __raw_writeb(v,c)
296#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
297#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
Catalin Marinase9367712010-07-28 22:00:54 +0100298
Russell Kingb92b3612010-07-29 11:38:05 +0100299#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
300#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
301#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
302
303#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
304#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
305#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
306
Rob Herring5621caa2012-02-10 20:04:56 -0600307#define readsb(p,d,l) __raw_readsb(p,d,l)
308#define readsw(p,d,l) __raw_readsw(p,d,l)
309#define readsl(p,d,l) __raw_readsl(p,d,l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310
Rob Herring5621caa2012-02-10 20:04:56 -0600311#define writesb(p,d,l) __raw_writesb(p,d,l)
312#define writesw(p,d,l) __raw_writesw(p,d,l)
313#define writesl(p,d,l) __raw_writesl(p,d,l)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314
Russell King7ddfe622015-05-07 14:22:40 +0100315#ifndef __ARMBE__
316static inline void memset_io(volatile void __iomem *dst, unsigned c,
317 size_t count)
318{
Russell King1bd46782015-07-03 15:22:54 +0100319 extern void mmioset(void *, unsigned int, size_t);
320 mmioset((void __force *)dst, c, count);
Russell King7ddfe622015-05-07 14:22:40 +0100321}
322#define memset_io(dst,c,count) memset_io(dst,c,count)
323
324static inline void memcpy_fromio(void *to, const volatile void __iomem *from,
325 size_t count)
326{
Russell King1bd46782015-07-03 15:22:54 +0100327 extern void mmiocpy(void *, const void *, size_t);
328 mmiocpy(to, (const void __force *)from, count);
Russell King7ddfe622015-05-07 14:22:40 +0100329}
330#define memcpy_fromio(to,from,count) memcpy_fromio(to,from,count)
331
332static inline void memcpy_toio(volatile void __iomem *to, const void *from,
333 size_t count)
334{
Russell King1bd46782015-07-03 15:22:54 +0100335 extern void mmiocpy(void *, const void *, size_t);
336 mmiocpy((void __force *)to, from, count);
Russell King7ddfe622015-05-07 14:22:40 +0100337}
338#define memcpy_toio(to,from,count) memcpy_toio(to,from,count)
339
340#else
Rob Herring5621caa2012-02-10 20:04:56 -0600341#define memset_io(c,v,l) _memset_io(c,(v),(l))
342#define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
343#define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
Russell King7ddfe622015-05-07 14:22:40 +0100344#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700345
Rob Herring5621caa2012-02-10 20:04:56 -0600346#endif /* readl */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347
348/*
Russell Kingac5e2f12015-07-01 10:02:39 +0100349 * ioremap() and friends.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350 *
Russell Kingac5e2f12015-07-01 10:02:39 +0100351 * ioremap() takes a resource address, and size. Due to the ARM memory
352 * types, it is important to use the correct ioremap() function as each
353 * mapping has specific properties.
Deepak Saxena9d4ae722006-01-09 19:23:11 +0000354 *
Russell Kingac5e2f12015-07-01 10:02:39 +0100355 * Function Memory type Cacheability Cache hint
356 * ioremap() Device n/a n/a
357 * ioremap_nocache() Device n/a n/a
358 * ioremap_cache() Normal Writeback Read allocate
359 * ioremap_wc() Normal Non-cacheable n/a
360 * ioremap_wt() Normal Non-cacheable n/a
361 *
362 * All device mappings have the following properties:
363 * - no access speculation
364 * - no repetition (eg, on return from an exception)
365 * - number, order and size of accesses are maintained
366 * - unaligned accesses are "unpredictable"
367 * - writes may be delayed before they hit the endpoint device
368 *
369 * ioremap_nocache() is the same as ioremap() as there are too many device
370 * drivers using this for device registers, and documentation which tells
371 * people to use it for such for this to be any different. This is not a
372 * safe fallback for memory-like mappings, or memory regions where the
373 * compiler may generate unaligned accesses - eg, via inlining its own
374 * memcpy.
375 *
376 * All normal memory mappings have the following properties:
377 * - reads can be repeated with no side effects
378 * - repeated reads return the last value written
379 * - reads can fetch additional locations without side effects
380 * - writes can be repeated (in certain cases) with no side effects
381 * - writes can be merged before accessing the target
382 * - unaligned accesses can be supported
383 * - ordering is not guaranteed without explicit dependencies or barrier
384 * instructions
385 * - writes may be delayed before they hit the endpoint memory
386 *
387 * The cache hint is only a performance hint: CPUs may alias these hints.
388 * Eg, a CPU not implementing read allocate but implementing write allocate
389 * will provide a write allocate mapping instead.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390 */
Russell King20a10802015-07-01 10:06:32 +0100391void __iomem *ioremap(resource_size_t res_cookie, size_t size);
392#define ioremap ioremap
393#define ioremap_nocache ioremap
394
395void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size);
396#define ioremap_cache ioremap_cache
397
398void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
399#define ioremap_wc ioremap_wc
400#define ioremap_wt ioremap_wc
401
402void iounmap(volatile void __iomem *iomem_cookie);
403#define iounmap iounmap
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404
405/*
Thierry Reding84c4d3a2014-07-28 16:34:18 +0200406 * io{read,write}{16,32}be() macros
Russell King09f05512005-06-20 18:44:37 +0100407 */
Thierry Reding84c4d3a2014-07-28 16:34:18 +0200408#define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
409#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
Russell King09f05512005-06-20 18:44:37 +0100410
Thierry Reding84c4d3a2014-07-28 16:34:18 +0200411#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
412#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
Arnd Bergmann06901bd2011-09-03 17:54:44 +0200413
Thierry Reding84c4d3a2014-07-28 16:34:18 +0200414#ifndef ioport_map
415#define ioport_map ioport_map
Russell King09f05512005-06-20 18:44:37 +0100416extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
Thierry Reding84c4d3a2014-07-28 16:34:18 +0200417#endif
418#ifndef ioport_unmap
419#define ioport_unmap ioport_unmap
Russell King09f05512005-06-20 18:44:37 +0100420extern void ioport_unmap(void __iomem *addr);
Lennert Buytenhek7533fca2005-06-24 23:11:31 +0100421#endif
Russell King09f05512005-06-20 18:44:37 +0100422
423struct pci_dev;
424
Thierry Reding84c4d3a2014-07-28 16:34:18 +0200425#define pci_iounmap pci_iounmap
Russell King09f05512005-06-20 18:44:37 +0100426extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
427
428/*
Thierry Reding84c4d3a2014-07-28 16:34:18 +0200429 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
430 * access
431 */
432#define xlate_dev_mem_ptr(p) __va(p)
433
434/*
435 * Convert a virtual cached pointer to an uncached pointer
436 */
437#define xlate_dev_kmem_ptr(p) p
438
439#include <asm-generic/io.h>
440
441/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 * can the hardware map this into one segment or not, given no other
443 * constraints.
444 */
445#define BIOVEC_MERGEABLE(vec1, vec2) \
446 ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
447
Stefano Stabelliniffc555b2013-11-06 12:38:28 +0000448struct bio_vec;
Stefano Stabellini3d1975b2013-10-25 10:33:26 +0000449extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
450 const struct bio_vec *vec2);
451#define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
452 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
453 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
454
Greg Ungerer95ba71f2007-05-17 06:22:41 +0100455#ifdef CONFIG_MMU
Lennert Buytenhek51635ad2006-09-16 10:50:22 +0100456#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
Cyril Chemparathy7e6735c2012-09-12 14:05:58 -0400457extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
Lennert Buytenhek51635ad2006-09-16 10:50:22 +0100458extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
Nicolas Pitre087aaff2010-09-22 18:34:36 -0400459extern int devmem_is_allowed(unsigned long pfn);
Greg Ungerer95ba71f2007-05-17 06:22:41 +0100460#endif
Lennert Buytenhek51635ad2006-09-16 10:50:22 +0100461
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462/*
Russell King1645f202006-08-28 12:45:16 +0100463 * Register ISA memory and port locations for glibc iopl/inb/outb
464 * emulation.
465 */
466extern void register_isa_ports(unsigned int mmio, unsigned int io,
467 unsigned int io_shift);
468
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469#endif /* __KERNEL__ */
470#endif /* __ASM_ARM_IO_H */