Fabio Estevam | 0eb6048 | 2018-05-01 09:20:40 -0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | // |
| 3 | // Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver |
| 4 | // |
| 5 | // Author: Timur Tabi <timur@freescale.com> |
| 6 | // |
| 7 | // Copyright 2007-2010 Freescale Semiconductor, Inc. |
| 8 | // |
| 9 | // Some notes why imx-pcm-fiq is used instead of DMA on some boards: |
| 10 | // |
| 11 | // The i.MX SSI core has some nasty limitations in AC97 mode. While most |
| 12 | // sane processor vendors have a FIFO per AC97 slot, the i.MX has only |
| 13 | // one FIFO which combines all valid receive slots. We cannot even select |
| 14 | // which slots we want to receive. The WM9712 with which this driver |
| 15 | // was developed with always sends GPIO status data in slot 12 which |
| 16 | // we receive in our (PCM-) data stream. The only chance we have is to |
| 17 | // manually skip this data in the FIQ handler. With sampling rates different |
| 18 | // from 48000Hz not every frame has valid receive data, so the ratio |
| 19 | // between pcm data and GPIO status data changes. Our FIQ handler is not |
| 20 | // able to handle this, hence this driver only works with 48000Hz sampling |
| 21 | // rate. |
| 22 | // Reading and writing AC97 registers is another challenge. The core |
| 23 | // provides us status bits when the read register is updated with *another* |
| 24 | // value. When we read the same register two times (and the register still |
| 25 | // contains the same value) these status bits are not set. We work |
| 26 | // around this by not polling these bits but only wait a fixed delay. |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 27 | |
| 28 | #include <linux/init.h> |
Shawn Guo | dfa1a107 | 2012-03-16 16:56:42 +0800 | [diff] [blame] | 29 | #include <linux/io.h> |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 30 | #include <linux/module.h> |
| 31 | #include <linux/interrupt.h> |
Shawn Guo | 95cd98f | 2012-03-29 10:53:41 +0800 | [diff] [blame] | 32 | #include <linux/clk.h> |
Fabio Estevam | c6682fe | 2017-04-05 16:44:06 -0300 | [diff] [blame] | 33 | #include <linux/ctype.h> |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 34 | #include <linux/device.h> |
| 35 | #include <linux/delay.h> |
Maciej S. Szmigiero | b880b80 | 2017-11-20 23:16:07 +0100 | [diff] [blame] | 36 | #include <linux/mutex.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 37 | #include <linux/slab.h> |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 38 | #include <linux/spinlock.h> |
Mark Brown | 9c72a04 | 2014-04-15 12:02:02 +0100 | [diff] [blame] | 39 | #include <linux/of.h> |
Shawn Guo | dfa1a107 | 2012-03-16 16:56:42 +0800 | [diff] [blame] | 40 | #include <linux/of_address.h> |
| 41 | #include <linux/of_irq.h> |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 42 | #include <linux/of_platform.h> |
Shengjiu Wang | 7aded70 | 2022-05-10 19:56:48 +0800 | [diff] [blame] | 43 | #include <linux/dma/imx-dma.h> |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 44 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 45 | #include <sound/core.h> |
| 46 | #include <sound/pcm.h> |
| 47 | #include <sound/pcm_params.h> |
| 48 | #include <sound/initval.h> |
| 49 | #include <sound/soc.h> |
Lars-Peter Clausen | a8909c9 | 2013-04-03 11:06:04 +0200 | [diff] [blame] | 50 | #include <sound/dmaengine_pcm.h> |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 51 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 52 | #include "fsl_ssi.h" |
Shawn Guo | 09ce111 | 2012-03-16 16:56:43 +0800 | [diff] [blame] | 53 | #include "imx-pcm.h" |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 54 | |
Nicolin Chen | 1476105 | 2018-02-12 14:03:09 -0800 | [diff] [blame] | 55 | /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */ |
| 56 | #define RX 0 |
| 57 | #define TX 1 |
| 58 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 59 | /** |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 60 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI |
| 61 | * |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 62 | * The SSI has a limitation in that the samples must be in the same byte |
| 63 | * order as the host CPU. This is because when multiple bytes are written |
| 64 | * to the STX register, the bytes and bits must be written in the same |
| 65 | * order. The STX is a shift register, so all the bits need to be aligned |
| 66 | * (bit-endianness must match byte-endianness). Processors typically write |
| 67 | * the bits within a byte in the same order that the bytes of a word are |
| 68 | * written in. So if the host CPU is big-endian, then only big-endian |
| 69 | * samples will be written to STX properly. |
| 70 | */ |
| 71 | #ifdef __BIG_ENDIAN |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 72 | #define FSLSSI_I2S_FORMATS \ |
| 73 | (SNDRV_PCM_FMTBIT_S8 | \ |
| 74 | SNDRV_PCM_FMTBIT_S16_BE | \ |
| 75 | SNDRV_PCM_FMTBIT_S18_3BE | \ |
| 76 | SNDRV_PCM_FMTBIT_S20_3BE | \ |
| 77 | SNDRV_PCM_FMTBIT_S24_3BE | \ |
| 78 | SNDRV_PCM_FMTBIT_S24_BE) |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 79 | #else |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 80 | #define FSLSSI_I2S_FORMATS \ |
| 81 | (SNDRV_PCM_FMTBIT_S8 | \ |
| 82 | SNDRV_PCM_FMTBIT_S16_LE | \ |
| 83 | SNDRV_PCM_FMTBIT_S18_3LE | \ |
| 84 | SNDRV_PCM_FMTBIT_S20_3LE | \ |
| 85 | SNDRV_PCM_FMTBIT_S24_3LE | \ |
| 86 | SNDRV_PCM_FMTBIT_S24_LE) |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 87 | #endif |
| 88 | |
Nicolin Chen | b6c93f7f | 2018-02-12 14:03:16 -0800 | [diff] [blame] | 89 | /* |
| 90 | * In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1: |
| 91 | * - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS |
| 92 | * - Also have NB_NF to mark these two clocks will not be inverted |
| 93 | */ |
| 94 | #define FSLSSI_AC97_DAIFMT \ |
| 95 | (SND_SOC_DAIFMT_AC97 | \ |
Charles Keepax | 3b14c15 | 2022-05-19 16:42:30 +0100 | [diff] [blame] | 96 | SND_SOC_DAIFMT_BC_FP | \ |
Nicolin Chen | b6c93f7f | 2018-02-12 14:03:16 -0800 | [diff] [blame] | 97 | SND_SOC_DAIFMT_NB_NF) |
| 98 | |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 99 | #define FSLSSI_SIER_DBG_RX_FLAGS \ |
| 100 | (SSI_SIER_RFF0_EN | \ |
| 101 | SSI_SIER_RLS_EN | \ |
| 102 | SSI_SIER_RFS_EN | \ |
| 103 | SSI_SIER_ROE0_EN | \ |
| 104 | SSI_SIER_RFRC_EN) |
| 105 | #define FSLSSI_SIER_DBG_TX_FLAGS \ |
| 106 | (SSI_SIER_TFE0_EN | \ |
| 107 | SSI_SIER_TLS_EN | \ |
| 108 | SSI_SIER_TFS_EN | \ |
| 109 | SSI_SIER_TUE0_EN | \ |
| 110 | SSI_SIER_TFRC_EN) |
Markus Pargmann | c1953bf | 2013-12-20 14:11:30 +0100 | [diff] [blame] | 111 | |
| 112 | enum fsl_ssi_type { |
| 113 | FSL_SSI_MCP8610, |
| 114 | FSL_SSI_MX21, |
Markus Pargmann | 0888efd | 2013-12-20 14:11:31 +0100 | [diff] [blame] | 115 | FSL_SSI_MX35, |
Markus Pargmann | c1953bf | 2013-12-20 14:11:30 +0100 | [diff] [blame] | 116 | FSL_SSI_MX51, |
| 117 | }; |
| 118 | |
Nicolin Chen | 2474e40 | 2017-12-17 18:52:08 -0800 | [diff] [blame] | 119 | struct fsl_ssi_regvals { |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 120 | u32 sier; |
| 121 | u32 srcr; |
| 122 | u32 stcr; |
| 123 | u32 scr; |
| 124 | }; |
| 125 | |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 126 | static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) |
| 127 | { |
| 128 | switch (reg) { |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 129 | case REG_SSI_SACCEN: |
| 130 | case REG_SSI_SACCDIS: |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 131 | return false; |
| 132 | default: |
| 133 | return true; |
| 134 | } |
| 135 | } |
| 136 | |
| 137 | static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) |
| 138 | { |
| 139 | switch (reg) { |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 140 | case REG_SSI_STX0: |
| 141 | case REG_SSI_STX1: |
| 142 | case REG_SSI_SRX0: |
| 143 | case REG_SSI_SRX1: |
| 144 | case REG_SSI_SISR: |
| 145 | case REG_SSI_SFCSR: |
| 146 | case REG_SSI_SACNT: |
| 147 | case REG_SSI_SACADD: |
| 148 | case REG_SSI_SACDAT: |
| 149 | case REG_SSI_SATAG: |
| 150 | case REG_SSI_SACCST: |
| 151 | case REG_SSI_SOR: |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 152 | return true; |
| 153 | default: |
| 154 | return false; |
| 155 | } |
| 156 | } |
| 157 | |
Maciej S. Szmigiero | f51e3d5 | 2015-12-20 21:31:48 +0100 | [diff] [blame] | 158 | static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) |
| 159 | { |
| 160 | switch (reg) { |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 161 | case REG_SSI_SRX0: |
| 162 | case REG_SSI_SRX1: |
| 163 | case REG_SSI_SISR: |
| 164 | case REG_SSI_SACADD: |
| 165 | case REG_SSI_SACDAT: |
| 166 | case REG_SSI_SATAG: |
Maciej S. Szmigiero | f51e3d5 | 2015-12-20 21:31:48 +0100 | [diff] [blame] | 167 | return true; |
| 168 | default: |
| 169 | return false; |
| 170 | } |
| 171 | } |
| 172 | |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 173 | static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) |
| 174 | { |
| 175 | switch (reg) { |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 176 | case REG_SSI_SRX0: |
| 177 | case REG_SSI_SRX1: |
| 178 | case REG_SSI_SACCST: |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 179 | return false; |
| 180 | default: |
| 181 | return true; |
| 182 | } |
| 183 | } |
| 184 | |
Markus Pargmann | 4324812 | 2014-05-27 10:24:25 +0200 | [diff] [blame] | 185 | static const struct regmap_config fsl_ssi_regconfig = { |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 186 | .max_register = REG_SSI_SACCDIS, |
Markus Pargmann | 4324812 | 2014-05-27 10:24:25 +0200 | [diff] [blame] | 187 | .reg_bits = 32, |
| 188 | .val_bits = 32, |
| 189 | .reg_stride = 4, |
| 190 | .val_format_endian = REGMAP_ENDIAN_NATIVE, |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 191 | .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1, |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 192 | .readable_reg = fsl_ssi_readable_reg, |
| 193 | .volatile_reg = fsl_ssi_volatile_reg, |
Maciej S. Szmigiero | f51e3d5 | 2015-12-20 21:31:48 +0100 | [diff] [blame] | 194 | .precious_reg = fsl_ssi_precious_reg, |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 195 | .writeable_reg = fsl_ssi_writeable_reg, |
Marek Vasut | bfcf928 | 2016-09-19 21:30:28 +0200 | [diff] [blame] | 196 | .cache_type = REGCACHE_FLAT, |
Markus Pargmann | 4324812 | 2014-05-27 10:24:25 +0200 | [diff] [blame] | 197 | }; |
Timur Tabi | d5a908b | 2009-03-26 11:42:38 -0500 | [diff] [blame] | 198 | |
Sascha Hauer | fcdbadef | 2014-05-27 10:24:18 +0200 | [diff] [blame] | 199 | struct fsl_ssi_soc_data { |
| 200 | bool imx; |
Maciej S. Szmigiero | 6139b1b | 2016-01-18 20:07:44 +0100 | [diff] [blame] | 201 | bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */ |
Sascha Hauer | fcdbadef | 2014-05-27 10:24:18 +0200 | [diff] [blame] | 202 | bool offline_config; |
| 203 | u32 sisr_write_mask; |
| 204 | }; |
| 205 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 206 | /** |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 207 | * struct fsl_ssi - per-SSI private data |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 208 | * @regs: Pointer to the regmap registers |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 209 | * @irq: IRQ of this SSI |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 210 | * @cpu_dai_drv: CPU DAI driver for this device |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 211 | * @dai_fmt: DAI configuration this device is currently used with |
Nicolin Chen | e0582731 | 2018-02-12 14:03:12 -0800 | [diff] [blame] | 212 | * @streams: Mask of current active streams: BIT(TX) and BIT(RX) |
Nicolin Chen | 8bc84a3 | 2017-12-17 18:52:09 -0800 | [diff] [blame] | 213 | * @i2s_net: I2S and Network mode configurations of SCR register |
Nicolin Chen | fac8a5a | 2018-04-07 21:40:21 -0700 | [diff] [blame] | 214 | * (this is the initial settings based on the DAI format) |
Nicolin Chen | badc959 | 2018-02-12 14:03:23 -0800 | [diff] [blame] | 215 | * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 216 | * @use_dma: DMA is used or FIQ with stream filter |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 217 | * @use_dual_fifo: DMA with support for dual FIFO mode |
Shengjiu Wang | 7aded70 | 2022-05-10 19:56:48 +0800 | [diff] [blame] | 218 | * @use_dyna_fifo: DMA with support for multi FIFO script |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 219 | * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree |
| 220 | * @fifo_depth: Depth of the SSI FIFOs |
| 221 | * @slot_width: Width of each DAI slot |
| 222 | * @slots: Number of slots |
Nicolin Chen | 2474e40 | 2017-12-17 18:52:08 -0800 | [diff] [blame] | 223 | * @regvals: Specific RX/TX register settings |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 224 | * @clk: Clock source to access register |
| 225 | * @baudclk: Clock source to generate bit and frame-sync clocks |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 226 | * @baudclk_streams: Active streams that are using baudclk |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 227 | * @regcache_sfcsr: Cache sfcsr register value during suspend and resume |
| 228 | * @regcache_sacnt: Cache sacnt register value during suspend and resume |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 229 | * @dma_params_tx: DMA transmit parameters |
| 230 | * @dma_params_rx: DMA receive parameters |
| 231 | * @ssi_phys: physical address of the SSI registers |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 232 | * @fiq_params: FIQ stream filtering parameters |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 233 | * @card_pdev: Platform_device pointer to register a sound card for PowerPC or |
| 234 | * to register a CODEC platform device for AC97 |
| 235 | * @card_name: Platform_device name to register a sound card for PowerPC or |
| 236 | * to register a CODEC platform device for AC97 |
| 237 | * @card_idx: The index of SSI to register a sound card for PowerPC or |
| 238 | * to register a CODEC platform device for AC97 |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 239 | * @dbg_stats: Debugging statistics |
Xiubo Li | dcfcf2c | 2015-08-12 14:38:18 +0800 | [diff] [blame] | 240 | * @soc: SoC specific data |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 241 | * @dev: Pointer to &pdev->dev |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 242 | * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are |
| 243 | * @fifo_watermark or fewer words in TX fifo or |
| 244 | * @fifo_watermark or more empty words in RX fifo. |
| 245 | * @dma_maxburst: Max number of words to transfer in one go. So far, |
| 246 | * this is always the same as fifo_watermark. |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 247 | * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations |
Shengjiu Wang | 7aded70 | 2022-05-10 19:56:48 +0800 | [diff] [blame] | 248 | * @audio_config: configure for dma multi fifo script |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 249 | */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 250 | struct fsl_ssi { |
Markus Pargmann | 4324812 | 2014-05-27 10:24:25 +0200 | [diff] [blame] | 251 | struct regmap *regs; |
Fabio Estevam | 9e446ad | 2015-01-14 10:48:59 -0200 | [diff] [blame] | 252 | int irq; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 253 | struct snd_soc_dai_driver cpu_dai_drv; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 254 | |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 255 | unsigned int dai_fmt; |
Nicolin Chen | e0582731 | 2018-02-12 14:03:12 -0800 | [diff] [blame] | 256 | u8 streams; |
Nicolin Chen | 8bc84a3 | 2017-12-17 18:52:09 -0800 | [diff] [blame] | 257 | u8 i2s_net; |
Nicolin Chen | badc959 | 2018-02-12 14:03:23 -0800 | [diff] [blame] | 258 | bool synchronous; |
Markus Pargmann | de623ec | 2013-07-27 13:31:53 +0200 | [diff] [blame] | 259 | bool use_dma; |
Nicolin Chen | 0da9e55 | 2013-11-13 22:55:26 +0800 | [diff] [blame] | 260 | bool use_dual_fifo; |
Shengjiu Wang | 7aded70 | 2022-05-10 19:56:48 +0800 | [diff] [blame] | 261 | bool use_dyna_fifo; |
Shengjiu Wang | f4a43ca | 2014-09-16 10:13:16 +0800 | [diff] [blame] | 262 | bool has_ipg_clk_name; |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 263 | unsigned int fifo_depth; |
Nicolin Chen | b0a7043 | 2017-09-13 20:07:09 -0700 | [diff] [blame] | 264 | unsigned int slot_width; |
| 265 | unsigned int slots; |
Nicolin Chen | 2474e40 | 2017-12-17 18:52:08 -0800 | [diff] [blame] | 266 | struct fsl_ssi_regvals regvals[2]; |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 267 | |
Shawn Guo | 95cd98f | 2012-03-29 10:53:41 +0800 | [diff] [blame] | 268 | struct clk *clk; |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 269 | struct clk *baudclk; |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 270 | unsigned int baudclk_streams; |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 271 | |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 272 | u32 regcache_sfcsr; |
Maciej S. Szmigiero | 3f1c241 | 2015-12-20 21:30:25 +0100 | [diff] [blame] | 273 | u32 regcache_sacnt; |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 274 | |
Lars-Peter Clausen | a8909c9 | 2013-04-03 11:06:04 +0200 | [diff] [blame] | 275 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
| 276 | struct snd_dmaengine_dai_dma_data dma_params_rx; |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 277 | dma_addr_t ssi_phys; |
| 278 | |
Markus Pargmann | de623ec | 2013-07-27 13:31:53 +0200 | [diff] [blame] | 279 | struct imx_pcm_fiq_params fiq_params; |
Markus Pargmann | 737a6b4 | 2014-05-27 10:24:24 +0200 | [diff] [blame] | 280 | |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 281 | struct platform_device *card_pdev; |
| 282 | char card_name[32]; |
| 283 | u32 card_idx; |
Shawn Guo | 09ce111 | 2012-03-16 16:56:43 +0800 | [diff] [blame] | 284 | |
Markus Pargmann | f138e62 | 2014-04-28 12:54:43 +0200 | [diff] [blame] | 285 | struct fsl_ssi_dbg dbg_stats; |
Sascha Hauer | fcdbadef | 2014-05-27 10:24:18 +0200 | [diff] [blame] | 286 | |
| 287 | const struct fsl_ssi_soc_data *soc; |
Arnaud Mouiche | 0096b69 | 2016-05-03 14:13:57 +0200 | [diff] [blame] | 288 | struct device *dev; |
Caleb Crome | 4ee437f | 2017-01-03 10:22:57 -0800 | [diff] [blame] | 289 | |
| 290 | u32 fifo_watermark; |
| 291 | u32 dma_maxburst; |
Maciej S. Szmigiero | b880b80 | 2017-11-20 23:16:07 +0100 | [diff] [blame] | 292 | |
| 293 | struct mutex ac97_reg_lock; |
Shengjiu Wang | 7aded70 | 2022-05-10 19:56:48 +0800 | [diff] [blame] | 294 | struct sdma_peripheral_config audio_config[2]; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 295 | }; |
| 296 | |
Markus Pargmann | 171d683 | 2014-04-28 12:54:48 +0200 | [diff] [blame] | 297 | /* |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 298 | * SoC specific data |
Markus Pargmann | 171d683 | 2014-04-28 12:54:48 +0200 | [diff] [blame] | 299 | * |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 300 | * Notes: |
| 301 | * 1) SSI in earlier SoCS has critical bits in control registers that |
| 302 | * cannot be changed after SSI starts running -- a software reset |
| 303 | * (set SSIEN to 0) is required to change their values. So adding |
| 304 | * an offline_config flag for these SoCs. |
| 305 | * 2) SDMA is available since imx35. However, imx35 does not support |
| 306 | * DMA bits changing when SSI is running, so set offline_config. |
| 307 | * 3) imx51 and later versions support register configurations when |
| 308 | * SSI is running (SSIEN); For these versions, DMA needs to be |
| 309 | * configured before SSI sends DMA request to avoid an undefined |
| 310 | * DMA request on the SDMA side. |
Markus Pargmann | 171d683 | 2014-04-28 12:54:48 +0200 | [diff] [blame] | 311 | */ |
Markus Pargmann | 171d683 | 2014-04-28 12:54:48 +0200 | [diff] [blame] | 312 | |
Sascha Hauer | fcdbadef | 2014-05-27 10:24:18 +0200 | [diff] [blame] | 313 | static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { |
| 314 | .imx = false, |
| 315 | .offline_config = true, |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 316 | .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 317 | SSI_SISR_ROE0 | SSI_SISR_ROE1 | |
| 318 | SSI_SISR_TUE0 | SSI_SISR_TUE1, |
Sascha Hauer | fcdbadef | 2014-05-27 10:24:18 +0200 | [diff] [blame] | 319 | }; |
| 320 | |
| 321 | static struct fsl_ssi_soc_data fsl_ssi_imx21 = { |
| 322 | .imx = true, |
Maciej S. Szmigiero | 6139b1b | 2016-01-18 20:07:44 +0100 | [diff] [blame] | 323 | .imx21regs = true, |
Sascha Hauer | fcdbadef | 2014-05-27 10:24:18 +0200 | [diff] [blame] | 324 | .offline_config = true, |
| 325 | .sisr_write_mask = 0, |
| 326 | }; |
| 327 | |
| 328 | static struct fsl_ssi_soc_data fsl_ssi_imx35 = { |
| 329 | .imx = true, |
| 330 | .offline_config = true, |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 331 | .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 332 | SSI_SISR_ROE0 | SSI_SISR_ROE1 | |
| 333 | SSI_SISR_TUE0 | SSI_SISR_TUE1, |
Sascha Hauer | fcdbadef | 2014-05-27 10:24:18 +0200 | [diff] [blame] | 334 | }; |
| 335 | |
| 336 | static struct fsl_ssi_soc_data fsl_ssi_imx51 = { |
| 337 | .imx = true, |
| 338 | .offline_config = false, |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 339 | .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 | |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 340 | SSI_SISR_TUE0 | SSI_SISR_TUE1, |
Sascha Hauer | fcdbadef | 2014-05-27 10:24:18 +0200 | [diff] [blame] | 341 | }; |
| 342 | |
| 343 | static const struct of_device_id fsl_ssi_ids[] = { |
| 344 | { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, |
| 345 | { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, |
| 346 | { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, |
| 347 | { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, |
| 348 | {} |
| 349 | }; |
| 350 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); |
| 351 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 352 | static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi) |
Sascha Hauer | fcdbadef | 2014-05-27 10:24:18 +0200 | [diff] [blame] | 353 | { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 354 | return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == |
Adam Thomson | 5b64c17 | 2015-09-16 10:13:19 +0100 | [diff] [blame] | 355 | SND_SOC_DAIFMT_AC97; |
Markus Pargmann | 171d683 | 2014-04-28 12:54:48 +0200 | [diff] [blame] | 356 | } |
| 357 | |
Mark Brown | 89efbda | 2021-09-21 22:35:33 +0100 | [diff] [blame] | 358 | static bool fsl_ssi_is_i2s_clock_provider(struct fsl_ssi *ssi) |
Sascha Hauer | 8dd51e2 | 2014-05-27 10:24:20 +0200 | [diff] [blame] | 359 | { |
Mark Brown | 89efbda | 2021-09-21 22:35:33 +0100 | [diff] [blame] | 360 | return (ssi->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) == |
Charles Keepax | 3b14c15 | 2022-05-19 16:42:30 +0100 | [diff] [blame] | 361 | SND_SOC_DAIFMT_BP_FP; |
Sascha Hauer | 8dd51e2 | 2014-05-27 10:24:20 +0200 | [diff] [blame] | 362 | } |
| 363 | |
Charles Keepax | 3b14c15 | 2022-05-19 16:42:30 +0100 | [diff] [blame] | 364 | static bool fsl_ssi_is_i2s_bc_fp(struct fsl_ssi *ssi) |
Fabio Falzoi | cf4f7fc | 2014-08-04 17:08:07 +0200 | [diff] [blame] | 365 | { |
Mark Brown | 89efbda | 2021-09-21 22:35:33 +0100 | [diff] [blame] | 366 | return (ssi->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) == |
Charles Keepax | 3b14c15 | 2022-05-19 16:42:30 +0100 | [diff] [blame] | 367 | SND_SOC_DAIFMT_BC_FP; |
Fabio Falzoi | cf4f7fc | 2014-08-04 17:08:07 +0200 | [diff] [blame] | 368 | } |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 369 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 370 | /** |
Pierre-Louis Bossart | 6a9287f | 2021-03-02 14:59:23 -0600 | [diff] [blame] | 371 | * fsl_ssi_isr - Interrupt handler to gather states |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 372 | * @irq: irq number |
| 373 | * @dev_id: context |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 374 | */ |
| 375 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) |
| 376 | { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 377 | struct fsl_ssi *ssi = dev_id; |
| 378 | struct regmap *regs = ssi->regs; |
Fabio Estevam | 671f820 | 2018-04-25 19:53:52 -0300 | [diff] [blame] | 379 | u32 sisr, sisr2; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 380 | |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 381 | regmap_read(regs, REG_SSI_SISR, &sisr); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 382 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 383 | sisr2 = sisr & ssi->soc->sisr_write_mask; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 384 | /* Clear the bits that we set */ |
| 385 | if (sisr2) |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 386 | regmap_write(regs, REG_SSI_SISR, sisr2); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 387 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 388 | fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr); |
Markus Pargmann | f138e62 | 2014-04-28 12:54:43 +0200 | [diff] [blame] | 389 | |
| 390 | return IRQ_HANDLED; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 391 | } |
| 392 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 393 | /** |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 394 | * fsl_ssi_config_enable - Set SCR, SIER, STCR and SRCR registers with |
| 395 | * cached values in regvals |
| 396 | * @ssi: SSI context |
| 397 | * @tx: direction |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 398 | * |
| 399 | * Notes: |
| 400 | * 1) For offline_config SoCs, enable all necessary bits of both streams |
| 401 | * when 1st stream starts, even if the opposite stream will not start |
| 402 | * 2) It also clears FIFO before setting regvals; SOR is safe to set online |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 403 | */ |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 404 | static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx) |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 405 | { |
Nicolin Chen | 2474e40 | 2017-12-17 18:52:08 -0800 | [diff] [blame] | 406 | struct fsl_ssi_regvals *vals = ssi->regvals; |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 407 | int dir = tx ? TX : RX; |
| 408 | u32 sier, srcr, stcr; |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 409 | |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 410 | /* Clear dirty data in the FIFO; It also prevents channel slipping */ |
| 411 | regmap_update_bits(ssi->regs, REG_SSI_SOR, |
| 412 | SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx)); |
| 413 | |
| 414 | /* |
| 415 | * On offline_config SoCs, SxCR and SIER are already configured when |
| 416 | * the previous stream started. So skip all SxCR and SIER settings |
| 417 | * to prevent online reconfigurations, then jump to set SCR directly |
| 418 | */ |
| 419 | if (ssi->soc->offline_config && ssi->streams) |
| 420 | goto enable_scr; |
| 421 | |
| 422 | if (ssi->soc->offline_config) { |
| 423 | /* |
| 424 | * Online reconfiguration not supported, so enable all bits for |
| 425 | * both streams at once to avoid necessity of reconfigurations |
| 426 | */ |
| 427 | srcr = vals[RX].srcr | vals[TX].srcr; |
| 428 | stcr = vals[RX].stcr | vals[TX].stcr; |
| 429 | sier = vals[RX].sier | vals[TX].sier; |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 430 | } else { |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 431 | /* Otherwise, only set bits for the current stream */ |
| 432 | srcr = vals[dir].srcr; |
| 433 | stcr = vals[dir].stcr; |
| 434 | sier = vals[dir].sier; |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 435 | } |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 436 | |
| 437 | /* Configure SRCR, STCR and SIER at once */ |
| 438 | regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr); |
| 439 | regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr); |
| 440 | regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier); |
| 441 | |
| 442 | enable_scr: |
| 443 | /* |
| 444 | * Start DMA before setting TE to avoid FIFO underrun |
| 445 | * which may cause a channel slip or a channel swap |
| 446 | * |
| 447 | * TODO: FIQ cases might also need this upon testing |
| 448 | */ |
| 449 | if (ssi->use_dma && tx) { |
| 450 | int try = 100; |
| 451 | u32 sfcsr; |
| 452 | |
| 453 | /* Enable SSI first to send TX DMA request */ |
| 454 | regmap_update_bits(ssi->regs, REG_SSI_SCR, |
| 455 | SSI_SCR_SSIEN, SSI_SCR_SSIEN); |
| 456 | |
| 457 | /* Busy wait until TX FIFO not empty -- DMA working */ |
| 458 | do { |
| 459 | regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr); |
| 460 | if (SSI_SFCSR_TFCNT0(sfcsr)) |
| 461 | break; |
| 462 | } while (--try); |
| 463 | |
| 464 | /* FIFO still empty -- something might be wrong */ |
| 465 | if (!SSI_SFCSR_TFCNT0(sfcsr)) |
| 466 | dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n"); |
| 467 | } |
| 468 | /* Enable all remaining bits in SCR */ |
| 469 | regmap_update_bits(ssi->regs, REG_SSI_SCR, |
| 470 | vals[dir].scr, vals[dir].scr); |
| 471 | |
| 472 | /* Log the enabled stream to the mask */ |
| 473 | ssi->streams |= BIT(dir); |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 474 | } |
| 475 | |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 476 | /* |
Nicolin Chen | 06a9945 | 2018-02-12 14:03:13 -0800 | [diff] [blame] | 477 | * Exclude bits that are used by the opposite stream |
Markus Pargmann | 65c961c | 2014-04-28 12:54:42 +0200 | [diff] [blame] | 478 | * |
Nicolin Chen | 06a9945 | 2018-02-12 14:03:13 -0800 | [diff] [blame] | 479 | * When both streams are active, disabling some bits for the current stream |
| 480 | * might break the other stream if these bits are used by it. |
Markus Pargmann | 65c961c | 2014-04-28 12:54:42 +0200 | [diff] [blame] | 481 | * |
Nicolin Chen | 06a9945 | 2018-02-12 14:03:13 -0800 | [diff] [blame] | 482 | * @vals : regvals of the current stream |
| 483 | * @avals: regvals of the opposite stream |
| 484 | * @aactive: active state of the opposite stream |
Markus Pargmann | 65c961c | 2014-04-28 12:54:42 +0200 | [diff] [blame] | 485 | * |
Nicolin Chen | 06a9945 | 2018-02-12 14:03:13 -0800 | [diff] [blame] | 486 | * 1) XOR vals and avals to get the differences if the other stream is active; |
| 487 | * Otherwise, return current vals if the other stream is not active |
| 488 | * 2) AND the result of 1) with the current vals |
Markus Pargmann | 65c961c | 2014-04-28 12:54:42 +0200 | [diff] [blame] | 489 | */ |
Nicolin Chen | 06a9945 | 2018-02-12 14:03:13 -0800 | [diff] [blame] | 490 | #define _ssi_xor_shared_bits(vals, avals, aactive) \ |
| 491 | ((vals) ^ ((avals) * (aactive))) |
| 492 | |
| 493 | #define ssi_excl_shared_bits(vals, avals, aactive) \ |
| 494 | ((vals) & _ssi_xor_shared_bits(vals, avals, aactive)) |
Markus Pargmann | 65c961c | 2014-04-28 12:54:42 +0200 | [diff] [blame] | 495 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 496 | /** |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 497 | * fsl_ssi_config_disable - Unset SCR, SIER, STCR and SRCR registers |
| 498 | * with cached values in regvals |
| 499 | * @ssi: SSI context |
| 500 | * @tx: direction |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 501 | * |
| 502 | * Notes: |
| 503 | * 1) For offline_config SoCs, to avoid online reconfigurations, disable all |
| 504 | * bits of both streams at once when the last stream is abort to end |
| 505 | * 2) It also clears FIFO after unsetting regvals; SOR is safe to set online |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 506 | */ |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 507 | static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx) |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 508 | { |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 509 | struct fsl_ssi_regvals *vals, *avals; |
| 510 | u32 sier, srcr, stcr, scr; |
Nicolin Chen | 2e13274 | 2018-02-12 14:03:14 -0800 | [diff] [blame] | 511 | int adir = tx ? RX : TX; |
| 512 | int dir = tx ? TX : RX; |
Nicolin Chen | 06a9945 | 2018-02-12 14:03:13 -0800 | [diff] [blame] | 513 | bool aactive; |
Markus Pargmann | 65c961c | 2014-04-28 12:54:42 +0200 | [diff] [blame] | 514 | |
Nicolin Chen | 06a9945 | 2018-02-12 14:03:13 -0800 | [diff] [blame] | 515 | /* Check if the opposite stream is active */ |
| 516 | aactive = ssi->streams & BIT(adir); |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 517 | |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 518 | vals = &ssi->regvals[dir]; |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 519 | |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 520 | /* Get regvals of the opposite stream to keep opposite stream safe */ |
| 521 | avals = &ssi->regvals[adir]; |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 522 | |
| 523 | /* |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 524 | * To keep the other stream safe, exclude shared bits between |
| 525 | * both streams, and get safe bits to disable current stream |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 526 | */ |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 527 | scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive); |
| 528 | |
| 529 | /* Disable safe bits of SCR register for the current stream */ |
| 530 | regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0); |
| 531 | |
| 532 | /* Log the disabled stream to the mask */ |
| 533 | ssi->streams &= ~BIT(dir); |
| 534 | |
| 535 | /* |
| 536 | * On offline_config SoCs, if the other stream is active, skip |
| 537 | * SxCR and SIER settings to prevent online reconfigurations |
| 538 | */ |
| 539 | if (ssi->soc->offline_config && aactive) |
| 540 | goto fifo_clear; |
| 541 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 542 | if (ssi->soc->offline_config) { |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 543 | /* Now there is only current stream active, disable all bits */ |
| 544 | srcr = vals->srcr | avals->srcr; |
| 545 | stcr = vals->stcr | avals->stcr; |
| 546 | sier = vals->sier | avals->sier; |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 547 | } else { |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 548 | /* |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 549 | * To keep the other stream safe, exclude shared bits between |
| 550 | * both streams, and get safe bits to disable current stream |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 551 | */ |
Nicolin Chen | 06a9945 | 2018-02-12 14:03:13 -0800 | [diff] [blame] | 552 | sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive); |
| 553 | srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive); |
| 554 | stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive); |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 555 | } |
| 556 | |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 557 | /* Clear configurations of SRCR, STCR and SIER at once */ |
| 558 | regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0); |
| 559 | regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0); |
| 560 | regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0); |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 561 | |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 562 | fifo_clear: |
| 563 | /* Clear remaining data in the FIFO */ |
| 564 | regmap_update_bits(ssi->regs, REG_SSI_SOR, |
| 565 | SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx)); |
Markus Pargmann | 4e6ec0d | 2013-12-20 14:11:33 +0100 | [diff] [blame] | 566 | } |
| 567 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 568 | static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi) |
Maciej S. Szmigiero | 01ca485 | 2017-11-22 00:54:26 +0100 | [diff] [blame] | 569 | { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 570 | struct regmap *regs = ssi->regs; |
Maciej S. Szmigiero | 01ca485 | 2017-11-22 00:54:26 +0100 | [diff] [blame] | 571 | |
| 572 | /* no SACC{ST,EN,DIS} regs on imx21-class SSI */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 573 | if (!ssi->soc->imx21regs) { |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 574 | /* Disable all channel slots */ |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 575 | regmap_write(regs, REG_SSI_SACCDIS, 0xff); |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 576 | /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */ |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 577 | regmap_write(regs, REG_SSI_SACCEN, 0x300); |
Maciej S. Szmigiero | 01ca485 | 2017-11-22 00:54:26 +0100 | [diff] [blame] | 578 | } |
| 579 | } |
| 580 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 581 | /** |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 582 | * fsl_ssi_setup_regvals - Cache critical bits of SIER, SRCR, STCR and |
| 583 | * SCR to later set them safely |
| 584 | * @ssi: SSI context |
Markus Pargmann | 6de8387 | 2013-12-20 14:11:34 +0100 | [diff] [blame] | 585 | */ |
Nicolin Chen | 2474e40 | 2017-12-17 18:52:08 -0800 | [diff] [blame] | 586 | static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi) |
Markus Pargmann | 6de8387 | 2013-12-20 14:11:34 +0100 | [diff] [blame] | 587 | { |
Nicolin Chen | 2474e40 | 2017-12-17 18:52:08 -0800 | [diff] [blame] | 588 | struct fsl_ssi_regvals *vals = ssi->regvals; |
Markus Pargmann | 6de8387 | 2013-12-20 14:11:34 +0100 | [diff] [blame] | 589 | |
Nicolin Chen | 501bc1d | 2018-02-12 14:03:17 -0800 | [diff] [blame] | 590 | vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS; |
Nicolin Chen | 2474e40 | 2017-12-17 18:52:08 -0800 | [diff] [blame] | 591 | vals[RX].srcr = SSI_SRCR_RFEN0; |
Nicolin Chen | 501bc1d | 2018-02-12 14:03:17 -0800 | [diff] [blame] | 592 | vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE; |
| 593 | vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS; |
Nicolin Chen | 2474e40 | 2017-12-17 18:52:08 -0800 | [diff] [blame] | 594 | vals[TX].stcr = SSI_STCR_TFEN0; |
Nicolin Chen | 501bc1d | 2018-02-12 14:03:17 -0800 | [diff] [blame] | 595 | vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE; |
Markus Pargmann | 6de8387 | 2013-12-20 14:11:34 +0100 | [diff] [blame] | 596 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 597 | /* AC97 has already enabled SSIEN, RE and TE, so ignore them */ |
Nicolin Chen | 501bc1d | 2018-02-12 14:03:17 -0800 | [diff] [blame] | 598 | if (fsl_ssi_is_ac97(ssi)) |
| 599 | vals[RX].scr = vals[TX].scr = 0; |
Markus Pargmann | 6de8387 | 2013-12-20 14:11:34 +0100 | [diff] [blame] | 600 | |
Nicolin Chen | 702d7965 | 2018-02-12 14:03:18 -0800 | [diff] [blame] | 601 | if (ssi->use_dual_fifo) { |
| 602 | vals[RX].srcr |= SSI_SRCR_RFEN1; |
| 603 | vals[TX].stcr |= SSI_STCR_TFEN1; |
| 604 | } |
| 605 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 606 | if (ssi->use_dma) { |
Nicolin Chen | 2474e40 | 2017-12-17 18:52:08 -0800 | [diff] [blame] | 607 | vals[RX].sier |= SSI_SIER_RDMAE; |
| 608 | vals[TX].sier |= SSI_SIER_TDMAE; |
Markus Pargmann | 6de8387 | 2013-12-20 14:11:34 +0100 | [diff] [blame] | 609 | } else { |
Nicolin Chen | 2474e40 | 2017-12-17 18:52:08 -0800 | [diff] [blame] | 610 | vals[RX].sier |= SSI_SIER_RIE; |
| 611 | vals[TX].sier |= SSI_SIER_TIE; |
Markus Pargmann | 6de8387 | 2013-12-20 14:11:34 +0100 | [diff] [blame] | 612 | } |
Markus Pargmann | 6de8387 | 2013-12-20 14:11:34 +0100 | [diff] [blame] | 613 | } |
| 614 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 615 | static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi) |
Markus Pargmann | d876464 | 2013-11-20 10:04:15 +0100 | [diff] [blame] | 616 | { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 617 | struct regmap *regs = ssi->regs; |
Markus Pargmann | d876464 | 2013-11-20 10:04:15 +0100 | [diff] [blame] | 618 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 619 | /* Setup the clock control register */ |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 620 | regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); |
| 621 | regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); |
Markus Pargmann | d876464 | 2013-11-20 10:04:15 +0100 | [diff] [blame] | 622 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 623 | /* Enable AC97 mode and startup the SSI */ |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 624 | regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV); |
Maciej S. Szmigiero | 6139b1b | 2016-01-18 20:07:44 +0100 | [diff] [blame] | 625 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 626 | /* AC97 has to communicate with codec before starting a stream */ |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 627 | regmap_update_bits(regs, REG_SSI_SCR, |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 628 | SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE, |
| 629 | SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE); |
Markus Pargmann | d876464 | 2013-11-20 10:04:15 +0100 | [diff] [blame] | 630 | |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 631 | regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3)); |
Markus Pargmann | d876464 | 2013-11-20 10:04:15 +0100 | [diff] [blame] | 632 | } |
| 633 | |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 634 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
| 635 | struct snd_soc_dai *dai) |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 636 | { |
Kuninori Morimoto | 9f5f078 | 2020-07-20 10:18:38 +0900 | [diff] [blame] | 637 | struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); |
Kuninori Morimoto | 17198ae | 2020-03-23 14:18:30 +0900 | [diff] [blame] | 638 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); |
Shengjiu Wang | f4a43ca | 2014-09-16 10:13:16 +0800 | [diff] [blame] | 639 | int ret; |
| 640 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 641 | ret = clk_prepare_enable(ssi->clk); |
Shengjiu Wang | f4a43ca | 2014-09-16 10:13:16 +0800 | [diff] [blame] | 642 | if (ret) |
| 643 | return ret; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 644 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 645 | /* |
| 646 | * When using dual fifo mode, it is safer to ensure an even period |
Nicolin Chen | 0da9e55 | 2013-11-13 22:55:26 +0800 | [diff] [blame] | 647 | * size. If appearing to an odd number while DMA always starts its |
| 648 | * task from fifo0, fifo1 would be neglected at the end of each |
| 649 | * period. But SSI would still access fifo1 with an invalid data. |
| 650 | */ |
Shengjiu Wang | 7aded70 | 2022-05-10 19:56:48 +0800 | [diff] [blame] | 651 | if (ssi->use_dual_fifo || ssi->use_dyna_fifo) |
Nicolin Chen | 0da9e55 | 2013-11-13 22:55:26 +0800 | [diff] [blame] | 652 | snd_pcm_hw_constraint_step(substream->runtime, 0, |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 653 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); |
Nicolin Chen | 0da9e55 | 2013-11-13 22:55:26 +0800 | [diff] [blame] | 654 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 655 | return 0; |
| 656 | } |
| 657 | |
Shengjiu Wang | f4a43ca | 2014-09-16 10:13:16 +0800 | [diff] [blame] | 658 | static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 659 | struct snd_soc_dai *dai) |
Shengjiu Wang | f4a43ca | 2014-09-16 10:13:16 +0800 | [diff] [blame] | 660 | { |
Kuninori Morimoto | 9f5f078 | 2020-07-20 10:18:38 +0900 | [diff] [blame] | 661 | struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); |
Kuninori Morimoto | 17198ae | 2020-03-23 14:18:30 +0900 | [diff] [blame] | 662 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); |
Shengjiu Wang | f4a43ca | 2014-09-16 10:13:16 +0800 | [diff] [blame] | 663 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 664 | clk_disable_unprepare(ssi->clk); |
Shengjiu Wang | f4a43ca | 2014-09-16 10:13:16 +0800 | [diff] [blame] | 665 | } |
| 666 | |
| 667 | /** |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 668 | * fsl_ssi_set_bclk - Configure Digital Audio Interface bit clock |
| 669 | * @substream: ASoC substream |
| 670 | * @dai: pointer to DAI |
| 671 | * @hw_params: pointers to hw_params |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 672 | * |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 673 | * Notes: This function can be only called when using SSI as DAI master |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 674 | * |
| 675 | * Quick instruction for parameters: |
Nicolin Chen | b0a7043 | 2017-09-13 20:07:09 -0700 | [diff] [blame] | 676 | * freq: Output BCLK frequency = samplerate * slots * slot_width |
| 677 | * (In 2-channel I2S Master mode, slot_width is fixed 32) |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 678 | */ |
Sascha Hauer | 8dd51e2 | 2014-05-27 10:24:20 +0200 | [diff] [blame] | 679 | static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 680 | struct snd_soc_dai *dai, |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 681 | struct snd_pcm_hw_params *hw_params) |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 682 | { |
Nicolin Chen | 52eee84 | 2017-12-17 18:52:10 -0800 | [diff] [blame] | 683 | bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 684 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 685 | struct regmap *regs = ssi->regs; |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 686 | u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; |
Sascha Hauer | d8ced47 | 2014-05-27 10:24:21 +0200 | [diff] [blame] | 687 | unsigned long clkrate, baudrate, tmprate; |
Shengjiu Wang | ed1220d | 2020-06-16 10:53:48 +0800 | [diff] [blame] | 688 | unsigned int channels = params_channels(hw_params); |
| 689 | unsigned int slot_width = params_width(hw_params); |
| 690 | unsigned int slots = 2; |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 691 | u64 sub, savesub = 100000; |
Sascha Hauer | 8dd51e2 | 2014-05-27 10:24:20 +0200 | [diff] [blame] | 692 | unsigned int freq; |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 693 | bool baudclk_is_used; |
Nicolin Chen | badc959 | 2018-02-12 14:03:23 -0800 | [diff] [blame] | 694 | int ret; |
Sascha Hauer | 8dd51e2 | 2014-05-27 10:24:20 +0200 | [diff] [blame] | 695 | |
Nicolin Chen | b0a7043 | 2017-09-13 20:07:09 -0700 | [diff] [blame] | 696 | /* Override slots and slot_width if being specifically set... */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 697 | if (ssi->slots) |
| 698 | slots = ssi->slots; |
Shengjiu Wang | ed1220d | 2020-06-16 10:53:48 +0800 | [diff] [blame] | 699 | if (ssi->slot_width) |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 700 | slot_width = ssi->slot_width; |
Nicolin Chen | b0a7043 | 2017-09-13 20:07:09 -0700 | [diff] [blame] | 701 | |
Shengjiu Wang | ed1220d | 2020-06-16 10:53:48 +0800 | [diff] [blame] | 702 | /* ...but force 32 bits for stereo audio using I2S Master Mode */ |
| 703 | if (channels == 2 && |
| 704 | (ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER) |
| 705 | slot_width = 32; |
| 706 | |
Nicolin Chen | b0a7043 | 2017-09-13 20:07:09 -0700 | [diff] [blame] | 707 | /* Generate bit clock based on the slot number and slot width */ |
| 708 | freq = slots * slot_width * params_rate(hw_params); |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 709 | |
| 710 | /* Don't apply it to any non-baudclk circumstance */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 711 | if (IS_ERR(ssi->baudclk)) |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 712 | return -EINVAL; |
| 713 | |
Arnaud Mouiche | e09745f | 2016-05-03 14:13:56 +0200 | [diff] [blame] | 714 | /* |
| 715 | * Hardware limitation: The bclk rate must be |
| 716 | * never greater than 1/5 IPG clock rate |
| 717 | */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 718 | if (freq * 5 > clk_get_rate(ssi->clk)) { |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 719 | dev_err(dai->dev, "bitclk > ipgclk / 5\n"); |
Arnaud Mouiche | e09745f | 2016-05-03 14:13:56 +0200 | [diff] [blame] | 720 | return -EINVAL; |
| 721 | } |
| 722 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 723 | baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream)); |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 724 | |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 725 | /* It should be already enough to divide clock by setting pm alone */ |
| 726 | psr = 0; |
| 727 | div2 = 0; |
| 728 | |
| 729 | factor = (div2 + 1) * (7 * psr + 1) * 2; |
| 730 | |
| 731 | for (i = 0; i < 255; i++) { |
Nicolin Chen | 6c8ca30 | 2015-03-04 21:05:04 -0800 | [diff] [blame] | 732 | tmprate = freq * factor * (i + 1); |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 733 | |
| 734 | if (baudclk_is_used) |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 735 | clkrate = clk_get_rate(ssi->baudclk); |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 736 | else |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 737 | clkrate = clk_round_rate(ssi->baudclk, tmprate); |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 738 | |
Timur Tabi | acf2c60 | 2014-06-13 07:42:40 -0500 | [diff] [blame] | 739 | clkrate /= factor; |
| 740 | afreq = clkrate / (i + 1); |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 741 | |
| 742 | if (freq == afreq) |
| 743 | sub = 0; |
| 744 | else if (freq / afreq == 1) |
| 745 | sub = freq - afreq; |
| 746 | else if (afreq / freq == 1) |
| 747 | sub = afreq - freq; |
| 748 | else |
| 749 | continue; |
| 750 | |
| 751 | /* Calculate the fraction */ |
| 752 | sub *= 100000; |
| 753 | do_div(sub, freq); |
| 754 | |
Pierre-Louis Bossart | 2fb5635 | 2021-02-19 17:29:33 -0600 | [diff] [blame] | 755 | if (sub < savesub && !(i == 0)) { |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 756 | baudrate = tmprate; |
| 757 | savesub = sub; |
| 758 | pm = i; |
| 759 | } |
| 760 | |
| 761 | /* We are lucky */ |
| 762 | if (savesub == 0) |
| 763 | break; |
| 764 | } |
| 765 | |
| 766 | /* No proper pm found if it is still remaining the initial value */ |
| 767 | if (pm == 999) { |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 768 | dev_err(dai->dev, "failed to handle the required sysclk\n"); |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 769 | return -EINVAL; |
| 770 | } |
| 771 | |
Pierre-Louis Bossart | 2fb5635 | 2021-02-19 17:29:33 -0600 | [diff] [blame] | 772 | stccr = SSI_SxCCR_PM(pm + 1); |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 773 | mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR; |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 774 | |
Nicolin Chen | 52eee84 | 2017-12-17 18:52:10 -0800 | [diff] [blame] | 775 | /* STCCR is used for RX in synchronous mode */ |
Nicolin Chen | badc959 | 2018-02-12 14:03:23 -0800 | [diff] [blame] | 776 | tx2 = tx || ssi->synchronous; |
Nicolin Chen | 52eee84 | 2017-12-17 18:52:10 -0800 | [diff] [blame] | 777 | regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr); |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 778 | |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 779 | if (!baudclk_is_used) { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 780 | ret = clk_set_rate(ssi->baudclk, baudrate); |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 781 | if (ret) { |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 782 | dev_err(dai->dev, "failed to set baudclk rate\n"); |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 783 | return -EINVAL; |
| 784 | } |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 785 | } |
Sascha Hauer | ee9daad | 2014-04-28 12:54:52 +0200 | [diff] [blame] | 786 | |
| 787 | return 0; |
| 788 | } |
| 789 | |
| 790 | /** |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 791 | * fsl_ssi_hw_params - Configure SSI based on PCM hardware parameters |
| 792 | * @substream: ASoC substream |
| 793 | * @hw_params: pointers to hw_params |
| 794 | * @dai: pointer to DAI |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 795 | * |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 796 | * Notes: |
| 797 | * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily |
| 798 | * disabled on offline_config SoCs. Even for online configurable SoCs |
| 799 | * running in synchronous mode (both TX and RX use STCCR), it is not |
| 800 | * safe to re-configure them when both two streams start running. |
| 801 | * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the |
| 802 | * fsl_ssi_set_bclk() if SSI is the DAI clock master. |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 803 | */ |
Timur Tabi | 85ef237 | 2009-02-05 17:56:02 -0600 | [diff] [blame] | 804 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 805 | struct snd_pcm_hw_params *hw_params, |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 806 | struct snd_soc_dai *dai) |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 807 | { |
Nicolin Chen | 52eee84 | 2017-12-17 18:52:10 -0800 | [diff] [blame] | 808 | bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 809 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
Shengjiu Wang | 7aded70 | 2022-05-10 19:56:48 +0800 | [diff] [blame] | 810 | struct fsl_ssi_regvals *vals = ssi->regvals; |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 811 | struct regmap *regs = ssi->regs; |
Nicolin Chen | 2924a99 | 2013-12-02 23:29:03 +0800 | [diff] [blame] | 812 | unsigned int channels = params_channels(hw_params); |
Zidan Wang | 4ca7304 | 2015-11-24 15:32:09 +0800 | [diff] [blame] | 813 | unsigned int sample_size = params_width(hw_params); |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 814 | u32 wl = SSI_SxCCR_WL(sample_size); |
Sascha Hauer | 8dd51e2 | 2014-05-27 10:24:20 +0200 | [diff] [blame] | 815 | int ret; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 816 | |
Mark Brown | 89efbda | 2021-09-21 22:35:33 +0100 | [diff] [blame] | 817 | if (fsl_ssi_is_i2s_clock_provider(ssi)) { |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 818 | ret = fsl_ssi_set_bclk(substream, dai, hw_params); |
Sascha Hauer | 8dd51e2 | 2014-05-27 10:24:20 +0200 | [diff] [blame] | 819 | if (ret) |
| 820 | return ret; |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 821 | |
| 822 | /* Do not enable the clock if it is already enabled */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 823 | if (!(ssi->baudclk_streams & BIT(substream->stream))) { |
| 824 | ret = clk_prepare_enable(ssi->baudclk); |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 825 | if (ret) |
| 826 | return ret; |
| 827 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 828 | ssi->baudclk_streams |= BIT(substream->stream); |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 829 | } |
Sascha Hauer | 8dd51e2 | 2014-05-27 10:24:20 +0200 | [diff] [blame] | 830 | } |
| 831 | |
Shengjiu Wang | 696d052 | 2019-08-28 13:20:17 -0400 | [diff] [blame] | 832 | /* |
| 833 | * SSI is properly configured if it is enabled and running in |
| 834 | * the synchronous mode; Note that AC97 mode is an exception |
| 835 | * that should set separate configurations for STCCR and SRCCR |
| 836 | * despite running in the synchronous mode. |
| 837 | */ |
| 838 | if (ssi->streams && ssi->synchronous) |
| 839 | return 0; |
| 840 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 841 | if (!fsl_ssi_is_ac97(ssi)) { |
Nicolin Chen | fac8a5a | 2018-04-07 21:40:21 -0700 | [diff] [blame] | 842 | /* |
| 843 | * Keep the ssi->i2s_net intact while having a local variable |
| 844 | * to override settings for special use cases. Otherwise, the |
| 845 | * ssi->i2s_net will lose the settings for regular use cases. |
| 846 | */ |
| 847 | u8 i2s_net = ssi->i2s_net; |
| 848 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 849 | /* Normal + Network mode to send 16-bit data in 32-bit frames */ |
Charles Keepax | 3b14c15 | 2022-05-19 16:42:30 +0100 | [diff] [blame] | 850 | if (fsl_ssi_is_i2s_bc_fp(ssi) && sample_size == 16) |
Nicolin Chen | fac8a5a | 2018-04-07 21:40:21 -0700 | [diff] [blame] | 851 | i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET; |
Nicolin Chen | ebf08ae | 2018-02-12 14:03:10 -0800 | [diff] [blame] | 852 | |
| 853 | /* Use Normal mode to send mono data at 1st slot of 2 slots */ |
| 854 | if (channels == 1) |
Nicolin Chen | fac8a5a | 2018-04-07 21:40:21 -0700 | [diff] [blame] | 855 | i2s_net = SSI_SCR_I2S_MODE_NORMAL; |
Fabio Falzoi | cf4f7fc | 2014-08-04 17:08:07 +0200 | [diff] [blame] | 856 | |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 857 | regmap_update_bits(regs, REG_SSI_SCR, |
Nicolin Chen | fac8a5a | 2018-04-07 21:40:21 -0700 | [diff] [blame] | 858 | SSI_SCR_I2S_NET_MASK, i2s_net); |
Fabio Falzoi | cf4f7fc | 2014-08-04 17:08:07 +0200 | [diff] [blame] | 859 | } |
| 860 | |
Timur Tabi | 5e538ec | 2011-09-13 12:59:37 -0500 | [diff] [blame] | 861 | /* In synchronous mode, the SSI uses STCCR for capture */ |
Nicolin Chen | badc959 | 2018-02-12 14:03:23 -0800 | [diff] [blame] | 862 | tx2 = tx || ssi->synchronous; |
Nicolin Chen | 52eee84 | 2017-12-17 18:52:10 -0800 | [diff] [blame] | 863 | regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 864 | |
Shengjiu Wang | 7aded70 | 2022-05-10 19:56:48 +0800 | [diff] [blame] | 865 | if (ssi->use_dyna_fifo) { |
| 866 | if (channels == 1) { |
| 867 | ssi->audio_config[0].n_fifos_dst = 1; |
| 868 | ssi->audio_config[1].n_fifos_src = 1; |
| 869 | vals[RX].srcr &= ~SSI_SRCR_RFEN1; |
| 870 | vals[TX].stcr &= ~SSI_STCR_TFEN1; |
| 871 | vals[RX].scr &= ~SSI_SCR_TCH_EN; |
| 872 | vals[TX].scr &= ~SSI_SCR_TCH_EN; |
| 873 | } else { |
| 874 | ssi->audio_config[0].n_fifos_dst = 2; |
| 875 | ssi->audio_config[1].n_fifos_src = 2; |
| 876 | vals[RX].srcr |= SSI_SRCR_RFEN1; |
| 877 | vals[TX].stcr |= SSI_STCR_TFEN1; |
| 878 | vals[RX].scr |= SSI_SCR_TCH_EN; |
| 879 | vals[TX].scr |= SSI_SCR_TCH_EN; |
| 880 | } |
| 881 | ssi->dma_params_tx.peripheral_config = &ssi->audio_config[0]; |
| 882 | ssi->dma_params_tx.peripheral_size = sizeof(ssi->audio_config[0]); |
| 883 | ssi->dma_params_rx.peripheral_config = &ssi->audio_config[1]; |
| 884 | ssi->dma_params_rx.peripheral_size = sizeof(ssi->audio_config[1]); |
| 885 | } |
| 886 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 887 | return 0; |
| 888 | } |
| 889 | |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 890 | static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 891 | struct snd_soc_dai *dai) |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 892 | { |
Kuninori Morimoto | 9f5f078 | 2020-07-20 10:18:38 +0900 | [diff] [blame] | 893 | struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); |
Kuninori Morimoto | 17198ae | 2020-03-23 14:18:30 +0900 | [diff] [blame] | 894 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 895 | |
Mark Brown | 89efbda | 2021-09-21 22:35:33 +0100 | [diff] [blame] | 896 | if (fsl_ssi_is_i2s_clock_provider(ssi) && |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 897 | ssi->baudclk_streams & BIT(substream->stream)) { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 898 | clk_disable_unprepare(ssi->baudclk); |
| 899 | ssi->baudclk_streams &= ~BIT(substream->stream); |
Markus Pargmann | d429d8e | 2014-05-27 10:24:23 +0200 | [diff] [blame] | 900 | } |
| 901 | |
| 902 | return 0; |
| 903 | } |
| 904 | |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 905 | static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt) |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 906 | { |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 907 | u32 strcr = 0, scr = 0, stcr, srcr, mask; |
Alexander Shiyan | 8726396 | 2021-02-16 14:42:21 +0300 | [diff] [blame] | 908 | unsigned int slots; |
Markus Pargmann | 2b0db99 | 2014-03-15 13:44:09 +0100 | [diff] [blame] | 909 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 910 | ssi->dai_fmt = fmt; |
Markus Pargmann | 171d683 | 2014-04-28 12:54:48 +0200 | [diff] [blame] | 911 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 912 | /* Synchronize frame sync clock for TE to avoid data slipping */ |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 913 | scr |= SSI_SCR_SYNC_TX_FS; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 914 | |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 915 | /* Set to default shifting settings: LSB_ALIGNED */ |
| 916 | strcr |= SSI_STCR_TXBIT0; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 917 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 918 | /* Use Network mode as default */ |
Nicolin Chen | 8bc84a3 | 2017-12-17 18:52:09 -0800 | [diff] [blame] | 919 | ssi->i2s_net = SSI_SCR_NET; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 920 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 921 | case SND_SOC_DAIFMT_I2S: |
Mark Brown | 89efbda | 2021-09-21 22:35:33 +0100 | [diff] [blame] | 922 | switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
Charles Keepax | 3b14c15 | 2022-05-19 16:42:30 +0100 | [diff] [blame] | 923 | case SND_SOC_DAIFMT_BP_FP: |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 924 | if (IS_ERR(ssi->baudclk)) { |
| 925 | dev_err(ssi->dev, |
| 926 | "missing baudclk for master mode\n"); |
| 927 | return -EINVAL; |
| 928 | } |
Gustavo A. R. Silva | df561f66 | 2020-08-23 17:36:59 -0500 | [diff] [blame] | 929 | fallthrough; |
Charles Keepax | 3b14c15 | 2022-05-19 16:42:30 +0100 | [diff] [blame] | 930 | case SND_SOC_DAIFMT_BC_FP: |
Nicolin Chen | 8bc84a3 | 2017-12-17 18:52:09 -0800 | [diff] [blame] | 931 | ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 932 | break; |
Charles Keepax | 3b14c15 | 2022-05-19 16:42:30 +0100 | [diff] [blame] | 933 | case SND_SOC_DAIFMT_BC_FC: |
Nicolin Chen | 8bc84a3 | 2017-12-17 18:52:09 -0800 | [diff] [blame] | 934 | ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 935 | break; |
| 936 | default: |
| 937 | return -EINVAL; |
| 938 | } |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 939 | |
Alexander Shiyan | 8726396 | 2021-02-16 14:42:21 +0300 | [diff] [blame] | 940 | slots = ssi->slots ? : 2; |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 941 | regmap_update_bits(ssi->regs, REG_SSI_STCCR, |
Alexander Shiyan | 8726396 | 2021-02-16 14:42:21 +0300 | [diff] [blame] | 942 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 943 | regmap_update_bits(ssi->regs, REG_SSI_SRCCR, |
Alexander Shiyan | 8726396 | 2021-02-16 14:42:21 +0300 | [diff] [blame] | 944 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 945 | |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 946 | /* Data on rising edge of bclk, frame low, 1clk before data */ |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 947 | strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 948 | break; |
| 949 | case SND_SOC_DAIFMT_LEFT_J: |
| 950 | /* Data on rising edge of bclk, frame high */ |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 951 | strcr |= SSI_STCR_TSCKP; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 952 | break; |
| 953 | case SND_SOC_DAIFMT_DSP_A: |
| 954 | /* Data on rising edge of bclk, frame high, 1clk before data */ |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 955 | strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 956 | break; |
| 957 | case SND_SOC_DAIFMT_DSP_B: |
| 958 | /* Data on rising edge of bclk, frame high */ |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 959 | strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 960 | break; |
Markus Pargmann | 2b0db99 | 2014-03-15 13:44:09 +0100 | [diff] [blame] | 961 | case SND_SOC_DAIFMT_AC97: |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 962 | /* Data on falling edge of bclk, frame high, 1clk before data */ |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 963 | strcr |= SSI_STCR_TEFS; |
Markus Pargmann | 2b0db99 | 2014-03-15 13:44:09 +0100 | [diff] [blame] | 964 | break; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 965 | default: |
| 966 | return -EINVAL; |
| 967 | } |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 968 | |
Nicolin Chen | 8bc84a3 | 2017-12-17 18:52:09 -0800 | [diff] [blame] | 969 | scr |= ssi->i2s_net; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 970 | |
| 971 | /* DAI clock inversion */ |
| 972 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 973 | case SND_SOC_DAIFMT_NB_NF: |
| 974 | /* Nothing to do for both normal cases */ |
| 975 | break; |
| 976 | case SND_SOC_DAIFMT_IB_NF: |
| 977 | /* Invert bit clock */ |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 978 | strcr ^= SSI_STCR_TSCKP; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 979 | break; |
| 980 | case SND_SOC_DAIFMT_NB_IF: |
| 981 | /* Invert frame clock */ |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 982 | strcr ^= SSI_STCR_TFSI; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 983 | break; |
| 984 | case SND_SOC_DAIFMT_IB_IF: |
| 985 | /* Invert both clocks */ |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 986 | strcr ^= SSI_STCR_TSCKP; |
| 987 | strcr ^= SSI_STCR_TFSI; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 988 | break; |
| 989 | default: |
| 990 | return -EINVAL; |
| 991 | } |
| 992 | |
Mark Brown | 89efbda | 2021-09-21 22:35:33 +0100 | [diff] [blame] | 993 | /* DAI clock provider masks */ |
| 994 | switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
Charles Keepax | 3b14c15 | 2022-05-19 16:42:30 +0100 | [diff] [blame] | 995 | case SND_SOC_DAIFMT_BP_FP: |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 996 | /* Output bit and frame sync clocks */ |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 997 | strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR; |
| 998 | scr |= SSI_SCR_SYS_CLK_EN; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 999 | break; |
Charles Keepax | 3b14c15 | 2022-05-19 16:42:30 +0100 | [diff] [blame] | 1000 | case SND_SOC_DAIFMT_BC_FC: |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1001 | /* Input bit or frame sync clocks */ |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1002 | break; |
Charles Keepax | 3b14c15 | 2022-05-19 16:42:30 +0100 | [diff] [blame] | 1003 | case SND_SOC_DAIFMT_BC_FP: |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1004 | /* Input bit clock but output frame sync clock */ |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1005 | strcr |= SSI_STCR_TFDIR; |
Fabio Falzoi | cf4f7fc | 2014-08-04 17:08:07 +0200 | [diff] [blame] | 1006 | break; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1007 | default: |
Nicolin Chen | b6c93f7f | 2018-02-12 14:03:16 -0800 | [diff] [blame] | 1008 | return -EINVAL; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1009 | } |
| 1010 | |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 1011 | stcr = strcr; |
| 1012 | srcr = strcr; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1013 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1014 | /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */ |
Nicolin Chen | badc959 | 2018-02-12 14:03:23 -0800 | [diff] [blame] | 1015 | if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) { |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1016 | srcr &= ~SSI_SRCR_RXDIR; |
| 1017 | scr |= SSI_SCR_SYN; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1018 | } |
| 1019 | |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 1020 | mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP | |
| 1021 | SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0; |
| 1022 | |
| 1023 | regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr); |
| 1024 | regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr); |
| 1025 | |
| 1026 | mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK | |
| 1027 | SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN; |
| 1028 | regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr); |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1029 | |
| 1030 | return 0; |
Markus Pargmann | 85e59af | 2014-05-27 10:24:19 +0200 | [diff] [blame] | 1031 | } |
| 1032 | |
| 1033 | /** |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 1034 | * fsl_ssi_set_dai_fmt - Configure Digital Audio Interface (DAI) Format |
| 1035 | * @dai: pointer to DAI |
| 1036 | * @fmt: format mask |
Markus Pargmann | 85e59af | 2014-05-27 10:24:19 +0200 | [diff] [blame] | 1037 | */ |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 1038 | static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
Markus Pargmann | 85e59af | 2014-05-27 10:24:19 +0200 | [diff] [blame] | 1039 | { |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 1040 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
Markus Pargmann | 85e59af | 2014-05-27 10:24:19 +0200 | [diff] [blame] | 1041 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1042 | /* AC97 configured DAIFMT earlier in the probe() */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1043 | if (fsl_ssi_is_ac97(ssi)) |
Maciej S. Szmigiero | c997a92 | 2017-11-22 00:55:14 +0100 | [diff] [blame] | 1044 | return 0; |
| 1045 | |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 1046 | return _fsl_ssi_set_dai_fmt(ssi, fmt); |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1047 | } |
| 1048 | |
| 1049 | /** |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 1050 | * fsl_ssi_set_dai_tdm_slot - Set TDM slot number and slot width |
| 1051 | * @dai: pointer to DAI |
| 1052 | * @tx_mask: mask for TX |
| 1053 | * @rx_mask: mask for RX |
| 1054 | * @slots: number of slots |
| 1055 | * @slot_width: number of bits per slot |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1056 | */ |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 1057 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1058 | u32 rx_mask, int slots, int slot_width) |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1059 | { |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 1060 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1061 | struct regmap *regs = ssi->regs; |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1062 | u32 val; |
| 1063 | |
Nicolin Chen | b0a7043 | 2017-09-13 20:07:09 -0700 | [diff] [blame] | 1064 | /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */ |
| 1065 | if (slot_width & 1 || slot_width < 8 || slot_width > 24) { |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 1066 | dev_err(dai->dev, "invalid slot width: %d\n", slot_width); |
Nicolin Chen | b0a7043 | 2017-09-13 20:07:09 -0700 | [diff] [blame] | 1067 | return -EINVAL; |
| 1068 | } |
| 1069 | |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1070 | /* The slot number should be >= 2 if using Network mode or I2S mode */ |
Nicolin Chen | 0994763 | 2018-02-12 14:03:11 -0800 | [diff] [blame] | 1071 | if (ssi->i2s_net && slots < 2) { |
Nicolin Chen | 0c884be | 2017-12-17 18:52:06 -0800 | [diff] [blame] | 1072 | dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n"); |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1073 | return -EINVAL; |
| 1074 | } |
| 1075 | |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1076 | regmap_update_bits(regs, REG_SSI_STCCR, |
| 1077 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); |
| 1078 | regmap_update_bits(regs, REG_SSI_SRCCR, |
| 1079 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1080 | |
Nicolin Chen | 0994763 | 2018-02-12 14:03:11 -0800 | [diff] [blame] | 1081 | /* Save the SCR register value */ |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1082 | regmap_read(regs, REG_SSI_SCR, &val); |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1083 | /* Temporarily enable SSI to allow SxMSKs to be configurable */ |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1084 | regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN); |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1085 | |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1086 | regmap_write(regs, REG_SSI_STMSK, ~tx_mask); |
| 1087 | regmap_write(regs, REG_SSI_SRMSK, ~rx_mask); |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1088 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1089 | /* Restore the value of SSIEN bit */ |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1090 | regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val); |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1091 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1092 | ssi->slot_width = slot_width; |
| 1093 | ssi->slots = slots; |
Nicolin Chen | b0a7043 | 2017-09-13 20:07:09 -0700 | [diff] [blame] | 1094 | |
Nicolin Chen | aafa85e | 2013-12-12 18:44:45 +0800 | [diff] [blame] | 1095 | return 0; |
| 1096 | } |
| 1097 | |
| 1098 | /** |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 1099 | * fsl_ssi_trigger - Start or stop SSI and corresponding DMA transaction. |
| 1100 | * @substream: ASoC substream |
| 1101 | * @cmd: trigger command |
| 1102 | * @dai: pointer to DAI |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1103 | * |
| 1104 | * The DMA channel is in external master start and pause mode, which |
| 1105 | * means the SSI completely controls the flow of data. |
| 1106 | */ |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 1107 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
| 1108 | struct snd_soc_dai *dai) |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1109 | { |
Kuninori Morimoto | 9f5f078 | 2020-07-20 10:18:38 +0900 | [diff] [blame] | 1110 | struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); |
Kuninori Morimoto | 17198ae | 2020-03-23 14:18:30 +0900 | [diff] [blame] | 1111 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 1112 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
Michael Grzeschik | 9b443e3 | 2013-08-19 17:06:00 +0200 | [diff] [blame] | 1113 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1114 | switch (cmd) { |
| 1115 | case SNDRV_PCM_TRIGGER_START: |
Fabio Estevam | b20e53a | 2014-05-23 02:38:56 -0300 | [diff] [blame] | 1116 | case SNDRV_PCM_TRIGGER_RESUME: |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1117 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 1118 | /* |
| 1119 | * SACCST might be modified via AC Link by a CODEC if it sends |
| 1120 | * extra bits in their SLOTREQ requests, which'll accidentally |
| 1121 | * send valid data to slots other than normal playback slots. |
| 1122 | * |
| 1123 | * To be safe, configure SACCST right before TX starts. |
| 1124 | */ |
| 1125 | if (tx && fsl_ssi_is_ac97(ssi)) |
| 1126 | fsl_ssi_tx_ac97_saccst_setup(ssi); |
| 1127 | fsl_ssi_config_enable(ssi, tx); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1128 | break; |
| 1129 | |
| 1130 | case SNDRV_PCM_TRIGGER_STOP: |
Fabio Estevam | b20e53a | 2014-05-23 02:38:56 -0300 | [diff] [blame] | 1131 | case SNDRV_PCM_TRIGGER_SUSPEND: |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1132 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
Nicolin Chen | 7d67bcb | 2018-02-12 14:03:15 -0800 | [diff] [blame] | 1133 | fsl_ssi_config_disable(ssi, tx); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1134 | break; |
| 1135 | |
| 1136 | default: |
| 1137 | return -EINVAL; |
| 1138 | } |
| 1139 | |
| 1140 | return 0; |
| 1141 | } |
| 1142 | |
Lars-Peter Clausen | fc8ba7f | 2013-04-15 19:19:58 +0200 | [diff] [blame] | 1143 | static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) |
| 1144 | { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1145 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
Lars-Peter Clausen | fc8ba7f | 2013-04-15 19:19:58 +0200 | [diff] [blame] | 1146 | |
Nicolin Chen | 40f2563 | 2018-02-12 14:03:19 -0800 | [diff] [blame] | 1147 | if (ssi->soc->imx && ssi->use_dma) |
| 1148 | snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx, |
| 1149 | &ssi->dma_params_rx); |
Lars-Peter Clausen | fc8ba7f | 2013-04-15 19:19:58 +0200 | [diff] [blame] | 1150 | |
| 1151 | return 0; |
| 1152 | } |
| 1153 | |
Lars-Peter Clausen | 85e7652 | 2011-11-23 11:40:40 +0100 | [diff] [blame] | 1154 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1155 | .startup = fsl_ssi_startup, |
| 1156 | .shutdown = fsl_ssi_shutdown, |
| 1157 | .hw_params = fsl_ssi_hw_params, |
| 1158 | .hw_free = fsl_ssi_hw_free, |
Charles Keepax | 0077827 | 2022-05-19 16:42:57 +0100 | [diff] [blame] | 1159 | .set_fmt = fsl_ssi_set_dai_fmt, |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1160 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, |
| 1161 | .trigger = fsl_ssi_trigger, |
Eric Miao | 6335d05 | 2009-03-03 09:41:00 +0800 | [diff] [blame] | 1162 | }; |
| 1163 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1164 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { |
Lars-Peter Clausen | fc8ba7f | 2013-04-15 19:19:58 +0200 | [diff] [blame] | 1165 | .probe = fsl_ssi_dai_probe, |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1166 | .playback = { |
Nicolin Chen | e365500 | 2014-07-30 11:10:29 +0800 | [diff] [blame] | 1167 | .stream_name = "CPU-Playback", |
Nicolin Chen | 2924a99 | 2013-12-02 23:29:03 +0800 | [diff] [blame] | 1168 | .channels_min = 1, |
Arnaud Mouiche | 48a260e | 2016-05-03 14:13:55 +0200 | [diff] [blame] | 1169 | .channels_max = 32, |
Fabio Estevam | 5805567 | 2017-04-05 16:44:05 -0300 | [diff] [blame] | 1170 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1171 | .formats = FSLSSI_I2S_FORMATS, |
| 1172 | }, |
| 1173 | .capture = { |
Nicolin Chen | e365500 | 2014-07-30 11:10:29 +0800 | [diff] [blame] | 1174 | .stream_name = "CPU-Capture", |
Nicolin Chen | 2924a99 | 2013-12-02 23:29:03 +0800 | [diff] [blame] | 1175 | .channels_min = 1, |
Arnaud Mouiche | 48a260e | 2016-05-03 14:13:55 +0200 | [diff] [blame] | 1176 | .channels_max = 32, |
Fabio Estevam | 5805567 | 2017-04-05 16:44:05 -0300 | [diff] [blame] | 1177 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1178 | .formats = FSLSSI_I2S_FORMATS, |
| 1179 | }, |
Eric Miao | 6335d05 | 2009-03-03 09:41:00 +0800 | [diff] [blame] | 1180 | .ops = &fsl_ssi_dai_ops, |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1181 | }; |
| 1182 | |
Kuninori Morimoto | 3580aa1 | 2013-03-21 03:32:04 -0700 | [diff] [blame] | 1183 | static const struct snd_soc_component_driver fsl_ssi_component = { |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1184 | .name = "fsl-ssi", |
Charles Keepax | 1e63fcc | 2022-06-23 13:51:34 +0100 | [diff] [blame] | 1185 | .legacy_dai_naming = 1, |
Kuninori Morimoto | 3580aa1 | 2013-03-21 03:32:04 -0700 | [diff] [blame] | 1186 | }; |
| 1187 | |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1188 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1189 | .symmetric_channels = 1, |
Maciej S. Szmigiero | 793e3e9 | 2015-08-05 17:22:53 +0200 | [diff] [blame] | 1190 | .probe = fsl_ssi_dai_probe, |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1191 | .playback = { |
Mark Brown | 8c6a42b | 2023-01-06 23:15:06 +0000 | [diff] [blame] | 1192 | .stream_name = "CPU AC97 Playback", |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1193 | .channels_min = 2, |
| 1194 | .channels_max = 2, |
| 1195 | .rates = SNDRV_PCM_RATE_8000_48000, |
Maciej S. Szmigiero | 1058263 | 2017-11-27 23:34:44 +0100 | [diff] [blame] | 1196 | .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20, |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1197 | }, |
| 1198 | .capture = { |
Mark Brown | 8c6a42b | 2023-01-06 23:15:06 +0000 | [diff] [blame] | 1199 | .stream_name = "CPU AC97 Capture", |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1200 | .channels_min = 2, |
| 1201 | .channels_max = 2, |
| 1202 | .rates = SNDRV_PCM_RATE_48000, |
Maciej S. Szmigiero | 1058263 | 2017-11-27 23:34:44 +0100 | [diff] [blame] | 1203 | /* 16-bit capture is broken (errata ERR003778) */ |
| 1204 | .formats = SNDRV_PCM_FMTBIT_S20, |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1205 | }, |
Markus Pargmann | a5a7ee7 | 2013-12-20 14:11:35 +0100 | [diff] [blame] | 1206 | .ops = &fsl_ssi_dai_ops, |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1207 | }; |
| 1208 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1209 | static struct fsl_ssi *fsl_ac97_data; |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1210 | |
Sachin Kamat | a851a2b | 2013-09-13 15:22:17 +0530 | [diff] [blame] | 1211 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1212 | unsigned short val) |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1213 | { |
Markus Pargmann | 4324812 | 2014-05-27 10:24:25 +0200 | [diff] [blame] | 1214 | struct regmap *regs = fsl_ac97_data->regs; |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1215 | unsigned int lreg; |
| 1216 | unsigned int lval; |
Maciej S. Szmigiero | 8277df3 | 2015-08-05 17:21:35 +0200 | [diff] [blame] | 1217 | int ret; |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1218 | |
| 1219 | if (reg > 0x7f) |
| 1220 | return; |
| 1221 | |
Maciej S. Szmigiero | b880b80 | 2017-11-20 23:16:07 +0100 | [diff] [blame] | 1222 | mutex_lock(&fsl_ac97_data->ac97_reg_lock); |
| 1223 | |
Maciej S. Szmigiero | 8277df3 | 2015-08-05 17:21:35 +0200 | [diff] [blame] | 1224 | ret = clk_prepare_enable(fsl_ac97_data->clk); |
| 1225 | if (ret) { |
| 1226 | pr_err("ac97 write clk_prepare_enable failed: %d\n", |
| 1227 | ret); |
Maciej S. Szmigiero | b880b80 | 2017-11-20 23:16:07 +0100 | [diff] [blame] | 1228 | goto ret_unlock; |
Maciej S. Szmigiero | 8277df3 | 2015-08-05 17:21:35 +0200 | [diff] [blame] | 1229 | } |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1230 | |
| 1231 | lreg = reg << 12; |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1232 | regmap_write(regs, REG_SSI_SACADD, lreg); |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1233 | |
| 1234 | lval = val << 4; |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1235 | regmap_write(regs, REG_SSI_SACDAT, lval); |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1236 | |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1237 | regmap_update_bits(regs, REG_SSI_SACNT, |
| 1238 | SSI_SACNT_RDWR_MASK, SSI_SACNT_WR); |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1239 | udelay(100); |
Maciej S. Szmigiero | 8277df3 | 2015-08-05 17:21:35 +0200 | [diff] [blame] | 1240 | |
| 1241 | clk_disable_unprepare(fsl_ac97_data->clk); |
Maciej S. Szmigiero | b880b80 | 2017-11-20 23:16:07 +0100 | [diff] [blame] | 1242 | |
| 1243 | ret_unlock: |
| 1244 | mutex_unlock(&fsl_ac97_data->ac97_reg_lock); |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1245 | } |
| 1246 | |
Sachin Kamat | a851a2b | 2013-09-13 15:22:17 +0530 | [diff] [blame] | 1247 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1248 | unsigned short reg) |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1249 | { |
Markus Pargmann | 4324812 | 2014-05-27 10:24:25 +0200 | [diff] [blame] | 1250 | struct regmap *regs = fsl_ac97_data->regs; |
Maciej S. Szmigiero | b880b80 | 2017-11-20 23:16:07 +0100 | [diff] [blame] | 1251 | unsigned short val = 0; |
Markus Pargmann | 4324812 | 2014-05-27 10:24:25 +0200 | [diff] [blame] | 1252 | u32 reg_val; |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1253 | unsigned int lreg; |
Maciej S. Szmigiero | 8277df3 | 2015-08-05 17:21:35 +0200 | [diff] [blame] | 1254 | int ret; |
| 1255 | |
Maciej S. Szmigiero | b880b80 | 2017-11-20 23:16:07 +0100 | [diff] [blame] | 1256 | mutex_lock(&fsl_ac97_data->ac97_reg_lock); |
| 1257 | |
Maciej S. Szmigiero | 8277df3 | 2015-08-05 17:21:35 +0200 | [diff] [blame] | 1258 | ret = clk_prepare_enable(fsl_ac97_data->clk); |
| 1259 | if (ret) { |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1260 | pr_err("ac97 read clk_prepare_enable failed: %d\n", ret); |
Maciej S. Szmigiero | b880b80 | 2017-11-20 23:16:07 +0100 | [diff] [blame] | 1261 | goto ret_unlock; |
Maciej S. Szmigiero | 8277df3 | 2015-08-05 17:21:35 +0200 | [diff] [blame] | 1262 | } |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1263 | |
| 1264 | lreg = (reg & 0x7f) << 12; |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1265 | regmap_write(regs, REG_SSI_SACADD, lreg); |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1266 | regmap_update_bits(regs, REG_SSI_SACNT, |
| 1267 | SSI_SACNT_RDWR_MASK, SSI_SACNT_RD); |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1268 | |
| 1269 | udelay(100); |
| 1270 | |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1271 | regmap_read(regs, REG_SSI_SACDAT, ®_val); |
Markus Pargmann | 4324812 | 2014-05-27 10:24:25 +0200 | [diff] [blame] | 1272 | val = (reg_val >> 4) & 0xffff; |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1273 | |
Maciej S. Szmigiero | 8277df3 | 2015-08-05 17:21:35 +0200 | [diff] [blame] | 1274 | clk_disable_unprepare(fsl_ac97_data->clk); |
| 1275 | |
Maciej S. Szmigiero | b880b80 | 2017-11-20 23:16:07 +0100 | [diff] [blame] | 1276 | ret_unlock: |
| 1277 | mutex_unlock(&fsl_ac97_data->ac97_reg_lock); |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1278 | return val; |
| 1279 | } |
| 1280 | |
| 1281 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1282 | .read = fsl_ssi_ac97_read, |
| 1283 | .write = fsl_ssi_ac97_write, |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1284 | }; |
| 1285 | |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1286 | /** |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 1287 | * fsl_ssi_hw_init - Initialize SSI registers |
| 1288 | * @ssi: SSI context |
Nicolin Chen | a1d154a | 2018-02-12 14:03:20 -0800 | [diff] [blame] | 1289 | */ |
| 1290 | static int fsl_ssi_hw_init(struct fsl_ssi *ssi) |
| 1291 | { |
| 1292 | u32 wm = ssi->fifo_watermark; |
| 1293 | |
| 1294 | /* Initialize regvals */ |
| 1295 | fsl_ssi_setup_regvals(ssi); |
| 1296 | |
| 1297 | /* Set watermarks */ |
| 1298 | regmap_write(ssi->regs, REG_SSI_SFCSR, |
| 1299 | SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) | |
| 1300 | SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm)); |
| 1301 | |
| 1302 | /* Enable Dual FIFO mode */ |
| 1303 | if (ssi->use_dual_fifo) |
| 1304 | regmap_update_bits(ssi->regs, REG_SSI_SCR, |
| 1305 | SSI_SCR_TCH_EN, SSI_SCR_TCH_EN); |
| 1306 | |
Nicolin Chen | 37ac30a | 2018-02-12 14:03:21 -0800 | [diff] [blame] | 1307 | /* AC97 should start earlier to communicate with CODECs */ |
| 1308 | if (fsl_ssi_is_ac97(ssi)) { |
Nicolin Chen | 26b31f4f | 2018-02-12 14:03:22 -0800 | [diff] [blame] | 1309 | _fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt); |
Nicolin Chen | 37ac30a | 2018-02-12 14:03:21 -0800 | [diff] [blame] | 1310 | fsl_ssi_setup_ac97(ssi); |
| 1311 | } |
| 1312 | |
Nicolin Chen | a1d154a | 2018-02-12 14:03:20 -0800 | [diff] [blame] | 1313 | return 0; |
| 1314 | } |
| 1315 | |
| 1316 | /** |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 1317 | * fsl_ssi_hw_clean - Clear SSI registers |
| 1318 | * @ssi: SSI context |
Nicolin Chen | 37ac30a | 2018-02-12 14:03:21 -0800 | [diff] [blame] | 1319 | */ |
| 1320 | static void fsl_ssi_hw_clean(struct fsl_ssi *ssi) |
| 1321 | { |
| 1322 | /* Disable registers for AC97 */ |
| 1323 | if (fsl_ssi_is_ac97(ssi)) { |
| 1324 | /* Disable TE and RE bits first */ |
| 1325 | regmap_update_bits(ssi->regs, REG_SSI_SCR, |
| 1326 | SSI_SCR_TE | SSI_SCR_RE, 0); |
| 1327 | /* Disable AC97 mode */ |
| 1328 | regmap_write(ssi->regs, REG_SSI_SACNT, 0); |
| 1329 | /* Unset WAIT bits */ |
| 1330 | regmap_write(ssi->regs, REG_SSI_SOR, 0); |
| 1331 | /* Disable SSI -- software reset */ |
| 1332 | regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0); |
| 1333 | } |
| 1334 | } |
Pierre-Louis Bossart | 6ababfc | 2020-07-02 14:21:37 -0500 | [diff] [blame] | 1335 | |
| 1336 | /* |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1337 | * Make every character in a string lower-case |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1338 | */ |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1339 | static void make_lowercase(char *s) |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1340 | { |
Fabio Estevam | c6682fe | 2017-04-05 16:44:06 -0300 | [diff] [blame] | 1341 | if (!s) |
| 1342 | return; |
| 1343 | for (; *s; s++) |
| 1344 | *s = tolower(*s); |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1345 | } |
| 1346 | |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1347 | static int fsl_ssi_imx_probe(struct platform_device *pdev, |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1348 | struct fsl_ssi *ssi, void __iomem *iomem) |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1349 | { |
Nicolin Chen | 8483c06 | 2017-12-17 18:52:01 -0800 | [diff] [blame] | 1350 | struct device *dev = &pdev->dev; |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1351 | int ret; |
| 1352 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1353 | /* Backward compatible for a DT without ipg clock name assigned */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1354 | if (ssi->has_ipg_clk_name) |
Nicolin Chen | 8483c06 | 2017-12-17 18:52:01 -0800 | [diff] [blame] | 1355 | ssi->clk = devm_clk_get(dev, "ipg"); |
Shengjiu Wang | f4a43ca | 2014-09-16 10:13:16 +0800 | [diff] [blame] | 1356 | else |
Nicolin Chen | 8483c06 | 2017-12-17 18:52:01 -0800 | [diff] [blame] | 1357 | ssi->clk = devm_clk_get(dev, NULL); |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1358 | if (IS_ERR(ssi->clk)) { |
| 1359 | ret = PTR_ERR(ssi->clk); |
Nicolin Chen | 2c22503 | 2017-12-17 18:52:05 -0800 | [diff] [blame] | 1360 | dev_err(dev, "failed to get clock: %d\n", ret); |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1361 | return ret; |
| 1362 | } |
| 1363 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1364 | /* Enable the clock since regmap will not handle it in this case */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1365 | if (!ssi->has_ipg_clk_name) { |
| 1366 | ret = clk_prepare_enable(ssi->clk); |
Shengjiu Wang | f4a43ca | 2014-09-16 10:13:16 +0800 | [diff] [blame] | 1367 | if (ret) { |
Nicolin Chen | 8483c06 | 2017-12-17 18:52:01 -0800 | [diff] [blame] | 1368 | dev_err(dev, "clk_prepare_enable failed: %d\n", ret); |
Shengjiu Wang | f4a43ca | 2014-09-16 10:13:16 +0800 | [diff] [blame] | 1369 | return ret; |
| 1370 | } |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1371 | } |
| 1372 | |
Mark Brown | 89efbda | 2021-09-21 22:35:33 +0100 | [diff] [blame] | 1373 | /* Do not error out for consumer cases that live without a baud clock */ |
Nicolin Chen | 8483c06 | 2017-12-17 18:52:01 -0800 | [diff] [blame] | 1374 | ssi->baudclk = devm_clk_get(dev, "baud"); |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1375 | if (IS_ERR(ssi->baudclk)) |
Nicolin Chen | 2c22503 | 2017-12-17 18:52:05 -0800 | [diff] [blame] | 1376 | dev_dbg(dev, "failed to get baud clock: %ld\n", |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1377 | PTR_ERR(ssi->baudclk)); |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1378 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1379 | ssi->dma_params_tx.maxburst = ssi->dma_maxburst; |
| 1380 | ssi->dma_params_rx.maxburst = ssi->dma_maxburst; |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1381 | ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0; |
| 1382 | ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0; |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1383 | |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1384 | /* Use even numbers to avoid channel swap due to SDMA script design */ |
Shengjiu Wang | 7aded70 | 2022-05-10 19:56:48 +0800 | [diff] [blame] | 1385 | if (ssi->use_dual_fifo || ssi->use_dyna_fifo) { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1386 | ssi->dma_params_tx.maxburst &= ~0x1; |
| 1387 | ssi->dma_params_rx.maxburst &= ~0x1; |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1388 | } |
| 1389 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1390 | if (!ssi->use_dma) { |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1391 | /* |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1392 | * Some boards use an incompatible codec. Use imx-fiq-pcm-audio |
| 1393 | * to get it working, as DMA is not possible in this situation. |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1394 | */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1395 | ssi->fiq_params.irq = ssi->irq; |
| 1396 | ssi->fiq_params.base = iomem; |
| 1397 | ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx; |
| 1398 | ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx; |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1399 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1400 | ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params); |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1401 | if (ret) |
| 1402 | goto error_pcm; |
| 1403 | } else { |
Sascha Hauer | 9b3ff63 | 2022-02-23 14:06:25 +0100 | [diff] [blame] | 1404 | ret = imx_pcm_dma_init(pdev); |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1405 | if (ret) |
| 1406 | goto error_pcm; |
| 1407 | } |
| 1408 | |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1409 | return 0; |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1410 | |
| 1411 | error_pcm: |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1412 | if (!ssi->has_ipg_clk_name) |
| 1413 | clk_disable_unprepare(ssi->clk); |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1414 | |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1415 | return ret; |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1416 | } |
| 1417 | |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1418 | static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi) |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1419 | { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1420 | if (!ssi->use_dma) |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1421 | imx_pcm_fiq_exit(pdev); |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1422 | if (!ssi->has_ipg_clk_name) |
| 1423 | clk_disable_unprepare(ssi->clk); |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1424 | } |
| 1425 | |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1426 | static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi) |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1427 | { |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1428 | struct device *dev = ssi->dev; |
| 1429 | struct device_node *np = dev->of_node; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1430 | const char *p, *sprop; |
Fabio Estevam | da18bcf | 2018-02-11 19:53:21 -0200 | [diff] [blame] | 1431 | const __be32 *iprop; |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1432 | u32 dmas[4]; |
| 1433 | int ret; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1434 | |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1435 | ret = of_property_match_string(np, "clock-names", "ipg"); |
| 1436 | /* Get error code if not found */ |
| 1437 | ssi->has_ipg_clk_name = ret >= 0; |
Sascha Hauer | fcdbadef | 2014-05-27 10:24:18 +0200 | [diff] [blame] | 1438 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1439 | /* Check if being used in AC97 mode */ |
Markus Pargmann | 85e59af | 2014-05-27 10:24:19 +0200 | [diff] [blame] | 1440 | sprop = of_get_property(np, "fsl,mode", NULL); |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1441 | if (sprop && !strcmp(sprop, "ac97-slave")) { |
| 1442 | ssi->dai_fmt = FSLSSI_AC97_DAIFMT; |
| 1443 | |
| 1444 | ret = of_property_read_u32(np, "cell-index", &ssi->card_idx); |
| 1445 | if (ret) { |
| 1446 | dev_err(dev, "failed to get SSI index property\n"); |
| 1447 | return -EINVAL; |
| 1448 | } |
| 1449 | strcpy(ssi->card_name, "ac97-codec"); |
| 1450 | } else if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { |
| 1451 | /* |
| 1452 | * In synchronous mode, STCK and STFS ports are used by RX |
| 1453 | * as well. So the software should limit the sample rates, |
| 1454 | * sample bits and channels to be symmetric. |
| 1455 | * |
| 1456 | * This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs |
| 1457 | * in the SSI synchronous mode however it does not have to |
| 1458 | * limit symmetric sample rates and sample bits. |
| 1459 | */ |
| 1460 | ssi->synchronous = true; |
Markus Pargmann | 85e59af | 2014-05-27 10:24:19 +0200 | [diff] [blame] | 1461 | } |
| 1462 | |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1463 | /* Select DMA or FIQ */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1464 | ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter"); |
Markus Pargmann | de623ec | 2013-07-27 13:31:53 +0200 | [diff] [blame] | 1465 | |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1466 | /* Fetch FIFO depth; Set to 8 for older DT without this property */ |
| 1467 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); |
| 1468 | if (iprop) |
| 1469 | ssi->fifo_depth = be32_to_cpup(iprop); |
| 1470 | else |
| 1471 | ssi->fifo_depth = 8; |
| 1472 | |
| 1473 | /* Use dual FIFO mode depending on the support from SDMA script */ |
| 1474 | ret = of_property_read_u32_array(np, "dmas", dmas, 4); |
| 1475 | if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) |
| 1476 | ssi->use_dual_fifo = true; |
| 1477 | |
Shengjiu Wang | 7aded70 | 2022-05-10 19:56:48 +0800 | [diff] [blame] | 1478 | if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) |
| 1479 | ssi->use_dyna_fifo = true; |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1480 | /* |
| 1481 | * Backward compatible for older bindings by manually triggering the |
| 1482 | * machine driver's probe(). Use /compatible property, including the |
| 1483 | * address of CPU DAI driver structure, as the name of machine driver |
| 1484 | * |
| 1485 | * If card_name is set by AC97 earlier, bypass here since it uses a |
| 1486 | * different name to register the device. |
| 1487 | */ |
| 1488 | if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) { |
Takashi Iwai | 2757970 | 2019-02-19 16:46:47 +0100 | [diff] [blame] | 1489 | struct device_node *root = of_find_node_by_path("/"); |
| 1490 | |
| 1491 | sprop = of_get_property(root, "compatible", NULL); |
| 1492 | of_node_put(root); |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1493 | /* Strip "fsl," in the compatible name if applicable */ |
| 1494 | p = strrchr(sprop, ','); |
| 1495 | if (p) |
| 1496 | sprop = p + 1; |
| 1497 | snprintf(ssi->card_name, sizeof(ssi->card_name), |
| 1498 | "snd-soc-%s", sprop); |
| 1499 | make_lowercase(ssi->card_name); |
| 1500 | ssi->card_idx = 0; |
| 1501 | } |
| 1502 | |
| 1503 | return 0; |
| 1504 | } |
| 1505 | |
| 1506 | static int fsl_ssi_probe(struct platform_device *pdev) |
| 1507 | { |
| 1508 | struct regmap_config regconfig = fsl_ssi_regconfig; |
| 1509 | struct device *dev = &pdev->dev; |
| 1510 | struct fsl_ssi *ssi; |
| 1511 | struct resource *res; |
| 1512 | void __iomem *iomem; |
| 1513 | int ret = 0; |
| 1514 | |
| 1515 | ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL); |
| 1516 | if (!ssi) |
| 1517 | return -ENOMEM; |
| 1518 | |
| 1519 | ssi->dev = dev; |
Fabio Estevam | 9ce6320 | 2021-01-18 09:38:10 -0300 | [diff] [blame] | 1520 | ssi->soc = of_device_get_match_data(&pdev->dev); |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1521 | |
| 1522 | /* Probe from DT */ |
| 1523 | ret = fsl_ssi_probe_from_dt(ssi); |
| 1524 | if (ret) |
| 1525 | return ret; |
| 1526 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1527 | if (fsl_ssi_is_ac97(ssi)) { |
| 1528 | memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai, |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1529 | sizeof(fsl_ssi_ac97_dai)); |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1530 | fsl_ac97_data = ssi; |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1531 | } else { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1532 | memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template, |
Markus Pargmann | cd7f029 | 2013-08-19 17:05:58 +0200 | [diff] [blame] | 1533 | sizeof(fsl_ssi_dai_template)); |
| 1534 | } |
Nicolin Chen | 8483c06 | 2017-12-17 18:52:01 -0800 | [diff] [blame] | 1535 | ssi->cpu_dai_drv.name = dev_name(dev); |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1536 | |
Yang Yingliang | 6779886 | 2021-06-15 09:39:21 +0800 | [diff] [blame] | 1537 | iomem = devm_platform_get_and_ioremap_resource(pdev, 0, &res); |
Fabio Estevam | ca26418 | 2015-04-10 07:12:29 -0300 | [diff] [blame] | 1538 | if (IS_ERR(iomem)) |
| 1539 | return PTR_ERR(iomem); |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1540 | ssi->ssi_phys = res->start; |
Markus Pargmann | 4324812 | 2014-05-27 10:24:25 +0200 | [diff] [blame] | 1541 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1542 | if (ssi->soc->imx21regs) { |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1543 | /* No SACC{ST,EN,DIS} regs in imx21-class SSI */ |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1544 | regconfig.max_register = REG_SSI_SRMSK; |
Mark Brown | f26b3b2 | 2016-09-29 11:22:52 -0700 | [diff] [blame] | 1545 | regconfig.num_reg_defaults_raw = |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1546 | REG_SSI_SRMSK / sizeof(uint32_t) + 1; |
Maciej S. Szmigiero | 6139b1b | 2016-01-18 20:07:44 +0100 | [diff] [blame] | 1547 | } |
| 1548 | |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1549 | if (ssi->has_ipg_clk_name) |
Nicolin Chen | 8483c06 | 2017-12-17 18:52:01 -0800 | [diff] [blame] | 1550 | ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem, |
| 1551 | ®config); |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1552 | else |
| 1553 | ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config); |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1554 | if (IS_ERR(ssi->regs)) { |
Nicolin Chen | 2c22503 | 2017-12-17 18:52:05 -0800 | [diff] [blame] | 1555 | dev_err(dev, "failed to init register map\n"); |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1556 | return PTR_ERR(ssi->regs); |
Markus Pargmann | 4324812 | 2014-05-27 10:24:25 +0200 | [diff] [blame] | 1557 | } |
Timur Tabi | 1fab6ca | 2011-08-16 18:47:45 -0400 | [diff] [blame] | 1558 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1559 | ssi->irq = platform_get_irq(pdev, 0); |
Stephen Boyd | cf9441a | 2019-07-30 11:15:49 -0700 | [diff] [blame] | 1560 | if (ssi->irq < 0) |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1561 | return ssi->irq; |
Timur Tabi | 1fab6ca | 2011-08-16 18:47:45 -0400 | [diff] [blame] | 1562 | |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1563 | /* Set software limitations for synchronous mode except AC97 */ |
| 1564 | if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) { |
Kuninori Morimoto | cb2f692 | 2021-01-15 13:54:08 +0900 | [diff] [blame] | 1565 | ssi->cpu_dai_drv.symmetric_rate = 1; |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1566 | ssi->cpu_dai_drv.symmetric_channels = 1; |
Kuninori Morimoto | cb2f692 | 2021-01-15 13:54:08 +0900 | [diff] [blame] | 1567 | ssi->cpu_dai_drv.symmetric_sample_bits = 1; |
Nicolin Chen | 07a9483 | 2013-12-03 18:38:07 +0800 | [diff] [blame] | 1568 | } |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1569 | |
Caleb Crome | 4ee437f | 2017-01-03 10:22:57 -0800 | [diff] [blame] | 1570 | /* |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1571 | * Configure TX and RX DMA watermarks -- when to send a DMA request |
Caleb Crome | 4ee437f | 2017-01-03 10:22:57 -0800 | [diff] [blame] | 1572 | * |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1573 | * Values should be tested to avoid FIFO under/over run. Set maxburst |
| 1574 | * to fifo_watermark to maxiumize DMA transaction to reduce overhead. |
Caleb Crome | 4ee437f | 2017-01-03 10:22:57 -0800 | [diff] [blame] | 1575 | */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1576 | switch (ssi->fifo_depth) { |
Caleb Crome | 4ee437f | 2017-01-03 10:22:57 -0800 | [diff] [blame] | 1577 | case 15: |
| 1578 | /* |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1579 | * Set to 8 as a balanced configuration -- When TX FIFO has 8 |
| 1580 | * empty slots, send a DMA request to fill these 8 slots. The |
| 1581 | * remaining 7 slots should be able to allow DMA to finish the |
| 1582 | * transaction before TX FIFO underruns; Same applies to RX. |
| 1583 | * |
| 1584 | * Tested with cases running at 48kHz @ 16 bits x 16 channels |
Caleb Crome | 4ee437f | 2017-01-03 10:22:57 -0800 | [diff] [blame] | 1585 | */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1586 | ssi->fifo_watermark = 8; |
| 1587 | ssi->dma_maxburst = 8; |
Caleb Crome | 4ee437f | 2017-01-03 10:22:57 -0800 | [diff] [blame] | 1588 | break; |
| 1589 | case 8: |
| 1590 | default: |
Nicolin Chen | 7a8fceb | 2017-12-17 18:52:02 -0800 | [diff] [blame] | 1591 | /* Safely use old watermark configurations for older chips */ |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1592 | ssi->fifo_watermark = ssi->fifo_depth - 2; |
| 1593 | ssi->dma_maxburst = ssi->fifo_depth - 2; |
Caleb Crome | 4ee437f | 2017-01-03 10:22:57 -0800 | [diff] [blame] | 1594 | break; |
| 1595 | } |
| 1596 | |
Nicolin Chen | 8483c06 | 2017-12-17 18:52:01 -0800 | [diff] [blame] | 1597 | dev_set_drvdata(dev, ssi); |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1598 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1599 | if (ssi->soc->imx) { |
| 1600 | ret = fsl_ssi_imx_probe(pdev, ssi, iomem); |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1601 | if (ret) |
Fabio Estevam | 2ffa531 | 2014-12-01 19:57:14 -0200 | [diff] [blame] | 1602 | return ret; |
Markus Pargmann | 0888efd | 2013-12-20 14:11:31 +0100 | [diff] [blame] | 1603 | } |
| 1604 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1605 | if (fsl_ssi_is_ac97(ssi)) { |
| 1606 | mutex_init(&ssi->ac97_reg_lock); |
Maciej S. Szmigiero | 695b78b | 2017-11-20 23:14:55 +0100 | [diff] [blame] | 1607 | ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); |
| 1608 | if (ret) { |
Nicolin Chen | 2c22503 | 2017-12-17 18:52:05 -0800 | [diff] [blame] | 1609 | dev_err(dev, "failed to set AC'97 ops\n"); |
Maciej S. Szmigiero | 695b78b | 2017-11-20 23:14:55 +0100 | [diff] [blame] | 1610 | goto error_ac97_ops; |
| 1611 | } |
| 1612 | } |
| 1613 | |
Nicolin Chen | 8483c06 | 2017-12-17 18:52:01 -0800 | [diff] [blame] | 1614 | ret = devm_snd_soc_register_component(dev, &fsl_ssi_component, |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1615 | &ssi->cpu_dai_drv, 1); |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1616 | if (ret) { |
Nicolin Chen | 8483c06 | 2017-12-17 18:52:01 -0800 | [diff] [blame] | 1617 | dev_err(dev, "failed to register DAI: %d\n", ret); |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1618 | goto error_asoc_register; |
| 1619 | } |
| 1620 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1621 | if (ssi->use_dma) { |
Nicolin Chen | 8483c06 | 2017-12-17 18:52:01 -0800 | [diff] [blame] | 1622 | ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0, |
| 1623 | dev_name(dev), ssi); |
Michael Grzeschik | f037708 | 2013-08-19 17:06:01 +0200 | [diff] [blame] | 1624 | if (ret < 0) { |
Nicolin Chen | 2c22503 | 2017-12-17 18:52:05 -0800 | [diff] [blame] | 1625 | dev_err(dev, "failed to claim irq %u\n", ssi->irq); |
Fabio Estevam | 299e7e9 | 2015-04-09 14:56:41 -0300 | [diff] [blame] | 1626 | goto error_asoc_register; |
Michael Grzeschik | f037708 | 2013-08-19 17:06:01 +0200 | [diff] [blame] | 1627 | } |
Shawn Guo | 09ce111 | 2012-03-16 16:56:43 +0800 | [diff] [blame] | 1628 | } |
| 1629 | |
Greg Kroah-Hartman | 227ab8b | 2019-06-14 11:47:55 +0200 | [diff] [blame] | 1630 | fsl_ssi_debugfs_create(&ssi->dbg_stats, dev); |
Shawn Guo | 09ce111 | 2012-03-16 16:56:43 +0800 | [diff] [blame] | 1631 | |
Nicolin Chen | a1d154a | 2018-02-12 14:03:20 -0800 | [diff] [blame] | 1632 | /* Initially configures SSI registers */ |
| 1633 | fsl_ssi_hw_init(ssi); |
| 1634 | |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1635 | /* Register a platform device for older bindings or AC97 */ |
| 1636 | if (ssi->card_name[0]) { |
| 1637 | struct device *parent = dev; |
| 1638 | /* |
| 1639 | * Do not set SSI dev as the parent of AC97 CODEC device since |
| 1640 | * it does not have a DT node. Otherwise ASoC core will assume |
| 1641 | * CODEC has the same DT node as the SSI, so it may bypass the |
| 1642 | * dai_probe() of SSI and then cause NULL DMA data pointers. |
| 1643 | */ |
| 1644 | if (fsl_ssi_is_ac97(ssi)) |
| 1645 | parent = NULL; |
Maciej S. Szmigiero | 8ed0c84 | 2015-08-05 17:26:44 +0200 | [diff] [blame] | 1646 | |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1647 | ssi->card_pdev = platform_device_register_data(parent, |
| 1648 | ssi->card_name, ssi->card_idx, NULL, 0); |
| 1649 | if (IS_ERR(ssi->card_pdev)) { |
| 1650 | ret = PTR_ERR(ssi->card_pdev); |
| 1651 | dev_err(dev, "failed to register %s: %d\n", |
| 1652 | ssi->card_name, ret); |
Maciej S. Szmigiero | 8ed0c84 | 2015-08-05 17:26:44 +0200 | [diff] [blame] | 1653 | goto error_sound_card; |
| 1654 | } |
| 1655 | } |
| 1656 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1657 | return 0; |
Timur Tabi | 87a0632 | 2010-08-03 17:55:28 -0500 | [diff] [blame] | 1658 | |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1659 | error_sound_card: |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1660 | fsl_ssi_debugfs_remove(&ssi->dbg_stats); |
Markus Pargmann | 4d9b7926 | 2014-04-28 12:54:47 +0200 | [diff] [blame] | 1661 | error_asoc_register: |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1662 | if (fsl_ssi_is_ac97(ssi)) |
Maciej S. Szmigiero | 695b78b | 2017-11-20 23:14:55 +0100 | [diff] [blame] | 1663 | snd_soc_set_ac97_ops(NULL); |
Maciej S. Szmigiero | 695b78b | 2017-11-20 23:14:55 +0100 | [diff] [blame] | 1664 | error_ac97_ops: |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1665 | if (fsl_ssi_is_ac97(ssi)) |
| 1666 | mutex_destroy(&ssi->ac97_reg_lock); |
Maciej S. Szmigiero | b880b80 | 2017-11-20 23:16:07 +0100 | [diff] [blame] | 1667 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1668 | if (ssi->soc->imx) |
| 1669 | fsl_ssi_imx_clean(pdev, ssi); |
Timur Tabi | 1fab6ca | 2011-08-16 18:47:45 -0400 | [diff] [blame] | 1670 | |
Timur Tabi | 87a0632 | 2010-08-03 17:55:28 -0500 | [diff] [blame] | 1671 | return ret; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1672 | } |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1673 | |
Timur Tabi | 38fec72 | 2010-08-19 15:26:58 -0500 | [diff] [blame] | 1674 | static int fsl_ssi_remove(struct platform_device *pdev) |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1675 | { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1676 | struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1677 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1678 | fsl_ssi_debugfs_remove(&ssi->dbg_stats); |
Markus Pargmann | 9368acc | 2013-12-20 14:11:29 +0100 | [diff] [blame] | 1679 | |
Nicolin Chen | 76f3845 | 2018-02-12 14:03:24 -0800 | [diff] [blame] | 1680 | if (ssi->card_pdev) |
| 1681 | platform_device_unregister(ssi->card_pdev); |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1682 | |
Nicolin Chen | 37ac30a | 2018-02-12 14:03:21 -0800 | [diff] [blame] | 1683 | /* Clean up SSI registers */ |
| 1684 | fsl_ssi_hw_clean(ssi); |
| 1685 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1686 | if (ssi->soc->imx) |
| 1687 | fsl_ssi_imx_clean(pdev, ssi); |
Markus Pargmann | 49da09e | 2014-04-28 12:54:45 +0200 | [diff] [blame] | 1688 | |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1689 | if (fsl_ssi_is_ac97(ssi)) { |
Maciej S. Szmigiero | 04143d6 | 2015-08-05 17:25:31 +0200 | [diff] [blame] | 1690 | snd_soc_set_ac97_ops(NULL); |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1691 | mutex_destroy(&ssi->ac97_reg_lock); |
Maciej S. Szmigiero | b880b80 | 2017-11-20 23:16:07 +0100 | [diff] [blame] | 1692 | } |
Maciej S. Szmigiero | 04143d6 | 2015-08-05 17:25:31 +0200 | [diff] [blame] | 1693 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1694 | return 0; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1695 | } |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1696 | |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 1697 | #ifdef CONFIG_PM_SLEEP |
| 1698 | static int fsl_ssi_suspend(struct device *dev) |
| 1699 | { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1700 | struct fsl_ssi *ssi = dev_get_drvdata(dev); |
| 1701 | struct regmap *regs = ssi->regs; |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 1702 | |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1703 | regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr); |
| 1704 | regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt); |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 1705 | |
| 1706 | regcache_cache_only(regs, true); |
| 1707 | regcache_mark_dirty(regs); |
| 1708 | |
| 1709 | return 0; |
| 1710 | } |
| 1711 | |
| 1712 | static int fsl_ssi_resume(struct device *dev) |
| 1713 | { |
Nicolin Chen | f317683 | 2017-12-17 18:52:00 -0800 | [diff] [blame] | 1714 | struct fsl_ssi *ssi = dev_get_drvdata(dev); |
| 1715 | struct regmap *regs = ssi->regs; |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 1716 | |
| 1717 | regcache_cache_only(regs, false); |
| 1718 | |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1719 | regmap_update_bits(regs, REG_SSI_SFCSR, |
Nicolin Chen | af4f7f3 | 2017-12-17 18:52:04 -0800 | [diff] [blame] | 1720 | SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK | |
| 1721 | SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK, |
| 1722 | ssi->regcache_sfcsr); |
Nicolin Chen | a818aa5 | 2017-12-17 18:52:03 -0800 | [diff] [blame] | 1723 | regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt); |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 1724 | |
| 1725 | return regcache_sync(regs); |
| 1726 | } |
| 1727 | #endif /* CONFIG_PM_SLEEP */ |
| 1728 | |
| 1729 | static const struct dev_pm_ops fsl_ssi_pm = { |
| 1730 | SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume) |
| 1731 | }; |
| 1732 | |
Grant Likely | f07eb22 | 2011-02-22 21:05:04 -0700 | [diff] [blame] | 1733 | static struct platform_driver fsl_ssi_driver = { |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1734 | .driver = { |
| 1735 | .name = "fsl-ssi-dai", |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1736 | .of_match_table = fsl_ssi_ids, |
Zidan Wang | 05cf237 | 2015-09-18 11:09:12 +0800 | [diff] [blame] | 1737 | .pm = &fsl_ssi_pm, |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1738 | }, |
| 1739 | .probe = fsl_ssi_probe, |
| 1740 | .remove = fsl_ssi_remove, |
| 1741 | }; |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1742 | |
Axel Lin | ba0a7e0 | 2011-11-25 10:10:55 +0800 | [diff] [blame] | 1743 | module_platform_driver(fsl_ssi_driver); |
Timur Tabi | a454dad | 2009-03-05 17:23:37 -0600 | [diff] [blame] | 1744 | |
Fabio Estevam | f314280 | 2013-07-20 16:16:01 -0300 | [diff] [blame] | 1745 | MODULE_ALIAS("platform:fsl-ssi-dai"); |
Timur Tabi | 17467f2 | 2008-01-11 18:15:26 +0100 | [diff] [blame] | 1746 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
| 1747 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 1748 | MODULE_LICENSE("GPL v2"); |