blob: 6d4b273469b1914ab019c7cdeb4ec00f1ddd329a [file] [log] [blame]
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001/*
Sujith Manoharan5b681382011-05-17 13:36:18 +05302 * Copyright (c) 2008-2011 Atheros Communications Inc.
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090018#include <linux/slab.h>
Paul Gortmaker9d9779e2011-07-03 15:21:01 -040019#include <linux/module.h>
Felix Fietkau09d8e312013-11-18 20:14:43 +010020#include <linux/time.h>
Felix Fietkauc67ce332013-12-14 18:03:38 +010021#include <linux/bitops.h>
Felix Fietkau5ca06eb2014-10-25 17:19:35 +020022#include <linux/etherdevice.h>
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070023#include <asm/unaligned.h>
24
Luis R. Rodriguezaf03abe2009-09-09 02:33:11 -070025#include "hw.h"
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -040026#include "hw-ops.h"
Luis R. Rodriguezb622a722010-04-15 17:39:28 -040027#include "ar9003_mac.h"
Sujith Manoharanf4701b52012-02-22 12:41:18 +053028#include "ar9003_mci.h"
Sujith Manoharan362cd032012-09-16 08:06:36 +053029#include "ar9003_phy.h"
Ben Greear462e58f2012-04-12 10:04:00 -070030#include "ath9k.h"
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070031
Sujithcbe61d82009-02-09 13:27:12 +053032static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070033
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040034MODULE_AUTHOR("Atheros Communications");
35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37MODULE_LICENSE("Dual BSD/GPL");
38
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020039static void ath9k_hw_set_clockrate(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +053040{
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020041 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkaue4744ec2013-10-11 23:31:01 +020042 struct ath9k_channel *chan = ah->curchan;
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020043 unsigned int clockrate;
Sujithcbe61d82009-02-09 13:27:12 +053044
Felix Fietkau087b6ff2011-07-09 11:12:49 +070045 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
46 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
47 clockrate = 117;
Felix Fietkaue4744ec2013-10-11 23:31:01 +020048 else if (!chan) /* should really check for CCK instead */
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020049 clockrate = ATH9K_CLOCK_RATE_CCK;
Felix Fietkaue4744ec2013-10-11 23:31:01 +020050 else if (IS_CHAN_2GHZ(chan))
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020051 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
52 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
53 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
Vasanthakumar Thiagarajane5553722010-04-26 15:04:33 -040054 else
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020055 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
56
Michal Nazarewiczbeae4162013-11-29 18:06:46 +010057 if (chan) {
58 if (IS_CHAN_HT40(chan))
59 clockrate *= 2;
Felix Fietkaue4744ec2013-10-11 23:31:01 +020060 if (IS_CHAN_HALF_RATE(chan))
Felix Fietkau906c7202011-07-09 11:12:48 +070061 clockrate /= 2;
Felix Fietkaue4744ec2013-10-11 23:31:01 +020062 if (IS_CHAN_QUARTER_RATE(chan))
Felix Fietkau906c7202011-07-09 11:12:48 +070063 clockrate /= 4;
64 }
65
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020066 common->clockrate = clockrate;
Sujithf1dc5602008-10-29 10:16:30 +053067}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070068
Sujithcbe61d82009-02-09 13:27:12 +053069static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
Sujithf1dc5602008-10-29 10:16:30 +053070{
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020071 struct ath_common *common = ath9k_hw_common(ah);
Sujithcbe61d82009-02-09 13:27:12 +053072
Felix Fietkaudfdac8a2010-10-08 22:13:51 +020073 return usecs * common->clockrate;
Sujithf1dc5602008-10-29 10:16:30 +053074}
75
Sujith0caa7b12009-02-16 13:23:20 +053076bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070077{
78 int i;
79
Sujith0caa7b12009-02-16 13:23:20 +053080 BUG_ON(timeout < AH_TIME_QUANTUM);
81
82 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070083 if ((REG_READ(ah, reg) & mask) == val)
84 return true;
85
86 udelay(AH_TIME_QUANTUM);
87 }
Sujith04bd46382008-11-28 22:18:05 +053088
Joe Perchesd2182b62011-12-15 14:55:53 -080089 ath_dbg(ath9k_hw_common(ah), ANY,
Joe Perches226afe62010-12-02 19:12:37 -080090 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
91 timeout, reg, REG_READ(ah, reg), mask, val);
Sujithf1dc5602008-10-29 10:16:30 +053092
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070093 return false;
94}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040095EXPORT_SYMBOL(ath9k_hw_wait);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070096
Felix Fietkau7c5adc82012-04-19 21:18:26 +020097void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
98 int hw_delay)
99{
Felix Fietkau1a5e6322013-10-11 23:30:54 +0200100 hw_delay /= 10;
Felix Fietkau7c5adc82012-04-19 21:18:26 +0200101
102 if (IS_CHAN_HALF_RATE(chan))
103 hw_delay *= 2;
104 else if (IS_CHAN_QUARTER_RATE(chan))
105 hw_delay *= 4;
106
107 udelay(hw_delay + BASE_ACTIVATE_DELAY);
108}
109
Felix Fietkau0166b4b2013-01-20 18:51:55 +0100110void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
Felix Fietkaua9b6b252011-03-23 20:57:27 +0100111 int column, unsigned int *writecnt)
112{
113 int r;
114
115 ENABLE_REGWRITE_BUFFER(ah);
116 for (r = 0; r < array->ia_rows; r++) {
117 REG_WRITE(ah, INI_RA(array, r, 0),
118 INI_RA(array, r, column));
119 DO_DELAY(*writecnt);
120 }
121 REGWRITE_BUFFER_FLUSH(ah);
122}
123
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700124u32 ath9k_hw_reverse_bits(u32 val, u32 n)
125{
126 u32 retval;
127 int i;
128
129 for (i = 0, retval = 0; i < n; i++) {
130 retval = (retval << 1) | (val & 1);
131 val >>= 1;
132 }
133 return retval;
134}
135
Sujithcbe61d82009-02-09 13:27:12 +0530136u16 ath9k_hw_computetxtime(struct ath_hw *ah,
Felix Fietkau545750d2009-11-23 22:21:01 +0100137 u8 phy, int kbps,
Sujithf1dc5602008-10-29 10:16:30 +0530138 u32 frameLen, u16 rateix,
139 bool shortPreamble)
140{
141 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
Sujithf1dc5602008-10-29 10:16:30 +0530142
143 if (kbps == 0)
144 return 0;
145
Felix Fietkau545750d2009-11-23 22:21:01 +0100146 switch (phy) {
Sujith46d14a52008-11-18 09:08:13 +0530147 case WLAN_RC_PHY_CCK:
Sujithf1dc5602008-10-29 10:16:30 +0530148 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
Felix Fietkau545750d2009-11-23 22:21:01 +0100149 if (shortPreamble)
Sujithf1dc5602008-10-29 10:16:30 +0530150 phyTime >>= 1;
151 numBits = frameLen << 3;
152 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
153 break;
Sujith46d14a52008-11-18 09:08:13 +0530154 case WLAN_RC_PHY_OFDM:
Sujith2660b812009-02-09 13:27:26 +0530155 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530156 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
157 numBits = OFDM_PLCP_BITS + (frameLen << 3);
158 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
159 txTime = OFDM_SIFS_TIME_QUARTER
160 + OFDM_PREAMBLE_TIME_QUARTER
161 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
Sujith2660b812009-02-09 13:27:26 +0530162 } else if (ah->curchan &&
163 IS_CHAN_HALF_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530164 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
165 numBits = OFDM_PLCP_BITS + (frameLen << 3);
166 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
167 txTime = OFDM_SIFS_TIME_HALF +
168 OFDM_PREAMBLE_TIME_HALF
169 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
170 } else {
171 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
172 numBits = OFDM_PLCP_BITS + (frameLen << 3);
173 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
174 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
175 + (numSymbols * OFDM_SYMBOL_TIME);
176 }
177 break;
178 default:
Joe Perches38002762010-12-02 19:12:36 -0800179 ath_err(ath9k_hw_common(ah),
180 "Unknown phy %u (rate ix %u)\n", phy, rateix);
Sujithf1dc5602008-10-29 10:16:30 +0530181 txTime = 0;
182 break;
183 }
184
185 return txTime;
186}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400187EXPORT_SYMBOL(ath9k_hw_computetxtime);
Sujithf1dc5602008-10-29 10:16:30 +0530188
Sujithcbe61d82009-02-09 13:27:12 +0530189void ath9k_hw_get_channel_centers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530190 struct ath9k_channel *chan,
191 struct chan_centers *centers)
192{
193 int8_t extoff;
Sujithf1dc5602008-10-29 10:16:30 +0530194
195 if (!IS_CHAN_HT40(chan)) {
196 centers->ctl_center = centers->ext_center =
197 centers->synth_center = chan->channel;
198 return;
199 }
200
Felix Fietkau88969342013-10-11 23:30:53 +0200201 if (IS_CHAN_HT40PLUS(chan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530202 centers->synth_center =
203 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
204 extoff = 1;
205 } else {
206 centers->synth_center =
207 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
208 extoff = -1;
209 }
210
211 centers->ctl_center =
212 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700213 /* 25 MHz spacing is supported by hw but not on upper layers */
Sujithf1dc5602008-10-29 10:16:30 +0530214 centers->ext_center =
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700215 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
Sujithf1dc5602008-10-29 10:16:30 +0530216}
217
218/******************/
219/* Chip Revisions */
220/******************/
221
Sujithcbe61d82009-02-09 13:27:12 +0530222static void ath9k_hw_read_revisions(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530223{
224 u32 val;
225
Felix Fietkau09c74f72014-09-27 22:49:43 +0200226 if (ah->get_mac_revision)
227 ah->hw_version.macRev = ah->get_mac_revision();
228
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530229 switch (ah->hw_version.devid) {
230 case AR5416_AR9100_DEVID:
231 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
232 break;
Gabor Juhos37625612011-06-21 11:23:23 +0200233 case AR9300_DEVID_AR9330:
234 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
Felix Fietkau09c74f72014-09-27 22:49:43 +0200235 if (!ah->get_mac_revision) {
Gabor Juhos37625612011-06-21 11:23:23 +0200236 val = REG_READ(ah, AR_SREV);
237 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
238 }
239 return;
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530240 case AR9300_DEVID_AR9340:
241 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530242 return;
Gabor Juhos813831d2012-07-03 19:13:17 +0200243 case AR9300_DEVID_QCA955X:
244 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
245 return;
Sujith Manoharane6b1e462013-12-31 08:11:59 +0530246 case AR9300_DEVID_AR953X:
247 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
248 return;
Vasanthakumar Thiagarajanecb1d382011-04-19 19:29:18 +0530249 }
250
Sujithf1dc5602008-10-29 10:16:30 +0530251 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
252
253 if (val == 0xFF) {
254 val = REG_READ(ah, AR_SREV);
Sujithd535a422009-02-09 13:27:06 +0530255 ah->hw_version.macVersion =
256 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
257 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
Mohammed Shafi Shajakhan76ed94b2011-09-30 11:31:28 +0530258
Sujith Manoharan77fac462012-09-11 20:09:18 +0530259 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
Mohammed Shafi Shajakhan76ed94b2011-09-30 11:31:28 +0530260 ah->is_pciexpress = true;
261 else
262 ah->is_pciexpress = (val &
263 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
Sujithf1dc5602008-10-29 10:16:30 +0530264 } else {
265 if (!AR_SREV_9100(ah))
Sujithd535a422009-02-09 13:27:06 +0530266 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
Sujithf1dc5602008-10-29 10:16:30 +0530267
Sujithd535a422009-02-09 13:27:06 +0530268 ah->hw_version.macRev = val & AR_SREV_REVISION;
Sujithf1dc5602008-10-29 10:16:30 +0530269
Sujithd535a422009-02-09 13:27:06 +0530270 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
Sujith2660b812009-02-09 13:27:26 +0530271 ah->is_pciexpress = true;
Sujithf1dc5602008-10-29 10:16:30 +0530272 }
273}
274
Sujithf1dc5602008-10-29 10:16:30 +0530275/************************************/
276/* HW Attach, Detach, Init Routines */
277/************************************/
278
Sujithcbe61d82009-02-09 13:27:12 +0530279static void ath9k_hw_disablepcie(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530280{
Felix Fietkau040b74f2010-12-12 00:51:07 +0100281 if (!AR_SREV_5416(ah))
Sujithf1dc5602008-10-29 10:16:30 +0530282 return;
283
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
293
294 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
295}
296
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400297/* This should work for all families including legacy */
Sujithcbe61d82009-02-09 13:27:12 +0530298static bool ath9k_hw_chip_test(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530299{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700300 struct ath_common *common = ath9k_hw_common(ah);
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400301 u32 regAddr[2] = { AR_STA_ID0 };
Sujithf1dc5602008-10-29 10:16:30 +0530302 u32 regHold[2];
Joe Perches07b2fa52010-11-20 18:38:53 -0800303 static const u32 patternData[4] = {
304 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
305 };
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400306 int i, j, loop_max;
Sujithf1dc5602008-10-29 10:16:30 +0530307
Senthil Balasubramanian1f3f0612010-04-15 17:38:29 -0400308 if (!AR_SREV_9300_20_OR_LATER(ah)) {
309 loop_max = 2;
310 regAddr[1] = AR_PHY_BASE + (8 << 2);
311 } else
312 loop_max = 1;
313
314 for (i = 0; i < loop_max; i++) {
Sujithf1dc5602008-10-29 10:16:30 +0530315 u32 addr = regAddr[i];
316 u32 wrData, rdData;
317
318 regHold[i] = REG_READ(ah, addr);
319 for (j = 0; j < 0x100; j++) {
320 wrData = (j << 16) | j;
321 REG_WRITE(ah, addr, wrData);
322 rdData = REG_READ(ah, addr);
323 if (rdData != wrData) {
Joe Perches38002762010-12-02 19:12:36 -0800324 ath_err(common,
325 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
326 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530327 return false;
328 }
329 }
330 for (j = 0; j < 4; j++) {
331 wrData = patternData[j];
332 REG_WRITE(ah, addr, wrData);
333 rdData = REG_READ(ah, addr);
334 if (wrData != rdData) {
Joe Perches38002762010-12-02 19:12:36 -0800335 ath_err(common,
336 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
337 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530338 return false;
339 }
340 }
341 REG_WRITE(ah, regAddr[i], regHold[i]);
342 }
343 udelay(100);
Sujithcbe61d82009-02-09 13:27:12 +0530344
Sujithf1dc5602008-10-29 10:16:30 +0530345 return true;
346}
347
Luis R. Rodriguezb8b0f372009-08-03 12:24:43 -0700348static void ath9k_hw_init_config(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700349{
Sujith Manoharanf57cf932013-12-28 09:47:12 +0530350 struct ath_common *common = ath9k_hw_common(ah);
351
Felix Fietkau689e7562012-04-12 22:35:56 +0200352 ah->config.dma_beacon_response_time = 1;
353 ah->config.sw_beacon_response_time = 6;
Sujith2660b812009-02-09 13:27:26 +0530354 ah->config.cwm_ignore_extcca = 0;
Sujith2660b812009-02-09 13:27:26 +0530355 ah->config.analog_shiftreg = 1;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700356
Sujith0ce024c2009-12-14 14:57:00 +0530357 ah->config.rx_intr_mitigation = true;
Luis R. Rodriguez61584252009-03-12 18:18:49 -0400358
Sujith Manoharana64e1a42014-01-23 08:20:30 +0530359 if (AR_SREV_9300_20_OR_LATER(ah)) {
360 ah->config.rimt_last = 500;
361 ah->config.rimt_first = 2000;
362 } else {
363 ah->config.rimt_last = 250;
364 ah->config.rimt_first = 700;
365 }
366
Luis R. Rodriguez61584252009-03-12 18:18:49 -0400367 /*
368 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
369 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
370 * This means we use it for all AR5416 devices, and the few
371 * minor PCI AR9280 devices out there.
372 *
373 * Serialization is required because these devices do not handle
374 * well the case of two concurrent reads/writes due to the latency
375 * involved. During one read/write another read/write can be issued
376 * on another CPU while the previous read/write may still be working
377 * on our hardware, if we hit this case the hardware poops in a loop.
378 * We prevent this by serializing reads and writes.
379 *
380 * This issue is not present on PCI-Express devices or pre-AR5416
381 * devices (legacy, 802.11abg).
382 */
383 if (num_possible_cpus() > 1)
David S. Miller2d6a5e92009-03-17 15:01:30 -0700384 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
Sujith Manoharanf57cf932013-12-28 09:47:12 +0530385
386 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
387 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
388 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
389 !ah->is_pciexpress)) {
390 ah->config.serialize_regmode = SER_REG_MODE_ON;
391 } else {
392 ah->config.serialize_regmode = SER_REG_MODE_OFF;
393 }
394 }
395
396 ath_dbg(common, RESET, "serialize_regmode is %d\n",
397 ah->config.serialize_regmode);
398
399 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
400 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
401 else
402 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700403}
404
Luis R. Rodriguez50aca252009-08-03 12:24:42 -0700405static void ath9k_hw_init_defaults(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700406{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700407 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
408
409 regulatory->country_code = CTRY_DEFAULT;
410 regulatory->power_limit = MAX_RATE_POWER;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700411
Sujithd535a422009-02-09 13:27:06 +0530412 ah->hw_version.magic = AR5416_MAGIC;
Sujithd535a422009-02-09 13:27:06 +0530413 ah->hw_version.subvendorid = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700414
Sujith Manoharanf57cf932013-12-28 09:47:12 +0530415 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
416 AR_STA_ID1_MCAST_KSRCH;
Felix Fietkauf1717602011-03-19 13:55:41 +0100417 if (AR_SREV_9100(ah))
418 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
Sujith Manoharanf57cf932013-12-28 09:47:12 +0530419
Rajkumar Manoharane3f2acc2011-08-27 11:22:59 +0530420 ah->slottime = ATH9K_SLOT_TIME_9;
Sujith2660b812009-02-09 13:27:26 +0530421 ah->globaltxtimeout = (u32) -1;
Gabor Juhoscbdec972009-07-24 17:27:22 +0200422 ah->power_mode = ATH9K_PM_UNDEFINED;
Felix Fietkau8efa7a82012-03-14 16:40:23 +0100423 ah->htc_reset_init = true;
Sujith Manoharanf57cf932013-12-28 09:47:12 +0530424
425 ah->ani_function = ATH9K_ANI_ALL;
426 if (!AR_SREV_9300_20_OR_LATER(ah))
427 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
428
429 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
430 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
431 else
432 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700433}
434
Sujithcbe61d82009-02-09 13:27:12 +0530435static int ath9k_hw_init_macaddr(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700436{
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700437 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530438 u32 sum;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700439 int i;
Sujithf1dc5602008-10-29 10:16:30 +0530440 u16 eeval;
Joe Perches07b2fa52010-11-20 18:38:53 -0800441 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700442
Sujithf1dc5602008-10-29 10:16:30 +0530443 sum = 0;
444 for (i = 0; i < 3; i++) {
Luis R. Rodriguez49101672010-04-15 17:39:13 -0400445 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530446 sum += eeval;
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700447 common->macaddr[2 * i] = eeval >> 8;
448 common->macaddr[2 * i + 1] = eeval & 0xff;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700449 }
Felix Fietkau5ca06eb2014-10-25 17:19:35 +0200450 if (!is_valid_ether_addr(common->macaddr)) {
451 ath_err(common,
452 "eeprom contains invalid mac address: %pM\n",
453 common->macaddr);
454
455 random_ether_addr(common->macaddr);
456 ath_err(common,
457 "random mac address will be used: %pM\n",
458 common->macaddr);
459 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700460
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700461 return 0;
462}
463
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700464static int ath9k_hw_post_init(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700465{
Sujith Manoharan6cae913d2011-01-04 13:16:37 +0530466 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700467 int ecode;
468
Sujith Manoharan6cae913d2011-01-04 13:16:37 +0530469 if (common->bus_ops->ath_bus_type != ATH_USB) {
Sujith527d4852010-03-17 14:25:16 +0530470 if (!ath9k_hw_chip_test(ah))
471 return -ENODEV;
472 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700473
Luis R. Rodriguezebd5a142010-04-15 17:39:18 -0400474 if (!AR_SREV_9300_20_OR_LATER(ah)) {
475 ecode = ar9002_hw_rf_claim(ah);
476 if (ecode != 0)
477 return ecode;
478 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700479
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700480 ecode = ath9k_hw_eeprom_init(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700481 if (ecode != 0)
482 return ecode;
Sujith7d01b222009-03-13 08:55:55 +0530483
Joe Perchesd2182b62011-12-15 14:55:53 -0800484 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
Joe Perches226afe62010-12-02 19:12:37 -0800485 ah->eep_ops->get_eeprom_ver(ah),
486 ah->eep_ops->get_eeprom_rev(ah));
Sujith7d01b222009-03-13 08:55:55 +0530487
Sujith Manoharane3233002013-06-03 09:19:26 +0530488 ath9k_hw_ani_init(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530489
Sujith Manoharand3b371c2013-09-03 10:28:55 +0530490 /*
491 * EEPROM needs to be initialized before we do this.
492 * This is required for regulatory compliance.
493 */
Sujith Manoharan0c7c2bb2013-12-06 16:28:50 +0530494 if (AR_SREV_9300_20_OR_LATER(ah)) {
Sujith Manoharand3b371c2013-09-03 10:28:55 +0530495 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
496 if ((regdmn & 0xF0) == CTL_FCC) {
Sujith Manoharan0c7c2bb2013-12-06 16:28:50 +0530497 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
498 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
Sujith Manoharand3b371c2013-09-03 10:28:55 +0530499 }
500 }
501
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700502 return 0;
503}
504
Felix Fietkauc1b976d2012-12-12 13:14:23 +0100505static int ath9k_hw_attach_ops(struct ath_hw *ah)
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700506{
Felix Fietkauc1b976d2012-12-12 13:14:23 +0100507 if (!AR_SREV_9300_20_OR_LATER(ah))
508 return ar9002_hw_attach_ops(ah);
509
510 ar9003_hw_attach_ops(ah);
511 return 0;
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700512}
513
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400514/* Called for all hardware families */
515static int __ath9k_hw_init(struct ath_hw *ah)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700516{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700517 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700518 int r = 0;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700519
Senthil Balasubramanianac45c122010-12-22 21:14:20 +0530520 ath9k_hw_read_revisions(ah);
521
Sujith Manoharande825822013-12-28 09:47:11 +0530522 switch (ah->hw_version.macVersion) {
523 case AR_SREV_VERSION_5416_PCI:
524 case AR_SREV_VERSION_5416_PCIE:
525 case AR_SREV_VERSION_9160:
526 case AR_SREV_VERSION_9100:
527 case AR_SREV_VERSION_9280:
528 case AR_SREV_VERSION_9285:
529 case AR_SREV_VERSION_9287:
530 case AR_SREV_VERSION_9271:
531 case AR_SREV_VERSION_9300:
532 case AR_SREV_VERSION_9330:
533 case AR_SREV_VERSION_9485:
534 case AR_SREV_VERSION_9340:
535 case AR_SREV_VERSION_9462:
536 case AR_SREV_VERSION_9550:
537 case AR_SREV_VERSION_9565:
Sujith Manoharane6b1e462013-12-31 08:11:59 +0530538 case AR_SREV_VERSION_9531:
Sujith Manoharande825822013-12-28 09:47:11 +0530539 break;
540 default:
541 ath_err(common,
542 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
543 ah->hw_version.macVersion, ah->hw_version.macRev);
544 return -EOPNOTSUPP;
545 }
546
Senthil Balasubramanian0a8d7cb2010-12-22 19:17:18 +0530547 /*
548 * Read back AR_WA into a permanent copy and set bits 14 and 17.
549 * We need to do this to avoid RMW of this register. We cannot
550 * read the reg when chip is asleep.
551 */
Sujith Manoharan27251e02013-08-27 11:34:39 +0530552 if (AR_SREV_9300_20_OR_LATER(ah)) {
553 ah->WARegVal = REG_READ(ah, AR_WA);
554 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
555 AR_WA_ASPM_TIMER_BASED_DISABLE);
556 }
Senthil Balasubramanian0a8d7cb2010-12-22 19:17:18 +0530557
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700558 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
Joe Perches38002762010-12-02 19:12:36 -0800559 ath_err(common, "Couldn't reset chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700560 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700561 }
562
Sujith Manoharana4a29542012-09-10 09:20:03 +0530563 if (AR_SREV_9565(ah)) {
564 ah->WARegVal |= AR_WA_BIT22;
565 REG_WRITE(ah, AR_WA, ah->WARegVal);
566 }
567
Luis R. Rodriguezbab1f622010-04-15 17:38:20 -0400568 ath9k_hw_init_defaults(ah);
569 ath9k_hw_init_config(ah);
570
Felix Fietkauc1b976d2012-12-12 13:14:23 +0100571 r = ath9k_hw_attach_ops(ah);
572 if (r)
573 return r;
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400574
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -0700575 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
Joe Perches38002762010-12-02 19:12:36 -0800576 ath_err(common, "Couldn't wakeup chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700577 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700578 }
579
Gabor Juhos2c8e5932011-06-21 11:23:21 +0200580 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
Gabor Juhosc95b5842012-07-03 19:13:20 +0200581 AR_SREV_9330(ah) || AR_SREV_9550(ah))
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400582 ah->is_pciexpress = false;
583
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700584 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700585 ath9k_hw_init_cal_settings(ah);
586
Stanislaw Gruszka69ce6742011-08-05 13:10:34 +0200587 if (!ah->is_pciexpress)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700588 ath9k_hw_disablepcie(ah);
589
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700590 r = ath9k_hw_post_init(ah);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700591 if (r)
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700592 return r;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700593
594 ath9k_hw_init_mode_gain_regs(ah);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +0100595 r = ath9k_hw_fill_cap_info(ah);
596 if (r)
597 return r;
598
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700599 r = ath9k_hw_init_macaddr(ah);
600 if (r) {
Joe Perches38002762010-12-02 19:12:36 -0800601 ath_err(common, "Failed to initialize MAC address\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700602 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700603 }
604
Sujith Manoharan45987022013-12-24 10:44:18 +0530605 ath9k_hw_init_hang_checks(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700606
Luis R. Rodriguez211f5852009-10-06 21:19:07 -0400607 common->state = ATH_HW_INITIALIZED;
608
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700609 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700610}
611
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400612int ath9k_hw_init(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530613{
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400614 int ret;
615 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530616
Sujith Manoharan77fac462012-09-11 20:09:18 +0530617 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400618 switch (ah->hw_version.devid) {
619 case AR5416_DEVID_PCI:
620 case AR5416_DEVID_PCIE:
621 case AR5416_AR9100_DEVID:
622 case AR9160_DEVID_PCI:
623 case AR9280_DEVID_PCI:
624 case AR9280_DEVID_PCIE:
625 case AR9285_DEVID_PCIE:
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -0400626 case AR9287_DEVID_PCI:
627 case AR9287_DEVID_PCIE:
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400628 case AR2427_DEVID_PCIE:
Senthil Balasubramaniandb3cc532010-04-15 17:38:18 -0400629 case AR9300_DEVID_PCIE:
Vasanthakumar Thiagarajan3050c912010-12-06 04:27:36 -0800630 case AR9300_DEVID_AR9485_PCIE:
Gabor Juhos999a7a82011-06-21 11:23:52 +0200631 case AR9300_DEVID_AR9330:
Vasanthakumar Thiagarajanbca04682011-04-19 19:29:20 +0530632 case AR9300_DEVID_AR9340:
Gabor Juhos2b943a32012-07-03 19:13:34 +0200633 case AR9300_DEVID_QCA955X:
Luis R. Rodriguez5a63ef02011-08-24 15:36:08 -0700634 case AR9300_DEVID_AR9580:
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530635 case AR9300_DEVID_AR9462:
Mohammed Shafi Shajakhand4e59792012-08-02 11:58:50 +0530636 case AR9485_DEVID_AR1111:
Sujith Manoharan77fac462012-09-11 20:09:18 +0530637 case AR9300_DEVID_AR9565:
Sujith Manoharane6b1e462013-12-31 08:11:59 +0530638 case AR9300_DEVID_AR953X:
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400639 break;
640 default:
641 if (common->bus_ops->ath_bus_type == ATH_USB)
642 break;
Joe Perches38002762010-12-02 19:12:36 -0800643 ath_err(common, "Hardware device ID 0x%04x not supported\n",
644 ah->hw_version.devid);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400645 return -EOPNOTSUPP;
646 }
Sujithf1dc5602008-10-29 10:16:30 +0530647
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400648 ret = __ath9k_hw_init(ah);
649 if (ret) {
Joe Perches38002762010-12-02 19:12:36 -0800650 ath_err(common,
651 "Unable to initialize hardware; initialization status: %d\n",
652 ret);
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400653 return ret;
654 }
Sujithf1dc5602008-10-29 10:16:30 +0530655
Lorenzo Bianconic774d572014-09-16 02:13:09 +0200656 ath_dynack_init(ah);
657
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400658 return 0;
Sujithf1dc5602008-10-29 10:16:30 +0530659}
Luis R. Rodriguezd70357d2010-04-15 17:38:06 -0400660EXPORT_SYMBOL(ath9k_hw_init);
Sujithf1dc5602008-10-29 10:16:30 +0530661
Sujithcbe61d82009-02-09 13:27:12 +0530662static void ath9k_hw_init_qos(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530663{
Sujith7d0d0df2010-04-16 11:53:57 +0530664 ENABLE_REGWRITE_BUFFER(ah);
665
Sujithf1dc5602008-10-29 10:16:30 +0530666 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
667 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
668
669 REG_WRITE(ah, AR_QOS_NO_ACK,
670 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
671 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
672 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
673
674 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
675 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
676 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
677 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
678 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
Sujith7d0d0df2010-04-16 11:53:57 +0530679
680 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530681}
682
Senthil Balasubramanianb84628e2011-04-22 11:32:12 +0530683u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
Vivek Natarajanb1415812011-01-27 14:45:07 +0530684{
Mohammed Shafi Shajakhanf18e3c62012-06-18 13:13:30 +0530685 struct ath_common *common = ath9k_hw_common(ah);
686 int i = 0;
687
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100688 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
689 udelay(100);
690 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
691
Mohammed Shafi Shajakhanf18e3c62012-06-18 13:13:30 +0530692 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
693
Vivek Natarajanb1415812011-01-27 14:45:07 +0530694 udelay(100);
Vivek Natarajanb1415812011-01-27 14:45:07 +0530695
Mohammed Shafi Shajakhanf18e3c62012-06-18 13:13:30 +0530696 if (WARN_ON_ONCE(i >= 100)) {
697 ath_err(common, "PLL4 meaurement not done\n");
698 break;
699 }
700
701 i++;
702 }
703
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100704 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
Vivek Natarajanb1415812011-01-27 14:45:07 +0530705}
706EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
707
Sujithcbe61d82009-02-09 13:27:12 +0530708static void ath9k_hw_init_pll(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530709 struct ath9k_channel *chan)
710{
Vasanthakumar Thiagarajand09b17f2010-12-06 04:27:44 -0800711 u32 pll;
712
Felix Fietkau5fb9b1b2014-09-29 20:45:42 +0200713 pll = ath9k_hw_compute_pll_control(ah, chan);
714
Sujith Manoharana4a29542012-09-10 09:20:03 +0530715 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530716 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
717 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
718 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
720 AR_CH0_DPLL2_KD, 0x40);
721 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
722 AR_CH0_DPLL2_KI, 0x4);
Vivek Natarajan22983c32011-01-27 14:45:09 +0530723
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530724 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
725 AR_CH0_BB_DPLL1_REFDIV, 0x5);
726 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
727 AR_CH0_BB_DPLL1_NINI, 0x58);
728 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
729 AR_CH0_BB_DPLL1_NFRAC, 0x0);
730
731 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
732 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
733 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
734 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
735 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
736 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
737
738 /* program BB PLL phase_shift to 0x6 */
739 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
740 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
741
742 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
743 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
Vivek Natarajan75e03512011-03-10 11:05:42 +0530744 udelay(1000);
Gabor Juhosa5415d62011-06-21 11:23:29 +0200745 } else if (AR_SREV_9330(ah)) {
746 u32 ddr_dpll2, pll_control2, kd;
747
748 if (ah->is_clk_25mhz) {
749 ddr_dpll2 = 0x18e82f01;
750 pll_control2 = 0xe04a3d;
751 kd = 0x1d;
752 } else {
753 ddr_dpll2 = 0x19e82f01;
754 pll_control2 = 0x886666;
755 kd = 0x3d;
756 }
757
758 /* program DDR PLL ki and kd value */
759 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
760
761 /* program DDR PLL phase_shift */
762 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
763 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
764
Felix Fietkau5fb9b1b2014-09-29 20:45:42 +0200765 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
766 pll | AR_RTC_9300_PLL_BYPASS);
Gabor Juhosa5415d62011-06-21 11:23:29 +0200767 udelay(1000);
768
769 /* program refdiv, nint, frac to RTC register */
770 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
771
772 /* program BB PLL kd and ki value */
773 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
775
776 /* program BB PLL phase_shift */
777 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
778 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
Sujith Manoharan2c323052013-12-31 08:12:02 +0530779 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530780 u32 regval, pll2_divint, pll2_divfrac, refdiv;
781
Felix Fietkau5fb9b1b2014-09-29 20:45:42 +0200782 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
783 pll | AR_RTC_9300_SOC_PLL_BYPASS);
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530784 udelay(1000);
785
786 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
787 udelay(100);
788
789 if (ah->is_clk_25mhz) {
Sujith Manoharan2c323052013-12-31 08:12:02 +0530790 if (AR_SREV_9531(ah)) {
791 pll2_divint = 0x1c;
792 pll2_divfrac = 0xa3d2;
793 refdiv = 1;
794 } else {
795 pll2_divint = 0x54;
796 pll2_divfrac = 0x1eb85;
797 refdiv = 3;
798 }
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530799 } else {
Gabor Juhosfc05a312012-07-03 19:13:31 +0200800 if (AR_SREV_9340(ah)) {
801 pll2_divint = 88;
802 pll2_divfrac = 0;
803 refdiv = 5;
804 } else {
805 pll2_divint = 0x11;
Rajkumar Manoharan76ac9ed2014-06-24 22:27:40 +0530806 pll2_divfrac =
807 AR_SREV_9531(ah) ? 0x26665 : 0x26666;
Gabor Juhosfc05a312012-07-03 19:13:31 +0200808 refdiv = 1;
809 }
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530810 }
811
812 regval = REG_READ(ah, AR_PHY_PLL_MODE);
Sujith Manoharan2c323052013-12-31 08:12:02 +0530813 if (AR_SREV_9531(ah))
814 regval |= (0x1 << 22);
815 else
816 regval |= (0x1 << 16);
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530817 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
818 udelay(100);
819
820 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
821 (pll2_divint << 18) | pll2_divfrac);
822 udelay(100);
823
824 regval = REG_READ(ah, AR_PHY_PLL_MODE);
Gabor Juhosfc05a312012-07-03 19:13:31 +0200825 if (AR_SREV_9340(ah))
Sujith Manoharan2c323052013-12-31 08:12:02 +0530826 regval = (regval & 0x80071fff) |
827 (0x1 << 30) |
828 (0x1 << 13) |
829 (0x4 << 26) |
830 (0x18 << 19);
831 else if (AR_SREV_9531(ah))
832 regval = (regval & 0x01c00fff) |
833 (0x1 << 31) |
834 (0x2 << 29) |
835 (0xa << 25) |
836 (0x1 << 19) |
837 (0x6 << 12);
Gabor Juhosfc05a312012-07-03 19:13:31 +0200838 else
Sujith Manoharan2c323052013-12-31 08:12:02 +0530839 regval = (regval & 0x80071fff) |
840 (0x3 << 30) |
841 (0x1 << 13) |
842 (0x4 << 26) |
843 (0x60 << 19);
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530844 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
Sujith Manoharan2c323052013-12-31 08:12:02 +0530845
846 if (AR_SREV_9531(ah))
847 REG_WRITE(ah, AR_PHY_PLL_MODE,
848 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
849 else
850 REG_WRITE(ah, AR_PHY_PLL_MODE,
851 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
852
Vasanthakumar Thiagarajan0b488ac2011-04-20 10:26:15 +0530853 udelay(1000);
Vivek Natarajan22983c32011-01-27 14:45:09 +0530854 }
Vasanthakumar Thiagarajand09b17f2010-12-06 04:27:44 -0800855
Sujith Manoharan8565f8b2012-09-10 09:20:29 +0530856 if (AR_SREV_9565(ah))
857 pll |= 0x40000;
Gabor Juhosd03a66c2009-01-14 20:17:09 +0100858 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
Sujithf1dc5602008-10-29 10:16:30 +0530859
Gabor Juhosfc05a312012-07-03 19:13:31 +0200860 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
861 AR_SREV_9550(ah))
Vasanthakumar Thiagarajan3dfd7f62011-04-11 16:39:40 +0530862 udelay(1000);
863
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -0400864 /* Switch the core clock for ar9271 to 117Mhz */
865 if (AR_SREV_9271(ah)) {
Sujith25e2ab12010-03-17 14:25:22 +0530866 udelay(500);
867 REG_WRITE(ah, 0x50040, 0x304);
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -0400868 }
869
Sujithf1dc5602008-10-29 10:16:30 +0530870 udelay(RTC_PLL_SETTLE_DELAY);
871
872 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
873}
874
Sujithcbe61d82009-02-09 13:27:12 +0530875static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
Colin McCabed97809d2008-12-01 13:38:55 -0800876 enum nl80211_iftype opmode)
Sujithf1dc5602008-10-29 10:16:30 +0530877{
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530878 u32 sync_default = AR_INTR_SYNC_DEFAULT;
Pavel Roskin152d5302010-03-31 18:05:37 -0400879 u32 imr_reg = AR_IMR_TXERR |
Sujithf1dc5602008-10-29 10:16:30 +0530880 AR_IMR_TXURN |
881 AR_IMR_RXERR |
882 AR_IMR_RXORN |
883 AR_IMR_BCNMISC;
884
Sujith Manoharanc90d4f72014-03-17 15:02:47 +0530885 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530886 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
887
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400888 if (AR_SREV_9300_20_OR_LATER(ah)) {
889 imr_reg |= AR_IMR_RXOK_HP;
890 if (ah->config.rx_intr_mitigation)
891 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
892 else
893 imr_reg |= AR_IMR_RXOK_LP;
Sujithf1dc5602008-10-29 10:16:30 +0530894
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400895 } else {
896 if (ah->config.rx_intr_mitigation)
897 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
898 else
899 imr_reg |= AR_IMR_RXOK;
900 }
901
902 if (ah->config.tx_intr_mitigation)
903 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
904 else
905 imr_reg |= AR_IMR_TXOK;
Sujithf1dc5602008-10-29 10:16:30 +0530906
Sujith7d0d0df2010-04-16 11:53:57 +0530907 ENABLE_REGWRITE_BUFFER(ah);
908
Pavel Roskin152d5302010-03-31 18:05:37 -0400909 REG_WRITE(ah, AR_IMR, imr_reg);
Pavel Roskin74bad5c2010-02-23 18:15:27 -0500910 ah->imrs2_reg |= AR_IMR_S2_GTT;
911 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
Sujithf1dc5602008-10-29 10:16:30 +0530912
913 if (!AR_SREV_9100(ah)) {
914 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530915 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
Sujithf1dc5602008-10-29 10:16:30 +0530916 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
917 }
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400918
Sujith7d0d0df2010-04-16 11:53:57 +0530919 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530920
Vasanthakumar Thiagarajan66860242010-04-15 17:39:07 -0400921 if (AR_SREV_9300_20_OR_LATER(ah)) {
922 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
923 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
924 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
925 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
926 }
Sujithf1dc5602008-10-29 10:16:30 +0530927}
928
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700929static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
930{
931 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
932 val = min(val, (u32) 0xFFFF);
933 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
934}
935
Lorenzo Bianconi8e15e092014-09-16 02:13:07 +0200936void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +0530937{
Felix Fietkau0005baf2010-01-15 02:33:40 +0100938 u32 val = ath9k_hw_mac_to_clks(ah, us);
939 val = min(val, (u32) 0xFFFF);
940 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
Sujithf1dc5602008-10-29 10:16:30 +0530941}
942
Lorenzo Bianconi8e15e092014-09-16 02:13:07 +0200943void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +0530944{
Felix Fietkau0005baf2010-01-15 02:33:40 +0100945 u32 val = ath9k_hw_mac_to_clks(ah, us);
946 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
947 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
948}
949
Lorenzo Bianconi8e15e092014-09-16 02:13:07 +0200950void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
Felix Fietkau0005baf2010-01-15 02:33:40 +0100951{
952 u32 val = ath9k_hw_mac_to_clks(ah, us);
953 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
954 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
Sujithf1dc5602008-10-29 10:16:30 +0530955}
956
Sujithcbe61d82009-02-09 13:27:12 +0530957static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
Sujithf1dc5602008-10-29 10:16:30 +0530958{
Sujithf1dc5602008-10-29 10:16:30 +0530959 if (tu > 0xFFFF) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800960 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
961 tu);
Sujith2660b812009-02-09 13:27:26 +0530962 ah->globaltxtimeout = (u32) -1;
Sujithf1dc5602008-10-29 10:16:30 +0530963 return false;
964 } else {
965 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
Sujith2660b812009-02-09 13:27:26 +0530966 ah->globaltxtimeout = tu;
Sujithf1dc5602008-10-29 10:16:30 +0530967 return true;
968 }
969}
970
Felix Fietkau0005baf2010-01-15 02:33:40 +0100971void ath9k_hw_init_global_settings(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530972{
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700973 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700974 const struct ath9k_channel *chan = ah->curchan;
Felix Fietkaue115b7e2012-04-19 21:18:23 +0200975 int acktimeout, ctstimeout, ack_offset = 0;
Felix Fietkaue239d852010-01-15 02:34:58 +0100976 int slottime;
Felix Fietkau0005baf2010-01-15 02:33:40 +0100977 int sifstime;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700978 int rx_lat = 0, tx_lat = 0, eifs = 0;
979 u32 reg;
Felix Fietkau0005baf2010-01-15 02:33:40 +0100980
Joe Perchesd2182b62011-12-15 14:55:53 -0800981 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
Joe Perches226afe62010-12-02 19:12:37 -0800982 ah->misc_mode);
Sujithf1dc5602008-10-29 10:16:30 +0530983
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700984 if (!chan)
985 return;
986
Sujith2660b812009-02-09 13:27:26 +0530987 if (ah->misc_mode != 0)
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100988 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
Felix Fietkau0005baf2010-01-15 02:33:40 +0100989
Rajkumar Manoharan81a91d52011-08-31 10:47:30 +0530990 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
991 rx_lat = 41;
992 else
993 rx_lat = 37;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +0700994 tx_lat = 54;
995
Felix Fietkaue88e4862012-04-19 21:18:22 +0200996 if (IS_CHAN_5GHZ(chan))
997 sifstime = 16;
998 else
999 sifstime = 10;
1000
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001001 if (IS_CHAN_HALF_RATE(chan)) {
1002 eifs = 175;
1003 rx_lat *= 2;
1004 tx_lat *= 2;
1005 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1006 tx_lat += 11;
1007
Simon Wunderlich92367fe72013-08-14 08:01:30 +02001008 sifstime = 32;
Felix Fietkaue115b7e2012-04-19 21:18:23 +02001009 ack_offset = 16;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001010 slottime = 13;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001011 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1012 eifs = 340;
Rajkumar Manoharan81a91d52011-08-31 10:47:30 +05301013 rx_lat = (rx_lat * 4) - 1;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001014 tx_lat *= 4;
1015 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1016 tx_lat += 22;
1017
Simon Wunderlich92367fe72013-08-14 08:01:30 +02001018 sifstime = 64;
Felix Fietkaue115b7e2012-04-19 21:18:23 +02001019 ack_offset = 32;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001020 slottime = 21;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001021 } else {
Rajkumar Manoharana7be0392011-08-27 12:13:21 +05301022 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1023 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1024 reg = AR_USEC_ASYNC_FIFO;
1025 } else {
1026 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1027 common->clockrate;
1028 reg = REG_READ(ah, AR_USEC);
1029 }
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001030 rx_lat = MS(reg, AR_USEC_RX_LAT);
1031 tx_lat = MS(reg, AR_USEC_TX_LAT);
1032
1033 slottime = ah->slottime;
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001034 }
Felix Fietkau0005baf2010-01-15 02:33:40 +01001035
Felix Fietkaue239d852010-01-15 02:34:58 +01001036 /* As defined by IEEE 802.11-2007 17.3.8.6 */
Mathias Kretschmerf77f8232013-04-22 22:34:41 +02001037 slottime += 3 * ah->coverage_class;
1038 acktimeout = slottime + sifstime + ack_offset;
Felix Fietkauadb50662011-08-28 01:52:10 +02001039 ctstimeout = acktimeout;
Felix Fietkau42c45682010-02-11 18:07:19 +01001040
1041 /*
1042 * Workaround for early ACK timeouts, add an offset to match the
Felix Fietkau55a2bb42012-02-05 21:15:18 +01001043 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
Felix Fietkau42c45682010-02-11 18:07:19 +01001044 * This was initially only meant to work around an issue with delayed
1045 * BA frames in some implementations, but it has been found to fix ACK
1046 * timeout issues in other cases as well.
1047 */
Felix Fietkaue4744ec2013-10-11 23:31:01 +02001048 if (IS_CHAN_2GHZ(chan) &&
Felix Fietkaue115b7e2012-04-19 21:18:23 +02001049 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
Felix Fietkau42c45682010-02-11 18:07:19 +01001050 acktimeout += 64 - sifstime - ah->slottime;
Felix Fietkau55a2bb42012-02-05 21:15:18 +01001051 ctstimeout += 48 - sifstime - ah->slottime;
1052 }
1053
Lorenzo Bianconi7aefa8a2014-09-16 02:13:11 +02001054 if (ah->dynack.enabled) {
1055 acktimeout = ah->dynack.ackto;
1056 ctstimeout = acktimeout;
1057 slottime = (acktimeout - 3) / 2;
1058 } else {
1059 ah->dynack.ackto = acktimeout;
1060 }
1061
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001062 ath9k_hw_set_sifs_time(ah, sifstime);
1063 ath9k_hw_setslottime(ah, slottime);
Felix Fietkau0005baf2010-01-15 02:33:40 +01001064 ath9k_hw_set_ack_timeout(ah, acktimeout);
Felix Fietkauadb50662011-08-28 01:52:10 +02001065 ath9k_hw_set_cts_timeout(ah, ctstimeout);
Sujith2660b812009-02-09 13:27:26 +05301066 if (ah->globaltxtimeout != (u32) -1)
1067 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
Felix Fietkaub6ba41b2011-07-09 11:12:50 +07001068
1069 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1070 REG_RMW(ah, AR_USEC,
1071 (common->clockrate - 1) |
1072 SM(rx_lat, AR_USEC_RX_LAT) |
1073 SM(tx_lat, AR_USEC_TX_LAT),
1074 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1075
Sujithf1dc5602008-10-29 10:16:30 +05301076}
Felix Fietkau0005baf2010-01-15 02:33:40 +01001077EXPORT_SYMBOL(ath9k_hw_init_global_settings);
Sujithf1dc5602008-10-29 10:16:30 +05301078
Sujith285f2dd2010-01-08 10:36:07 +05301079void ath9k_hw_deinit(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001080{
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001081 struct ath_common *common = ath9k_hw_common(ah);
1082
Sujith736b3a22010-03-17 14:25:24 +05301083 if (common->state < ATH_HW_INITIALIZED)
Felix Fietkauc1b976d2012-12-12 13:14:23 +01001084 return;
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001085
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001086 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001087}
Sujith285f2dd2010-01-08 10:36:07 +05301088EXPORT_SYMBOL(ath9k_hw_deinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001089
Sujithf1dc5602008-10-29 10:16:30 +05301090/*******/
1091/* INI */
1092/*******/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001093
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001094u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
Bob Copeland3a702e42009-03-30 22:30:29 -04001095{
1096 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1097
Felix Fietkau6b21fd22013-10-11 23:30:56 +02001098 if (IS_CHAN_2GHZ(chan))
Bob Copeland3a702e42009-03-30 22:30:29 -04001099 ctl |= CTL_11G;
1100 else
1101 ctl |= CTL_11A;
1102
1103 return ctl;
1104}
1105
Sujithf1dc5602008-10-29 10:16:30 +05301106/****************************************/
1107/* Reset and Channel Switching Routines */
1108/****************************************/
1109
Sujithcbe61d82009-02-09 13:27:12 +05301110static inline void ath9k_hw_set_dma(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301111{
Felix Fietkau57b32222010-04-15 17:39:22 -04001112 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkau86c157b2013-05-23 12:20:56 +02001113 int txbuf_size;
Sujithf1dc5602008-10-29 10:16:30 +05301114
Sujith7d0d0df2010-04-16 11:53:57 +05301115 ENABLE_REGWRITE_BUFFER(ah);
1116
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001117 /*
1118 * set AHB_MODE not to do cacheline prefetches
1119 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001120 if (!AR_SREV_9300_20_OR_LATER(ah))
1121 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
Sujithf1dc5602008-10-29 10:16:30 +05301122
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001123 /*
1124 * let mac dma reads be in 128 byte chunks
1125 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001126 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05301127
Sujith7d0d0df2010-04-16 11:53:57 +05301128 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301129
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001130 /*
1131 * Restore TX Trigger Level to its pre-reset value.
1132 * The initial value depends on whether aggregation is enabled, and is
1133 * adjusted whenever underruns are detected.
1134 */
Felix Fietkau57b32222010-04-15 17:39:22 -04001135 if (!AR_SREV_9300_20_OR_LATER(ah))
1136 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
Sujithf1dc5602008-10-29 10:16:30 +05301137
Sujith7d0d0df2010-04-16 11:53:57 +05301138 ENABLE_REGWRITE_BUFFER(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301139
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001140 /*
1141 * let mac dma writes be in 128 byte chunks
1142 */
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001143 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05301144
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001145 /*
1146 * Setup receive FIFO threshold to hold off TX activities
1147 */
Sujithf1dc5602008-10-29 10:16:30 +05301148 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1149
Felix Fietkau57b32222010-04-15 17:39:22 -04001150 if (AR_SREV_9300_20_OR_LATER(ah)) {
1151 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1152 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1153
1154 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1155 ah->caps.rx_status_len);
1156 }
1157
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001158 /*
1159 * reduce the number of usable entries in PCU TXBUF to avoid
1160 * wrap around issues.
1161 */
Sujithf1dc5602008-10-29 10:16:30 +05301162 if (AR_SREV_9285(ah)) {
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001163 /* For AR9285 the number of Fifos are reduced to half.
1164 * So set the usable tx buf size also to half to
1165 * avoid data/delimiter underruns
1166 */
Felix Fietkau86c157b2013-05-23 12:20:56 +02001167 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1168 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1169 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1170 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1171 } else {
1172 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
Sujithf1dc5602008-10-29 10:16:30 +05301173 }
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -04001174
Felix Fietkau86c157b2013-05-23 12:20:56 +02001175 if (!AR_SREV_9271(ah))
1176 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1177
Sujith7d0d0df2010-04-16 11:53:57 +05301178 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301179
Vasanthakumar Thiagarajan744d4022010-04-15 17:39:27 -04001180 if (AR_SREV_9300_20_OR_LATER(ah))
1181 ath9k_hw_reset_txstatus_ring(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301182}
1183
Sujithcbe61d82009-02-09 13:27:12 +05301184static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
Sujithf1dc5602008-10-29 10:16:30 +05301185{
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001186 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1187 u32 set = AR_STA_ID1_KSRCH_MODE;
Sujithf1dc5602008-10-29 10:16:30 +05301188
Sujithf1dc5602008-10-29 10:16:30 +05301189 switch (opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08001190 case NL80211_IFTYPE_ADHOC:
Felix Fietkau83322eb2014-09-27 22:49:44 +02001191 if (!AR_SREV_9340_13(ah)) {
1192 set |= AR_STA_ID1_ADHOC;
1193 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1194 break;
1195 }
1196 /* fall through */
Thomas Pedersen2664d662013-05-08 10:16:48 -07001197 case NL80211_IFTYPE_MESH_POINT:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001198 case NL80211_IFTYPE_AP:
1199 set |= AR_STA_ID1_STA_AP;
1200 /* fall through */
Colin McCabed97809d2008-12-01 13:38:55 -08001201 case NL80211_IFTYPE_STATION:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001202 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
Sujithf1dc5602008-10-29 10:16:30 +05301203 break;
Rajkumar Manoharan5f841b42010-10-27 18:31:15 +05301204 default:
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001205 if (!ah->is_monitoring)
1206 set = 0;
Rajkumar Manoharan5f841b42010-10-27 18:31:15 +05301207 break;
Sujithf1dc5602008-10-29 10:16:30 +05301208 }
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001209 REG_RMW(ah, AR_STA_ID1, set, mask);
Sujithf1dc5602008-10-29 10:16:30 +05301210}
1211
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001212void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1213 u32 *coef_mantissa, u32 *coef_exponent)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001214{
1215 u32 coef_exp, coef_man;
1216
1217 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1218 if ((coef_scaled >> coef_exp) & 0x1)
1219 break;
1220
1221 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1222
1223 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1224
1225 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1226 *coef_exponent = coef_exp - 16;
1227}
1228
Sujith Manoharand7df7a52013-12-18 09:53:27 +05301229/* AR9330 WAR:
1230 * call external reset function to reset WMAC if:
1231 * - doing a cold reset
1232 * - we have pending frames in the TX queues.
1233 */
1234static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1235{
1236 int i, npend = 0;
1237
1238 for (i = 0; i < AR_NUM_QCU; i++) {
1239 npend = ath9k_hw_numtxpending(ah, i);
1240 if (npend)
1241 break;
1242 }
1243
1244 if (ah->external_reset &&
1245 (npend || type == ATH9K_RESET_COLD)) {
1246 int reset_err = 0;
1247
1248 ath_dbg(ath9k_hw_common(ah), RESET,
1249 "reset MAC via external reset\n");
1250
1251 reset_err = ah->external_reset();
1252 if (reset_err) {
1253 ath_err(ath9k_hw_common(ah),
1254 "External reset failed, err=%d\n",
1255 reset_err);
1256 return false;
1257 }
1258
1259 REG_WRITE(ah, AR_RTC_RESET, 1);
1260 }
1261
1262 return true;
1263}
1264
Sujithcbe61d82009-02-09 13:27:12 +05301265static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
Sujithf1dc5602008-10-29 10:16:30 +05301266{
1267 u32 rst_flags;
1268 u32 tmpReg;
1269
Sujith70768492009-02-16 13:23:12 +05301270 if (AR_SREV_9100(ah)) {
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001271 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1272 AR_RTC_DERIVED_CLK_PERIOD, 1);
Sujith70768492009-02-16 13:23:12 +05301273 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1274 }
1275
Sujith7d0d0df2010-04-16 11:53:57 +05301276 ENABLE_REGWRITE_BUFFER(ah);
1277
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001278 if (AR_SREV_9300_20_OR_LATER(ah)) {
1279 REG_WRITE(ah, AR_WA, ah->WARegVal);
1280 udelay(10);
1281 }
1282
Sujithf1dc5602008-10-29 10:16:30 +05301283 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1284 AR_RTC_FORCE_WAKE_ON_INT);
1285
1286 if (AR_SREV_9100(ah)) {
1287 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1288 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1289 } else {
1290 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
Felix Fietkaua37a9912013-05-23 12:20:55 +02001291 if (AR_SREV_9340(ah))
1292 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1293 else
1294 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1295 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1296
1297 if (tmpReg) {
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001298 u32 val;
Sujithf1dc5602008-10-29 10:16:30 +05301299 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001300
1301 val = AR_RC_HOSTIF;
1302 if (!AR_SREV_9300_20_OR_LATER(ah))
1303 val |= AR_RC_AHB;
1304 REG_WRITE(ah, AR_RC, val);
1305
1306 } else if (!AR_SREV_9300_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05301307 REG_WRITE(ah, AR_RC, AR_RC_AHB);
Sujithf1dc5602008-10-29 10:16:30 +05301308
1309 rst_flags = AR_RTC_RC_MAC_WARM;
1310 if (type == ATH9K_RESET_COLD)
1311 rst_flags |= AR_RTC_RC_MAC_COLD;
1312 }
1313
Gabor Juhos7d95847c2011-06-21 11:23:51 +02001314 if (AR_SREV_9330(ah)) {
Sujith Manoharand7df7a52013-12-18 09:53:27 +05301315 if (!ath9k_hw_ar9330_reset_war(ah, type))
1316 return false;
Gabor Juhos7d95847c2011-06-21 11:23:51 +02001317 }
1318
Rajkumar Manoharan38634952012-06-11 12:19:32 +05301319 if (ath9k_hw_mci_is_enabled(ah))
Rajkumar Manoharan506847a2012-06-12 20:18:16 +05301320 ar9003_mci_check_gpm_offset(ah);
Rajkumar Manoharan38634952012-06-11 12:19:32 +05301321
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001322 REG_WRITE(ah, AR_RTC_RC, rst_flags);
Sujith7d0d0df2010-04-16 11:53:57 +05301323
1324 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301325
Sujith Manoharan4dc78c432013-12-18 09:53:26 +05301326 if (AR_SREV_9300_20_OR_LATER(ah))
1327 udelay(50);
1328 else if (AR_SREV_9100(ah))
Sujith Manoharan3683a072014-02-04 08:37:52 +05301329 mdelay(10);
Sujith Manoharan4dc78c432013-12-18 09:53:26 +05301330 else
1331 udelay(100);
Sujithf1dc5602008-10-29 10:16:30 +05301332
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001333 REG_WRITE(ah, AR_RTC_RC, 0);
Sujith0caa7b12009-02-16 13:23:20 +05301334 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001335 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
Sujithf1dc5602008-10-29 10:16:30 +05301336 return false;
1337 }
1338
1339 if (!AR_SREV_9100(ah))
1340 REG_WRITE(ah, AR_RC, 0);
1341
Sujithf1dc5602008-10-29 10:16:30 +05301342 if (AR_SREV_9100(ah))
1343 udelay(50);
1344
1345 return true;
1346}
1347
Sujithcbe61d82009-02-09 13:27:12 +05301348static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301349{
Sujith7d0d0df2010-04-16 11:53:57 +05301350 ENABLE_REGWRITE_BUFFER(ah);
1351
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001352 if (AR_SREV_9300_20_OR_LATER(ah)) {
1353 REG_WRITE(ah, AR_WA, ah->WARegVal);
1354 udelay(10);
1355 }
1356
Sujithf1dc5602008-10-29 10:16:30 +05301357 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1358 AR_RTC_FORCE_WAKE_ON_INT);
1359
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001360 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301361 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1362
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001363 REG_WRITE(ah, AR_RTC_RESET, 0);
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301364
Sujith7d0d0df2010-04-16 11:53:57 +05301365 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301366
Sujith Manoharanafe36532013-12-18 09:53:25 +05301367 udelay(2);
Senthil Balasubramanian84e21692010-04-15 17:38:30 -04001368
1369 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301370 REG_WRITE(ah, AR_RC, 0);
1371
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001372 REG_WRITE(ah, AR_RTC_RESET, 1);
Sujithf1dc5602008-10-29 10:16:30 +05301373
1374 if (!ath9k_hw_wait(ah,
1375 AR_RTC_STATUS,
1376 AR_RTC_STATUS_M,
Sujith0caa7b12009-02-16 13:23:20 +05301377 AR_RTC_STATUS_ON,
1378 AH_WAIT_TIMEOUT)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001379 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
Sujithf1dc5602008-10-29 10:16:30 +05301380 return false;
1381 }
1382
Sujithf1dc5602008-10-29 10:16:30 +05301383 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1384}
1385
Sujithcbe61d82009-02-09 13:27:12 +05301386static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Sujithf1dc5602008-10-29 10:16:30 +05301387{
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301388 bool ret = false;
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301389
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04001390 if (AR_SREV_9300_20_OR_LATER(ah)) {
1391 REG_WRITE(ah, AR_WA, ah->WARegVal);
1392 udelay(10);
1393 }
1394
Sujithf1dc5602008-10-29 10:16:30 +05301395 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1396 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1397
Felix Fietkauceb26a62012-10-03 21:07:51 +02001398 if (!ah->reset_power_on)
1399 type = ATH9K_RESET_POWER_ON;
1400
Sujithf1dc5602008-10-29 10:16:30 +05301401 switch (type) {
1402 case ATH9K_RESET_POWER_ON:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301403 ret = ath9k_hw_set_reset_power_on(ah);
Sujith Manoharanda8fb122012-11-17 21:20:50 +05301404 if (ret)
Felix Fietkauceb26a62012-10-03 21:07:51 +02001405 ah->reset_power_on = true;
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301406 break;
Sujithf1dc5602008-10-29 10:16:30 +05301407 case ATH9K_RESET_WARM:
1408 case ATH9K_RESET_COLD:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301409 ret = ath9k_hw_set_reset(ah, type);
1410 break;
Sujithf1dc5602008-10-29 10:16:30 +05301411 default:
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301412 break;
Sujithf1dc5602008-10-29 10:16:30 +05301413 }
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301414
Mohammed Shafi Shajakhan7a9233f2011-11-30 10:41:25 +05301415 return ret;
Sujithf1dc5602008-10-29 10:16:30 +05301416}
1417
Sujithcbe61d82009-02-09 13:27:12 +05301418static bool ath9k_hw_chip_reset(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05301419 struct ath9k_channel *chan)
1420{
Felix Fietkau9c083af2012-03-03 15:17:02 +01001421 int reset_type = ATH9K_RESET_WARM;
1422
1423 if (AR_SREV_9280(ah)) {
1424 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1425 reset_type = ATH9K_RESET_POWER_ON;
1426 else
1427 reset_type = ATH9K_RESET_COLD;
Felix Fietkau3412f2f02013-02-25 20:51:07 +01001428 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1429 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1430 reset_type = ATH9K_RESET_COLD;
Felix Fietkau9c083af2012-03-03 15:17:02 +01001431
1432 if (!ath9k_hw_set_reset_reg(ah, reset_type))
Sujithf1dc5602008-10-29 10:16:30 +05301433 return false;
1434
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001435 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05301436 return false;
1437
Sujith2660b812009-02-09 13:27:26 +05301438 ah->chip_fullsleep = false;
Felix Fietkaubfc441a2012-05-24 14:32:22 +02001439
1440 if (AR_SREV_9330(ah))
1441 ar9003_hw_internal_regulator_apply(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301442 ath9k_hw_init_pll(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301443
1444 return true;
1445}
1446
Sujithcbe61d82009-02-09 13:27:12 +05301447static bool ath9k_hw_channel_change(struct ath_hw *ah,
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001448 struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05301449{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001450 struct ath_common *common = ath9k_hw_common(ah);
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301451 struct ath9k_hw_capabilities *pCap = &ah->caps;
1452 bool band_switch = false, mode_diff = false;
Sujith Manoharan70e89a72013-07-16 12:03:22 +05301453 u8 ini_reloaded = 0;
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001454 u32 qnum;
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001455 int r;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301456
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301457 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
Felix Fietkauaf02efb2013-11-18 20:14:44 +01001458 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1459 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1460 mode_diff = !!(flags_diff & ~CHANNEL_HT);
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301461 }
Sujithf1dc5602008-10-29 10:16:30 +05301462
1463 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1464 if (ath9k_hw_numtxpending(ah, qnum)) {
Joe Perchesd2182b62011-12-15 14:55:53 -08001465 ath_dbg(common, QUEUE,
Joe Perches226afe62010-12-02 19:12:37 -08001466 "Transmit frames pending on queue %d\n", qnum);
Sujithf1dc5602008-10-29 10:16:30 +05301467 return false;
1468 }
1469 }
1470
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001471 if (!ath9k_hw_rfbus_req(ah)) {
Joe Perches38002762010-12-02 19:12:36 -08001472 ath_err(common, "Could not kill baseband RX\n");
Sujithf1dc5602008-10-29 10:16:30 +05301473 return false;
1474 }
1475
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301476 if (band_switch || mode_diff) {
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301477 ath9k_hw_mark_phy_inactive(ah);
1478 udelay(5);
1479
Sujith Manoharan5f35c0f2013-07-16 12:03:20 +05301480 if (band_switch)
1481 ath9k_hw_init_pll(ah, chan);
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301482
1483 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1484 ath_err(common, "Failed to do fast channel change\n");
1485 return false;
1486 }
1487 }
1488
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001489 ath9k_hw_set_channel_regs(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301490
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001491 r = ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001492 if (r) {
Joe Perches38002762010-12-02 19:12:36 -08001493 ath_err(common, "Failed to set channel\n");
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001494 return false;
Sujithf1dc5602008-10-29 10:16:30 +05301495 }
Felix Fietkaudfdac8a2010-10-08 22:13:51 +02001496 ath9k_hw_set_clockrate(ah);
Gabor Juhos64ea57d2012-04-15 20:38:05 +02001497 ath9k_hw_apply_txpower(ah, chan, false);
Sujithf1dc5602008-10-29 10:16:30 +05301498
Felix Fietkau81c507a2013-10-11 23:30:55 +02001499 ath9k_hw_set_delta_slope(ah, chan);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001500 ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301501
Sujith Manoharan70e89a72013-07-16 12:03:22 +05301502 if (band_switch || ini_reloaded)
1503 ah->eep_ops->set_board_values(ah, chan);
1504
1505 ath9k_hw_init_bb(ah, chan);
1506 ath9k_hw_rfbus_done(ah);
1507
1508 if (band_switch || ini_reloaded) {
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301509 ah->ah_flags |= AH_FASTCC;
Sujith Manoharan70e89a72013-07-16 12:03:22 +05301510 ath9k_hw_init_cal(ah, chan);
Rajkumar Manoharana126ff52011-10-13 11:00:42 +05301511 ah->ah_flags &= ~AH_FASTCC;
Rajkumar Manoharan5f0c04e2011-10-13 11:00:35 +05301512 }
1513
Sujithf1dc5602008-10-29 10:16:30 +05301514 return true;
1515}
1516
Felix Fietkau691680b2011-03-19 13:55:38 +01001517static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1518{
1519 u32 gpio_mask = ah->gpio_mask;
1520 int i;
1521
1522 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1523 if (!(gpio_mask & 1))
1524 continue;
1525
1526 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1527 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1528 }
1529}
1530
Sujith Manoharan1e516ca2013-09-11 21:30:27 +05301531void ath9k_hw_check_nav(struct ath_hw *ah)
1532{
1533 struct ath_common *common = ath9k_hw_common(ah);
1534 u32 val;
1535
1536 val = REG_READ(ah, AR_NAV);
1537 if (val != 0xdeadbeef && val > 0x7fff) {
1538 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1539 REG_WRITE(ah, AR_NAV, 0);
1540 }
1541}
1542EXPORT_SYMBOL(ath9k_hw_check_nav);
1543
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001544bool ath9k_hw_check_alive(struct ath_hw *ah)
Johannes Berg3b319aa2009-06-13 14:50:26 +05301545{
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001546 int count = 50;
Felix Fietkaud31a36a2014-02-24 22:26:05 +01001547 u32 reg, last_val;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301548
Rajkumar Manoharan01e18912012-03-15 05:34:27 +05301549 if (AR_SREV_9300(ah))
1550 return !ath9k_hw_detect_mac_hang(ah);
1551
Felix Fietkaue17f83e2010-09-22 12:34:53 +02001552 if (AR_SREV_9285_12_OR_LATER(ah))
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001553 return true;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301554
Felix Fietkaud31a36a2014-02-24 22:26:05 +01001555 last_val = REG_READ(ah, AR_OBS_BUS_1);
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001556 do {
1557 reg = REG_READ(ah, AR_OBS_BUS_1);
Felix Fietkaud31a36a2014-02-24 22:26:05 +01001558 if (reg != last_val)
1559 return true;
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001560
Felix Fietkau105ff412014-03-09 09:51:16 +01001561 udelay(1);
Felix Fietkaud31a36a2014-02-24 22:26:05 +01001562 last_val = reg;
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001563 if ((reg & 0x7E7FFFEF) == 0x00702400)
1564 continue;
1565
1566 switch (reg & 0x7E000B00) {
1567 case 0x1E000000:
1568 case 0x52000B00:
1569 case 0x18000B00:
1570 continue;
1571 default:
1572 return true;
1573 }
1574 } while (count-- > 0);
1575
1576 return false;
Johannes Berg3b319aa2009-06-13 14:50:26 +05301577}
Felix Fietkauc9c99e52010-04-19 19:57:29 +02001578EXPORT_SYMBOL(ath9k_hw_check_alive);
Johannes Berg3b319aa2009-06-13 14:50:26 +05301579
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301580static void ath9k_hw_init_mfp(struct ath_hw *ah)
1581{
1582 /* Setup MFP options for CCMP */
1583 if (AR_SREV_9280_20_OR_LATER(ah)) {
1584 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1585 * frames when constructing CCMP AAD. */
1586 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1587 0xc7ff);
Chun-Yeow Yeoh60fc4962014-11-16 03:05:41 +08001588 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1589 ah->sw_mgmt_crypto_tx = true;
1590 else
1591 ah->sw_mgmt_crypto_tx = false;
Chun-Yeow Yeohe6510b12014-11-16 03:05:40 +08001592 ah->sw_mgmt_crypto_rx = false;
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301593 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1594 /* Disable hardware crypto for management frames */
1595 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1596 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1597 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1598 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
Chun-Yeow Yeohe6510b12014-11-16 03:05:40 +08001599 ah->sw_mgmt_crypto_tx = true;
1600 ah->sw_mgmt_crypto_rx = true;
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301601 } else {
Chun-Yeow Yeohe6510b12014-11-16 03:05:40 +08001602 ah->sw_mgmt_crypto_tx = true;
1603 ah->sw_mgmt_crypto_rx = true;
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301604 }
1605}
1606
1607static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1608 u32 macStaId1, u32 saveDefAntenna)
1609{
1610 struct ath_common *common = ath9k_hw_common(ah);
1611
1612 ENABLE_REGWRITE_BUFFER(ah);
1613
Felix Fietkauecbbed32013-04-16 12:51:56 +02001614 REG_RMW(ah, AR_STA_ID1, macStaId1
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301615 | AR_STA_ID1_RTS_USE_DEF
Felix Fietkauecbbed32013-04-16 12:51:56 +02001616 | ah->sta_id1_defaults,
1617 ~AR_STA_ID1_SADH_MASK);
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301618 ath_hw_setbssidmask(common);
1619 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1620 ath9k_hw_write_associd(ah);
1621 REG_WRITE(ah, AR_ISR, ~0);
1622 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1623
1624 REGWRITE_BUFFER_FLUSH(ah);
1625
1626 ath9k_hw_set_operating_mode(ah, ah->opmode);
1627}
1628
1629static void ath9k_hw_init_queues(struct ath_hw *ah)
1630{
1631 int i;
1632
1633 ENABLE_REGWRITE_BUFFER(ah);
1634
1635 for (i = 0; i < AR_NUM_DCU; i++)
1636 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1637
1638 REGWRITE_BUFFER_FLUSH(ah);
1639
1640 ah->intr_txqs = 0;
1641 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1642 ath9k_hw_resettxqueue(ah, i);
1643}
1644
1645/*
1646 * For big endian systems turn on swapping for descriptors
1647 */
1648static void ath9k_hw_init_desc(struct ath_hw *ah)
1649{
1650 struct ath_common *common = ath9k_hw_common(ah);
1651
1652 if (AR_SREV_9100(ah)) {
1653 u32 mask;
1654 mask = REG_READ(ah, AR_CFG);
1655 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1656 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1657 mask);
1658 } else {
1659 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1660 REG_WRITE(ah, AR_CFG, mask);
1661 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1662 REG_READ(ah, AR_CFG));
1663 }
1664 } else {
1665 if (common->bus_ops->ath_bus_type == ATH_USB) {
1666 /* Configure AR9271 target WLAN */
1667 if (AR_SREV_9271(ah))
1668 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1669 else
1670 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1671 }
1672#ifdef __BIG_ENDIAN
1673 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
Sujith Manoharan2c323052013-12-31 08:12:02 +05301674 AR_SREV_9550(ah) || AR_SREV_9531(ah))
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301675 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1676 else
1677 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1678#endif
1679 }
1680}
1681
Sujith Manoharancaed6572012-03-14 14:40:46 +05301682/*
1683 * Fast channel change:
1684 * (Change synthesizer based on channel freq without resetting chip)
Sujith Manoharancaed6572012-03-14 14:40:46 +05301685 */
1686static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1687{
1688 struct ath_common *common = ath9k_hw_common(ah);
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301689 struct ath9k_hw_capabilities *pCap = &ah->caps;
Sujith Manoharancaed6572012-03-14 14:40:46 +05301690 int ret;
1691
1692 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1693 goto fail;
1694
1695 if (ah->chip_fullsleep)
1696 goto fail;
1697
1698 if (!ah->curchan)
1699 goto fail;
1700
1701 if (chan->channel == ah->curchan->channel)
1702 goto fail;
1703
Felix Fietkaufeb7bc92012-04-19 21:18:28 +02001704 if ((ah->curchan->channelFlags | chan->channelFlags) &
1705 (CHANNEL_HALF | CHANNEL_QUARTER))
1706 goto fail;
1707
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301708 /*
Felix Fietkau6b21fd22013-10-11 23:30:56 +02001709 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
Sujith Manoharanb840cff2013-07-16 12:03:19 +05301710 */
Felix Fietkau6b21fd22013-10-11 23:30:56 +02001711 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
Felix Fietkauaf02efb2013-11-18 20:14:44 +01001712 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
Felix Fietkau6b21fd22013-10-11 23:30:56 +02001713 goto fail;
Sujith Manoharancaed6572012-03-14 14:40:46 +05301714
1715 if (!ath9k_hw_check_alive(ah))
1716 goto fail;
1717
1718 /*
1719 * For AR9462, make sure that calibration data for
1720 * re-using are present.
1721 */
Sujith Manoharan8a90555f2012-05-04 13:23:59 +05301722 if (AR_SREV_9462(ah) && (ah->caldata &&
Sujith Manoharan4b9b42b2013-09-11 16:36:31 +05301723 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1724 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1725 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
Sujith Manoharancaed6572012-03-14 14:40:46 +05301726 goto fail;
1727
1728 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1729 ah->curchan->channel, chan->channel);
1730
1731 ret = ath9k_hw_channel_change(ah, chan);
1732 if (!ret)
1733 goto fail;
1734
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301735 if (ath9k_hw_mci_is_enabled(ah))
Rajkumar Manoharan1bde95fa2012-06-11 12:19:33 +05301736 ar9003_mci_2g5g_switch(ah, false);
Sujith Manoharancaed6572012-03-14 14:40:46 +05301737
Rajkumar Manoharan88033312012-09-12 18:59:19 +05301738 ath9k_hw_loadnf(ah, ah->curchan);
1739 ath9k_hw_start_nfcal(ah, true);
1740
Sujith Manoharancaed6572012-03-14 14:40:46 +05301741 if (AR_SREV_9271(ah))
1742 ar9002_hw_load_ani_reg(ah, chan);
1743
1744 return 0;
1745fail:
1746 return -EINVAL;
1747}
1748
Felix Fietkau8d7e09d2014-06-11 16:18:01 +05301749u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1750{
1751 struct timespec ts;
1752 s64 usec;
1753
1754 if (!cur) {
1755 getrawmonotonic(&ts);
1756 cur = &ts;
1757 }
1758
1759 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1760 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1761
1762 return (u32) usec;
1763}
1764EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1765
Sujithcbe61d82009-02-09 13:27:12 +05301766int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
Sujith Manoharancaed6572012-03-14 14:40:46 +05301767 struct ath9k_hw_cal_data *caldata, bool fastcc)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001768{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07001769 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001770 u32 saveLedState;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001771 u32 saveDefAntenna;
1772 u32 macStaId1;
Sujith46fe7822009-09-17 09:25:25 +05301773 u64 tsf = 0;
Felix Fietkau09d8e312013-11-18 20:14:43 +01001774 s64 usec = 0;
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301775 int r;
Sujith Manoharancaed6572012-03-14 14:40:46 +05301776 bool start_mci_reset = false;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301777 bool save_fullsleep = ah->chip_fullsleep;
1778
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301779 if (ath9k_hw_mci_is_enabled(ah)) {
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301780 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1781 if (start_mci_reset)
1782 return 0;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301783 }
1784
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001785 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001786 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001787
Sujith Manoharancaed6572012-03-14 14:40:46 +05301788 if (ah->curchan && !ah->chip_fullsleep)
1789 ath9k_hw_getnf(ah, ah->curchan);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001790
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001791 ah->caldata = caldata;
Sujith Manoharanfcb9a3d2013-03-04 12:42:52 +05301792 if (caldata && (chan->channel != caldata->channel ||
Felix Fietkau6b21fd22013-10-11 23:30:56 +02001793 chan->channelFlags != caldata->channelFlags)) {
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001794 /* Operating channel changed, reset channel calibration data */
1795 memset(caldata, 0, sizeof(*caldata));
1796 ath9k_init_nfcal_hist_buffer(ah, chan);
Felix Fietkau51dea9b2012-08-27 17:00:07 +02001797 } else if (caldata) {
Sujith Manoharan4b9b42b2013-09-11 16:36:31 +05301798 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001799 }
Lorenzo Bianconi5bc225a2013-10-11 14:09:54 +02001800 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
Felix Fietkau20bd2a02010-07-31 00:12:00 +02001801
Sujith Manoharancaed6572012-03-14 14:40:46 +05301802 if (fastcc) {
1803 r = ath9k_hw_do_fastcc(ah, chan);
1804 if (!r)
1805 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001806 }
1807
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301808 if (ath9k_hw_mci_is_enabled(ah))
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301809 ar9003_mci_stop_bt(ah, save_fullsleep);
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301810
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001811 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1812 if (saveDefAntenna == 0)
1813 saveDefAntenna = 1;
1814
1815 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1816
Felix Fietkau09d8e312013-11-18 20:14:43 +01001817 /* Save TSF before chip reset, a cold reset clears it */
1818 tsf = ath9k_hw_gettsf64(ah);
Thomas Gleixner6438e0d2014-07-16 21:05:09 +00001819 usec = ktime_to_us(ktime_get_raw());
Sujith46fe7822009-09-17 09:25:25 +05301820
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001821 saveLedState = REG_READ(ah, AR_CFG_LED) &
1822 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1823 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1824
1825 ath9k_hw_mark_phy_inactive(ah);
1826
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -08001827 ah->paprd_table_write_done = false;
1828
Sujith05020d22010-03-17 14:25:23 +05301829 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001830 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1831 REG_WRITE(ah,
1832 AR9271_RESET_POWER_DOWN_CONTROL,
1833 AR9271_RADIO_RF_RST);
1834 udelay(50);
1835 }
1836
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001837 if (!ath9k_hw_chip_reset(ah, chan)) {
Joe Perches38002762010-12-02 19:12:36 -08001838 ath_err(common, "Chip reset failed\n");
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001839 return -EINVAL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001840 }
1841
Sujith05020d22010-03-17 14:25:23 +05301842 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001843 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1844 ah->htc_reset_init = false;
1845 REG_WRITE(ah,
1846 AR9271_RESET_POWER_DOWN_CONTROL,
1847 AR9271_GATE_MAC_CTL);
1848 udelay(50);
1849 }
1850
Sujith46fe7822009-09-17 09:25:25 +05301851 /* Restore TSF */
Thomas Gleixner6438e0d2014-07-16 21:05:09 +00001852 usec = ktime_to_us(ktime_get_raw()) - usec;
Felix Fietkau09d8e312013-11-18 20:14:43 +01001853 ath9k_hw_settsf64(ah, tsf + usec);
Sujith46fe7822009-09-17 09:25:25 +05301854
Felix Fietkau7a370812010-09-22 12:34:52 +02001855 if (AR_SREV_9280_20_OR_LATER(ah))
Vasanthakumar Thiagarajan369391d2009-01-21 19:24:13 +05301856 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001857
Sujithe9141f72010-06-01 15:14:10 +05301858 if (!AR_SREV_9300_20_OR_LATER(ah))
1859 ar9002_hw_enable_async_fifo(ah);
1860
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001861 r = ath9k_hw_process_ini(ah, chan);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001862 if (r)
1863 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001864
Lorenzo Bianconi935d00c2013-12-12 18:10:16 +01001865 ath9k_hw_set_rfmode(ah, chan);
1866
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301867 if (ath9k_hw_mci_is_enabled(ah))
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301868 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1869
Felix Fietkauf860d522010-06-30 02:07:48 +02001870 /*
1871 * Some AR91xx SoC devices frequently fail to accept TSF writes
1872 * right after the chip reset. When that happens, write a new
1873 * value after the initvals have been applied, with an offset
1874 * based on measured time difference
1875 */
1876 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1877 tsf += 1500;
1878 ath9k_hw_settsf64(ah, tsf);
1879 }
1880
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301881 ath9k_hw_init_mfp(ah);
Jouni Malinen0ced0e12009-01-08 13:32:13 +02001882
Felix Fietkau81c507a2013-10-11 23:30:55 +02001883 ath9k_hw_set_delta_slope(ah, chan);
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001884 ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithd6509152009-03-13 08:56:05 +05301885 ah->eep_ops->set_board_values(ah, chan);
Luis R. Rodrigueza7765822009-10-19 02:33:45 -04001886
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301887 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
Sujith Manoharan00e00032011-01-26 21:59:05 +05301888
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001889 r = ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001890 if (r)
1891 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001892
Felix Fietkaudfdac8a2010-10-08 22:13:51 +02001893 ath9k_hw_set_clockrate(ah);
1894
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301895 ath9k_hw_init_queues(ah);
Sujith2660b812009-02-09 13:27:26 +05301896 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
Luis R. Rodrigueze36b27a2010-06-12 00:33:45 -04001897 ath9k_hw_ani_cache_ini_regs(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001898 ath9k_hw_init_qos(ah);
1899
Sujith2660b812009-02-09 13:27:26 +05301900 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Felix Fietkau55821322010-12-17 00:57:01 +01001901 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
Johannes Berg3b319aa2009-06-13 14:50:26 +05301902
Felix Fietkau0005baf2010-01-15 02:33:40 +01001903 ath9k_hw_init_global_settings(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001904
Felix Fietkaufe2b6af2011-07-09 11:12:51 +07001905 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1906 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1907 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1908 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1909 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1910 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1911 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301912 }
1913
Felix Fietkauca7a4de2011-03-23 20:57:26 +01001914 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001915
1916 ath9k_hw_set_dma(ah);
1917
Rajkumar Manoharaned6ebd82012-06-11 12:19:34 +05301918 if (!ath9k_hw_mci_is_enabled(ah))
1919 REG_WRITE(ah, AR_OBS, 8);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001920
Sujith0ce024c2009-12-14 14:57:00 +05301921 if (ah->config.rx_intr_mitigation) {
Sujith Manoharana64e1a42014-01-23 08:20:30 +05301922 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1923 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001924 }
1925
Vasanthakumar Thiagarajan7f62a132010-04-15 17:39:19 -04001926 if (ah->config.tx_intr_mitigation) {
1927 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1928 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1929 }
1930
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001931 ath9k_hw_init_bb(ah, chan);
1932
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +05301933 if (caldata) {
Sujith Manoharan4b9b42b2013-09-11 16:36:31 +05301934 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1935 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
Rajkumar Manoharan77a5a662011-10-13 11:00:37 +05301936 }
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001937 if (!ath9k_hw_init_cal(ah, chan))
Joe Perches6badaaf2009-06-28 09:26:32 -07001938 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001939
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301940 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301941 return -EIO;
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301942
Sujith7d0d0df2010-04-16 11:53:57 +05301943 ENABLE_REGWRITE_BUFFER(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001944
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -04001945 ath9k_hw_restore_chainmask(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001946 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1947
Sujith7d0d0df2010-04-16 11:53:57 +05301948 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05301949
Sujith Manoharanf4c34af2014-11-16 06:11:03 +05301950 ath9k_hw_gen_timer_start_tsf2(ah);
1951
Sujith Manoharan15d2b582013-03-04 12:42:53 +05301952 ath9k_hw_init_desc(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001953
Sujith Manoharandbccdd12012-02-22 17:55:47 +05301954 if (ath9k_hw_btcoex_is_enabled(ah))
Vasanthakumar Thiagarajan42cc41e2009-08-26 21:08:45 +05301955 ath9k_hw_btcoex_enable(ah);
1956
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05301957 if (ath9k_hw_mci_is_enabled(ah))
Sujith Manoharan528e5d32012-02-22 12:41:12 +05301958 ar9003_mci_check_bt(ah);
Mohammed Shafi Shajakhan63d32962011-11-30 10:41:27 +05301959
Felix Fietkau7b89fcc2014-10-25 17:19:32 +02001960 if (AR_SREV_9300_20_OR_LATER(ah)) {
1961 ath9k_hw_loadnf(ah, chan);
1962 ath9k_hw_start_nfcal(ah, true);
1963 }
Rajkumar Manoharan1fe860ed2012-07-01 19:53:51 +05301964
Sujith Manoharana7abaf72013-12-24 10:44:21 +05301965 if (AR_SREV_9300_20_OR_LATER(ah))
Luis R. Rodriguezaea702b2010-05-13 13:33:43 -04001966 ar9003_hw_bb_watchdog_config(ah);
Sujith Manoharana7abaf72013-12-24 10:44:21 +05301967
1968 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
Rajkumar Manoharan51ac8cb2011-05-20 17:52:13 +05301969 ar9003_hw_disable_phy_restart(ah);
Rajkumar Manoharan51ac8cb2011-05-20 17:52:13 +05301970
Felix Fietkau691680b2011-03-19 13:55:38 +01001971 ath9k_hw_apply_gpio_override(ah);
1972
Sujith Manoharan7bdea962013-08-04 14:22:00 +05301973 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
Sujith Manoharan362cd032012-09-16 08:06:36 +05301974 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
1975
Lorenzo Bianconi4307b0f2014-09-11 23:50:54 +02001976 if (ah->hw->conf.radar_enabled) {
1977 /* set HW specific DFS configuration */
Lorenzo Bianconi7a0a2602014-09-16 16:43:42 +02001978 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
Lorenzo Bianconi4307b0f2014-09-11 23:50:54 +02001979 ath9k_hw_set_radar_params(ah);
1980 }
1981
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001982 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001983}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04001984EXPORT_SYMBOL(ath9k_hw_reset);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001985
Sujithf1dc5602008-10-29 10:16:30 +05301986/******************************/
1987/* Power Management (Chipset) */
1988/******************************/
1989
Luis R. Rodriguez42d5bc32010-04-15 17:38:12 -04001990/*
1991 * Notify Power Mgt is disabled in self-generated frames.
1992 * If requested, force chip to sleep.
1993 */
Sujith Manoharan31604cf2012-06-04 16:27:36 +05301994static void ath9k_set_power_sleep(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301995{
1996 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05301997
Sujith Manoharana4a29542012-09-10 09:20:03 +05301998 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
Rajkumar Manoharan153dccd2012-06-04 16:28:47 +05301999 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2000 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2001 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302002 /* xxx Required for WLAN only case ? */
2003 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2004 udelay(100);
2005 }
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302006
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302007 /*
2008 * Clear the RTC force wake bit to allow the
2009 * mac to go to sleep.
2010 */
2011 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302012
Rajkumar Manoharan153dccd2012-06-04 16:28:47 +05302013 if (ath9k_hw_mci_is_enabled(ah))
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302014 udelay(100);
Sujithf1dc5602008-10-29 10:16:30 +05302015
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302016 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2017 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2018
2019 /* Shutdown chip. Active low */
2020 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2021 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2022 udelay(2);
Sujithf1dc5602008-10-29 10:16:30 +05302023 }
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04002024
2025 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
Rafael J. Wysockia7322812011-11-26 23:37:43 +01002026 if (AR_SREV_9300_20_OR_LATER(ah))
2027 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002028}
2029
Luis R. Rodriguezbbd79af2010-04-15 17:38:16 -04002030/*
2031 * Notify Power Management is enabled in self-generating
2032 * frames. If request, set power mode of chip to
2033 * auto/normal. Duration in units of 128us (1/8 TU).
2034 */
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302035static void ath9k_set_power_network_sleep(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002036{
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302037 struct ath9k_hw_capabilities *pCap = &ah->caps;
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302038
Sujithf1dc5602008-10-29 10:16:30 +05302039 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002040
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302041 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2042 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2043 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2044 AR_RTC_FORCE_WAKE_ON_INT);
2045 } else {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302046
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302047 /* When chip goes into network sleep, it could be waken
2048 * up by MCI_INT interrupt caused by BT's HW messages
2049 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2050 * rate (~100us). This will cause chip to leave and
2051 * re-enter network sleep mode frequently, which in
2052 * consequence will have WLAN MCI HW to generate lots of
2053 * SYS_WAKING and SYS_SLEEPING messages which will make
2054 * BT CPU to busy to process.
2055 */
Rajkumar Manoharan153dccd2012-06-04 16:28:47 +05302056 if (ath9k_hw_mci_is_enabled(ah))
2057 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2058 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302059 /*
2060 * Clear the RTC force wake bit to allow the
2061 * mac to go to sleep.
2062 */
Rajkumar Manoharan153dccd2012-06-04 16:28:47 +05302063 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302064
Rajkumar Manoharan153dccd2012-06-04 16:28:47 +05302065 if (ath9k_hw_mci_is_enabled(ah))
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302066 udelay(30);
Sujithf1dc5602008-10-29 10:16:30 +05302067 }
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04002068
2069 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2070 if (AR_SREV_9300_20_OR_LATER(ah))
2071 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
Sujithf1dc5602008-10-29 10:16:30 +05302072}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002073
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302074static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302075{
2076 u32 val;
2077 int i;
2078
Luis R. Rodriguez9a658d22010-06-21 18:38:47 -04002079 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2080 if (AR_SREV_9300_20_OR_LATER(ah)) {
2081 REG_WRITE(ah, AR_WA, ah->WARegVal);
2082 udelay(10);
2083 }
2084
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302085 if ((REG_READ(ah, AR_RTC_STATUS) &
2086 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2087 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
Sujithf1dc5602008-10-29 10:16:30 +05302088 return false;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002089 }
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302090 if (!AR_SREV_9300_20_OR_LATER(ah))
2091 ath9k_hw_init_pll(ah, NULL);
2092 }
2093 if (AR_SREV_9100(ah))
2094 REG_SET_BIT(ah, AR_RTC_RESET,
2095 AR_RTC_RESET_EN);
2096
2097 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2098 AR_RTC_FORCE_WAKE_EN);
Sujith Manoharan04575f22013-12-28 09:47:13 +05302099 if (AR_SREV_9100(ah))
Sujith Manoharan3683a072014-02-04 08:37:52 +05302100 mdelay(10);
Sujith Manoharan04575f22013-12-28 09:47:13 +05302101 else
2102 udelay(50);
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302103
2104 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2105 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2106 if (val == AR_RTC_STATUS_ON)
2107 break;
2108 udelay(50);
2109 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2110 AR_RTC_FORCE_WAKE_EN);
2111 }
2112 if (i == 0) {
2113 ath_err(ath9k_hw_common(ah),
2114 "Failed to wakeup in %uus\n",
2115 POWER_UP_TIME / 20);
2116 return false;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002117 }
2118
Rajkumar Manoharancdbe4082012-10-25 17:16:53 +05302119 if (ath9k_hw_mci_is_enabled(ah))
2120 ar9003_mci_set_power_awake(ah);
2121
Sujithf1dc5602008-10-29 10:16:30 +05302122 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2123
2124 return true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002125}
2126
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07002127bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Sujithf1dc5602008-10-29 10:16:30 +05302128{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002129 struct ath_common *common = ath9k_hw_common(ah);
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302130 int status = true;
Sujithf1dc5602008-10-29 10:16:30 +05302131 static const char *modes[] = {
2132 "AWAKE",
2133 "FULL-SLEEP",
2134 "NETWORK SLEEP",
2135 "UNDEFINED"
2136 };
Sujithf1dc5602008-10-29 10:16:30 +05302137
Gabor Juhoscbdec972009-07-24 17:27:22 +02002138 if (ah->power_mode == mode)
2139 return status;
2140
Joe Perchesd2182b62011-12-15 14:55:53 -08002141 ath_dbg(common, RESET, "%s -> %s\n",
Joe Perches226afe62010-12-02 19:12:37 -08002142 modes[ah->power_mode], modes[mode]);
Sujithf1dc5602008-10-29 10:16:30 +05302143
2144 switch (mode) {
2145 case ATH9K_PM_AWAKE:
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302146 status = ath9k_hw_set_power_awake(ah);
Sujithf1dc5602008-10-29 10:16:30 +05302147 break;
2148 case ATH9K_PM_FULL_SLEEP:
Sujith Manoharan5955b2b2012-06-04 16:27:30 +05302149 if (ath9k_hw_mci_is_enabled(ah))
Sujith Manoharand1ca8b82012-02-22 12:41:01 +05302150 ar9003_mci_set_full_sleep(ah);
Mohammed Shafi Shajakhan10109112011-11-30 10:41:24 +05302151
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302152 ath9k_set_power_sleep(ah);
Sujith2660b812009-02-09 13:27:26 +05302153 ah->chip_fullsleep = true;
Sujithf1dc5602008-10-29 10:16:30 +05302154 break;
2155 case ATH9K_PM_NETWORK_SLEEP:
Sujith Manoharan31604cf2012-06-04 16:27:36 +05302156 ath9k_set_power_network_sleep(ah);
Sujithf1dc5602008-10-29 10:16:30 +05302157 break;
2158 default:
Joe Perches38002762010-12-02 19:12:36 -08002159 ath_err(common, "Unknown power mode %u\n", mode);
Sujithf1dc5602008-10-29 10:16:30 +05302160 return false;
2161 }
Sujith2660b812009-02-09 13:27:26 +05302162 ah->power_mode = mode;
Sujithf1dc5602008-10-29 10:16:30 +05302163
Luis R. Rodriguez69f4aab2010-12-07 15:13:23 -08002164 /*
2165 * XXX: If this warning never comes up after a while then
2166 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2167 * ath9k_hw_setpower() return type void.
2168 */
Sujith Manoharan97dcec52010-12-20 08:02:42 +05302169
2170 if (!(ah->ah_flags & AH_UNPLUGGED))
2171 ATH_DBG_WARN_ON_ONCE(!status);
Luis R. Rodriguez69f4aab2010-12-07 15:13:23 -08002172
Sujithf1dc5602008-10-29 10:16:30 +05302173 return status;
2174}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002175EXPORT_SYMBOL(ath9k_hw_setpower);
Sujithf1dc5602008-10-29 10:16:30 +05302176
Sujithf1dc5602008-10-29 10:16:30 +05302177/*******************/
2178/* Beacon Handling */
2179/*******************/
2180
Sujithcbe61d82009-02-09 13:27:12 +05302181void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002182{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002183 int flags = 0;
2184
Sujith7d0d0df2010-04-16 11:53:57 +05302185 ENABLE_REGWRITE_BUFFER(ah);
2186
Sujith2660b812009-02-09 13:27:26 +05302187 switch (ah->opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08002188 case NL80211_IFTYPE_ADHOC:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002189 REG_SET_BIT(ah, AR_TXCFG,
2190 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
Thomas Pedersen2664d662013-05-08 10:16:48 -07002191 case NL80211_IFTYPE_MESH_POINT:
Colin McCabed97809d2008-12-01 13:38:55 -08002192 case NL80211_IFTYPE_AP:
Felix Fietkaudd347f22011-03-22 21:54:17 +01002193 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2194 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2195 TU_TO_USEC(ah->config.dma_beacon_response_time));
2196 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2197 TU_TO_USEC(ah->config.sw_beacon_response_time));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002198 flags |=
2199 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2200 break;
Colin McCabed97809d2008-12-01 13:38:55 -08002201 default:
Joe Perchesd2182b62011-12-15 14:55:53 -08002202 ath_dbg(ath9k_hw_common(ah), BEACON,
2203 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
Colin McCabed97809d2008-12-01 13:38:55 -08002204 return;
2205 break;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002206 }
2207
Felix Fietkaudd347f22011-03-22 21:54:17 +01002208 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2209 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2210 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002211
Sujith7d0d0df2010-04-16 11:53:57 +05302212 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302213
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002214 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2215}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002216EXPORT_SYMBOL(ath9k_hw_beaconinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002217
Sujithcbe61d82009-02-09 13:27:12 +05302218void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05302219 const struct ath9k_beacon_state *bs)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002220{
2221 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
Sujith2660b812009-02-09 13:27:26 +05302222 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002223 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002224
Sujith7d0d0df2010-04-16 11:53:57 +05302225 ENABLE_REGWRITE_BUFFER(ah);
2226
Felix Fietkau4ed15762013-12-14 18:03:44 +01002227 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2228 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2229 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002230
Sujith7d0d0df2010-04-16 11:53:57 +05302231 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302232
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002233 REG_RMW_FIELD(ah, AR_RSSI_THR,
2234 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2235
Rajkumar Manoharanf29f5c02011-05-20 17:52:11 +05302236 beaconintval = bs->bs_intval;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002237
2238 if (bs->bs_sleepduration > beaconintval)
2239 beaconintval = bs->bs_sleepduration;
2240
2241 dtimperiod = bs->bs_dtimperiod;
2242 if (bs->bs_sleepduration > dtimperiod)
2243 dtimperiod = bs->bs_sleepduration;
2244
2245 if (beaconintval == dtimperiod)
2246 nextTbtt = bs->bs_nextdtim;
2247 else
2248 nextTbtt = bs->bs_nexttbtt;
2249
Joe Perchesd2182b62011-12-15 14:55:53 -08002250 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2251 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2252 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2253 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002254
Sujith7d0d0df2010-04-16 11:53:57 +05302255 ENABLE_REGWRITE_BUFFER(ah);
2256
Felix Fietkau4ed15762013-12-14 18:03:44 +01002257 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2258 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002259
2260 REG_WRITE(ah, AR_SLEEP1,
2261 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2262 | AR_SLEEP1_ASSUME_DTIM);
2263
Sujith60b67f52008-08-07 10:52:38 +05302264 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002265 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2266 else
2267 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2268
2269 REG_WRITE(ah, AR_SLEEP2,
2270 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2271
Felix Fietkau4ed15762013-12-14 18:03:44 +01002272 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2273 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002274
Sujith7d0d0df2010-04-16 11:53:57 +05302275 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +05302276
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002277 REG_SET_BIT(ah, AR_TIMER_MODE,
2278 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2279 AR_DTIM_TIMER_EN);
2280
Sujith4af9cf42009-02-12 10:06:47 +05302281 /* TSF Out of Range Threshold */
2282 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002283}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002284EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002285
Sujithf1dc5602008-10-29 10:16:30 +05302286/*******************/
2287/* HW Capabilities */
2288/*******************/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002289
Felix Fietkau60540692011-07-19 08:46:44 +02002290static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2291{
2292 eeprom_chainmask &= chip_chainmask;
2293 if (eeprom_chainmask)
2294 return eeprom_chainmask;
2295 else
2296 return chip_chainmask;
2297}
2298
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002299/**
2300 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2301 * @ah: the atheros hardware data structure
2302 *
2303 * We enable DFS support upstream on chipsets which have passed a series
2304 * of tests. The testing requirements are going to be documented. Desired
2305 * test requirements are documented at:
2306 *
2307 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2308 *
2309 * Once a new chipset gets properly tested an individual commit can be used
2310 * to document the testing for DFS for that chipset.
2311 */
2312static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2313{
2314
2315 switch (ah->hw_version.macVersion) {
Zefir Kurtisi73e49372013-04-03 18:31:31 +02002316 /* for temporary testing DFS with 9280 */
2317 case AR_SREV_VERSION_9280:
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002318 /* AR9580 will likely be our first target to get testing on */
2319 case AR_SREV_VERSION_9580:
Zefir Kurtisi73e49372013-04-03 18:31:31 +02002320 return true;
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002321 default:
2322 return false;
2323 }
2324}
2325
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002326int ath9k_hw_fill_cap_info(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002327{
Sujith2660b812009-02-09 13:27:26 +05302328 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002329 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002330 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002331
Sujith Manoharan0ff2b5c2011-04-20 11:00:34 +05302332 u16 eeval;
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -08002333 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002334
Sujithf74df6f2009-02-09 13:27:24 +05302335 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002336 regulatory->current_rd = eeval;
Sujithf1dc5602008-10-29 10:16:30 +05302337
Sujith2660b812009-02-09 13:27:26 +05302338 if (ah->opmode != NL80211_IFTYPE_AP &&
Sujithd535a422009-02-09 13:27:06 +05302339 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07002340 if (regulatory->current_rd == 0x64 ||
2341 regulatory->current_rd == 0x65)
2342 regulatory->current_rd += 5;
2343 else if (regulatory->current_rd == 0x41)
2344 regulatory->current_rd = 0x43;
Joe Perchesd2182b62011-12-15 14:55:53 -08002345 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2346 regulatory->current_rd);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002347 }
Sujithdc2222a2008-08-14 13:26:55 +05302348
Sujithf74df6f2009-02-09 13:27:24 +05302349 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
Felix Fietkau34689682014-10-25 17:19:34 +02002350
2351 if (eeval & AR5416_OPFLAGS_11A) {
2352 if (ah->disable_5ghz)
2353 ath_warn(common, "disabling 5GHz band\n");
2354 else
2355 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002356 }
2357
Felix Fietkau34689682014-10-25 17:19:34 +02002358 if (eeval & AR5416_OPFLAGS_11G) {
2359 if (ah->disable_2ghz)
2360 ath_warn(common, "disabling 2GHz band\n");
2361 else
2362 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2363 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002364
Felix Fietkau34689682014-10-25 17:19:34 +02002365 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2366 ath_err(common, "both bands are disabled\n");
2367 return -EINVAL;
2368 }
Sujithf1dc5602008-10-29 10:16:30 +05302369
Sujith Manoharane41db612012-09-10 09:20:12 +05302370 if (AR_SREV_9485(ah) ||
2371 AR_SREV_9285(ah) ||
2372 AR_SREV_9330(ah) ||
2373 AR_SREV_9565(ah))
Sujith Manoharanee79ccd2014-11-16 06:11:04 +05302374 pCap->chip_chainmask = 1;
Felix Fietkau60540692011-07-19 08:46:44 +02002375 else if (!AR_SREV_9280_20_OR_LATER(ah))
Sujith Manoharanee79ccd2014-11-16 06:11:04 +05302376 pCap->chip_chainmask = 7;
2377 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2378 AR_SREV_9340(ah) ||
2379 AR_SREV_9462(ah) ||
2380 AR_SREV_9531(ah))
2381 pCap->chip_chainmask = 3;
Felix Fietkau60540692011-07-19 08:46:44 +02002382 else
Sujith Manoharanee79ccd2014-11-16 06:11:04 +05302383 pCap->chip_chainmask = 7;
Felix Fietkau60540692011-07-19 08:46:44 +02002384
Sujithf74df6f2009-02-09 13:27:24 +05302385 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002386 /*
2387 * For AR9271 we will temporarilly uses the rx chainmax as read from
2388 * the EEPROM.
2389 */
Sujith8147f5d2009-02-20 15:13:23 +05302390 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002391 !(eeval & AR5416_OPFLAGS_11A) &&
2392 !(AR_SREV_9271(ah)))
2393 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
Sujith8147f5d2009-02-20 15:13:23 +05302394 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
Felix Fietkau598cdd52011-03-19 13:55:42 +01002395 else if (AR_SREV_9100(ah))
2396 pCap->rx_chainmask = 0x7;
Sujith8147f5d2009-02-20 15:13:23 +05302397 else
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002398 /* Use rx_chainmask from EEPROM. */
Sujith8147f5d2009-02-20 15:13:23 +05302399 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05302400
Sujith Manoharanee79ccd2014-11-16 06:11:04 +05302401 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2402 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
Felix Fietkau82b2d332011-09-03 01:40:23 +02002403 ah->txchainmask = pCap->tx_chainmask;
2404 ah->rxchainmask = pCap->rx_chainmask;
Felix Fietkau60540692011-07-19 08:46:44 +02002405
Felix Fietkau7a370812010-09-22 12:34:52 +02002406 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
Sujithf1dc5602008-10-29 10:16:30 +05302407
Felix Fietkau02d2ebb2010-11-22 15:39:39 +01002408 /* enable key search for every frame in an aggregate */
2409 if (AR_SREV_9300_20_OR_LATER(ah))
2410 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2411
Bruno Randolfce2220d2010-09-17 11:36:25 +09002412 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2413
Felix Fietkau0db156e2011-03-23 20:57:29 +01002414 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
Sujithf1dc5602008-10-29 10:16:30 +05302415 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2416 else
2417 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2418
Sujith5b5fa352010-03-17 14:25:15 +05302419 if (AR_SREV_9271(ah))
2420 pCap->num_gpio_pins = AR9271_NUM_GPIO;
Sujith88c1f4f2010-06-30 14:46:31 +05302421 else if (AR_DEVID_7010(ah))
2422 pCap->num_gpio_pins = AR7010_NUM_GPIO;
Mohammed Shafi Shajakhan6321eb02011-09-30 11:31:27 +05302423 else if (AR_SREV_9300_20_OR_LATER(ah))
2424 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2425 else if (AR_SREV_9287_11_OR_LATER(ah))
2426 pCap->num_gpio_pins = AR9287_NUM_GPIO;
Felix Fietkaue17f83e2010-09-22 12:34:53 +02002427 else if (AR_SREV_9285_12_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302428 pCap->num_gpio_pins = AR9285_NUM_GPIO;
Felix Fietkau7a370812010-09-22 12:34:52 +02002429 else if (AR_SREV_9280_20_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302430 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2431 else
2432 pCap->num_gpio_pins = AR_NUM_GPIO;
2433
Mohammed Shafi Shajakhan1b2538b2011-12-07 16:51:39 +05302434 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302435 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
Mohammed Shafi Shajakhan1b2538b2011-12-07 16:51:39 +05302436 else
Sujithf1dc5602008-10-29 10:16:30 +05302437 pCap->rts_aggr_limit = (8 * 1024);
Sujithf1dc5602008-10-29 10:16:30 +05302438
Johannes Berg74e13062013-07-03 20:55:38 +02002439#ifdef CONFIG_ATH9K_RFKILL
Sujith2660b812009-02-09 13:27:26 +05302440 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2441 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2442 ah->rfkill_gpio =
2443 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2444 ah->rfkill_polarity =
2445 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
Sujithf1dc5602008-10-29 10:16:30 +05302446
2447 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2448 }
2449#endif
Vasanthakumar Thiagarajand5d11542010-05-17 18:57:56 -07002450 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
Vivek Natarajanbde748a2010-04-05 14:48:05 +05302451 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2452 else
2453 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
Sujithf1dc5602008-10-29 10:16:30 +05302454
Senthil Balasubramaniane7594072008-12-08 19:43:48 +05302455 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
Sujithf1dc5602008-10-29 10:16:30 +05302456 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2457 else
2458 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2459
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002460 if (AR_SREV_9300_20_OR_LATER(ah)) {
Vasanthakumar Thiagarajan784ad502010-12-06 04:27:40 -08002461 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
Sujith Manoharana4a29542012-09-10 09:20:03 +05302462 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
Vasanthakumar Thiagarajan784ad502010-12-06 04:27:40 -08002463 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2464
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002465 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2466 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2467 pCap->rx_status_len = sizeof(struct ar9003_rxs);
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -04002468 pCap->tx_desc_len = sizeof(struct ar9003_txc);
Vasanthakumar Thiagarajan5088c2f2010-04-15 17:39:34 -04002469 pCap->txs_len = sizeof(struct ar9003_txs);
Vasanthakumar Thiagarajan162c3be2010-04-15 17:38:41 -04002470 } else {
2471 pCap->tx_desc_len = sizeof(struct ath_desc);
Felix Fietkaua949b172011-07-09 11:12:47 +07002472 if (AR_SREV_9280_20(ah))
Felix Fietkau6b42e8d2010-04-26 15:04:35 -04002473 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
Vasanthakumar Thiagarajanceb26442010-04-15 17:38:25 -04002474 }
Vasanthakumar Thiagarajan1adf02f2010-04-15 17:38:24 -04002475
Vasanthakumar Thiagarajan6c84ce02010-04-15 17:39:16 -04002476 if (AR_SREV_9300_20_OR_LATER(ah))
2477 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2478
Senthil Balasubramanian6ee63f52010-11-10 05:03:16 -08002479 if (AR_SREV_9300_20_OR_LATER(ah))
2480 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2481
Felix Fietkaua42acef2010-09-22 12:34:54 +02002482 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
Vasanthakumar Thiagarajan6473d242010-05-13 18:42:38 -07002483 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2484
Sujith Manoharanf85c3372013-08-04 14:21:53 +05302485 if (AR_SREV_9285(ah)) {
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002486 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2487 ant_div_ctl1 =
2488 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
Sujith Manoharanf85c3372013-08-04 14:21:53 +05302489 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002490 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
Sujith Manoharanf85c3372013-08-04 14:21:53 +05302491 ath_info(common, "Enable LNA combining\n");
2492 }
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002493 }
Sujith Manoharanf85c3372013-08-04 14:21:53 +05302494 }
2495
Mohammed Shafi Shajakhanea066d52010-11-23 20:42:27 +05302496 if (AR_SREV_9300_20_OR_LATER(ah)) {
2497 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2498 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2499 }
2500
Sujith Manoharan06236e52012-09-16 08:07:12 +05302501 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
Mohammed Shafi Shajakhan21d2c632011-05-13 20:29:31 +05302502 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
Sujith Manoharanf85c3372013-08-04 14:21:53 +05302503 if ((ant_div_ctl1 >> 0x6) == 0x3) {
Mohammed Shafi Shajakhan21d2c632011-05-13 20:29:31 +05302504 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
Sujith Manoharanf85c3372013-08-04 14:21:53 +05302505 ath_info(common, "Enable LNA combining\n");
2506 }
Mohammed Shafi Shajakhan21d2c632011-05-13 20:29:31 +05302507 }
Vasanthakumar Thiagarajan754dc532010-09-02 01:34:41 -07002508
Zefir Kurtisi9a66af32011-12-14 20:16:33 -08002509 if (ath9k_hw_dfs_tested(ah))
2510 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2511
Vasanthakumar Thiagarajan47c80de2010-12-06 04:27:43 -08002512 tx_chainmask = pCap->tx_chainmask;
2513 rx_chainmask = pCap->rx_chainmask;
2514 while (tx_chainmask || rx_chainmask) {
2515 if (tx_chainmask & BIT(0))
2516 pCap->max_txchains++;
2517 if (rx_chainmask & BIT(0))
2518 pCap->max_rxchains++;
2519
2520 tx_chainmask >>= 1;
2521 rx_chainmask >>= 1;
2522 }
2523
Sujith Manoharana4a29542012-09-10 09:20:03 +05302524 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
Mohammed Shafi Shajakhan3789d592012-03-09 12:01:55 +05302525 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2526 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2527
Sujith Manoharan2b5e54e2013-06-24 18:18:46 +05302528 if (AR_SREV_9462_20_OR_LATER(ah))
Mohammed Shafi Shajakhan3789d592012-03-09 12:01:55 +05302529 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
Mohammed Shafi Shajakhan3789d592012-03-09 12:01:55 +05302530 }
2531
Sujith Manoharan846e4382013-06-03 09:19:24 +05302532 if (AR_SREV_9462(ah))
2533 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
Mohammed Shafi Shajakhand6878092012-07-10 14:55:17 +05302534
Sujith Manoharan0f21ee82012-12-10 07:22:37 +05302535 if (AR_SREV_9300_20_OR_LATER(ah) &&
2536 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2537 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2538
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01002539 return 0;
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07002540}
2541
Sujithf1dc5602008-10-29 10:16:30 +05302542/****************************/
2543/* GPIO / RFKILL / Antennae */
2544/****************************/
2545
Sujithcbe61d82009-02-09 13:27:12 +05302546static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05302547 u32 gpio, u32 type)
2548{
2549 int addr;
2550 u32 gpio_shift, tmp;
2551
2552 if (gpio > 11)
2553 addr = AR_GPIO_OUTPUT_MUX3;
2554 else if (gpio > 5)
2555 addr = AR_GPIO_OUTPUT_MUX2;
2556 else
2557 addr = AR_GPIO_OUTPUT_MUX1;
2558
2559 gpio_shift = (gpio % 6) * 5;
2560
2561 if (AR_SREV_9280_20_OR_LATER(ah)
2562 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2563 REG_RMW(ah, addr, (type << gpio_shift),
2564 (0x1f << gpio_shift));
2565 } else {
2566 tmp = REG_READ(ah, addr);
2567 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2568 tmp &= ~(0x1f << gpio_shift);
2569 tmp |= (type << gpio_shift);
2570 REG_WRITE(ah, addr, tmp);
2571 }
2572}
2573
Sujithcbe61d82009-02-09 13:27:12 +05302574void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05302575{
2576 u32 gpio_shift;
2577
Luis R. Rodriguez9680e8a2009-09-13 23:28:00 -07002578 BUG_ON(gpio >= ah->caps.num_gpio_pins);
Sujithf1dc5602008-10-29 10:16:30 +05302579
Sujith88c1f4f2010-06-30 14:46:31 +05302580 if (AR_DEVID_7010(ah)) {
2581 gpio_shift = gpio;
2582 REG_RMW(ah, AR7010_GPIO_OE,
2583 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2584 (AR7010_GPIO_OE_MASK << gpio_shift));
2585 return;
2586 }
Sujithf1dc5602008-10-29 10:16:30 +05302587
Sujith88c1f4f2010-06-30 14:46:31 +05302588 gpio_shift = gpio << 1;
Sujithf1dc5602008-10-29 10:16:30 +05302589 REG_RMW(ah,
2590 AR_GPIO_OE_OUT,
2591 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2592 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2593}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002594EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
Sujithf1dc5602008-10-29 10:16:30 +05302595
Sujithcbe61d82009-02-09 13:27:12 +05302596u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05302597{
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302598#define MS_REG_READ(x, y) \
2599 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2600
Sujith2660b812009-02-09 13:27:26 +05302601 if (gpio >= ah->caps.num_gpio_pins)
Sujithf1dc5602008-10-29 10:16:30 +05302602 return 0xffffffff;
2603
Sujith88c1f4f2010-06-30 14:46:31 +05302604 if (AR_DEVID_7010(ah)) {
2605 u32 val;
2606 val = REG_READ(ah, AR7010_GPIO_IN);
2607 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2608 } else if (AR_SREV_9300_20_OR_LATER(ah))
Vasanthakumar Thiagarajan93069902010-11-30 23:24:09 -08002609 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2610 AR_GPIO_BIT(gpio)) != 0;
Felix Fietkau783dfca2010-04-15 17:38:11 -04002611 else if (AR_SREV_9271(ah))
Sujith5b5fa352010-03-17 14:25:15 +05302612 return MS_REG_READ(AR9271, gpio) != 0;
Felix Fietkaua42acef2010-09-22 12:34:54 +02002613 else if (AR_SREV_9287_11_OR_LATER(ah))
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05302614 return MS_REG_READ(AR9287, gpio) != 0;
Felix Fietkaue17f83e2010-09-22 12:34:53 +02002615 else if (AR_SREV_9285_12_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302616 return MS_REG_READ(AR9285, gpio) != 0;
Felix Fietkau7a370812010-09-22 12:34:52 +02002617 else if (AR_SREV_9280_20_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05302618 return MS_REG_READ(AR928X, gpio) != 0;
2619 else
2620 return MS_REG_READ(AR, gpio) != 0;
Sujithf1dc5602008-10-29 10:16:30 +05302621}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002622EXPORT_SYMBOL(ath9k_hw_gpio_get);
Sujithf1dc5602008-10-29 10:16:30 +05302623
Sujithcbe61d82009-02-09 13:27:12 +05302624void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
Sujithf1dc5602008-10-29 10:16:30 +05302625 u32 ah_signal_type)
2626{
2627 u32 gpio_shift;
2628
Sujith88c1f4f2010-06-30 14:46:31 +05302629 if (AR_DEVID_7010(ah)) {
2630 gpio_shift = gpio;
2631 REG_RMW(ah, AR7010_GPIO_OE,
2632 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2633 (AR7010_GPIO_OE_MASK << gpio_shift));
2634 return;
2635 }
2636
Sujithf1dc5602008-10-29 10:16:30 +05302637 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
Sujithf1dc5602008-10-29 10:16:30 +05302638 gpio_shift = 2 * gpio;
Sujithf1dc5602008-10-29 10:16:30 +05302639 REG_RMW(ah,
2640 AR_GPIO_OE_OUT,
2641 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2642 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2643}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002644EXPORT_SYMBOL(ath9k_hw_cfg_output);
Sujithf1dc5602008-10-29 10:16:30 +05302645
Sujithcbe61d82009-02-09 13:27:12 +05302646void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
Sujithf1dc5602008-10-29 10:16:30 +05302647{
Sujith88c1f4f2010-06-30 14:46:31 +05302648 if (AR_DEVID_7010(ah)) {
2649 val = val ? 0 : 1;
2650 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2651 AR_GPIO_BIT(gpio));
2652 return;
2653 }
2654
Sujith5b5fa352010-03-17 14:25:15 +05302655 if (AR_SREV_9271(ah))
2656 val = ~val;
2657
Sujithf1dc5602008-10-29 10:16:30 +05302658 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2659 AR_GPIO_BIT(gpio));
2660}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002661EXPORT_SYMBOL(ath9k_hw_set_gpio);
Sujithf1dc5602008-10-29 10:16:30 +05302662
Sujithcbe61d82009-02-09 13:27:12 +05302663void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
Sujithf1dc5602008-10-29 10:16:30 +05302664{
2665 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2666}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002667EXPORT_SYMBOL(ath9k_hw_setantenna);
Sujithf1dc5602008-10-29 10:16:30 +05302668
Sujithf1dc5602008-10-29 10:16:30 +05302669/*********************/
2670/* General Operation */
2671/*********************/
2672
Sujithcbe61d82009-02-09 13:27:12 +05302673u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302674{
2675 u32 bits = REG_READ(ah, AR_RX_FILTER);
2676 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2677
2678 if (phybits & AR_PHY_ERR_RADAR)
2679 bits |= ATH9K_RX_FILTER_PHYRADAR;
2680 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2681 bits |= ATH9K_RX_FILTER_PHYERR;
2682
2683 return bits;
2684}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002685EXPORT_SYMBOL(ath9k_hw_getrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302686
Sujithcbe61d82009-02-09 13:27:12 +05302687void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
Sujithf1dc5602008-10-29 10:16:30 +05302688{
2689 u32 phybits;
2690
Sujith7d0d0df2010-04-16 11:53:57 +05302691 ENABLE_REGWRITE_BUFFER(ah);
2692
Sujith Manoharana4a29542012-09-10 09:20:03 +05302693 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302694 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2695
Sujith7ea310b2009-09-03 12:08:43 +05302696 REG_WRITE(ah, AR_RX_FILTER, bits);
2697
Sujithf1dc5602008-10-29 10:16:30 +05302698 phybits = 0;
2699 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2700 phybits |= AR_PHY_ERR_RADAR;
2701 if (bits & ATH9K_RX_FILTER_PHYERR)
2702 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2703 REG_WRITE(ah, AR_PHY_ERR, phybits);
2704
2705 if (phybits)
Felix Fietkauca7a4de2011-03-23 20:57:26 +01002706 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
Sujithf1dc5602008-10-29 10:16:30 +05302707 else
Felix Fietkauca7a4de2011-03-23 20:57:26 +01002708 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
Sujith7d0d0df2010-04-16 11:53:57 +05302709
2710 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +05302711}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002712EXPORT_SYMBOL(ath9k_hw_setrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302713
Sujithcbe61d82009-02-09 13:27:12 +05302714bool ath9k_hw_phy_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302715{
Rajkumar Manoharan99922a42012-06-04 16:28:31 +05302716 if (ath9k_hw_mci_is_enabled(ah))
2717 ar9003_mci_bt_gain_ctrl(ah);
2718
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302719 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2720 return false;
2721
2722 ath9k_hw_init_pll(ah, NULL);
Felix Fietkau8efa7a82012-03-14 16:40:23 +01002723 ah->htc_reset_init = true;
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302724 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302725}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002726EXPORT_SYMBOL(ath9k_hw_phy_disable);
Sujithf1dc5602008-10-29 10:16:30 +05302727
Sujithcbe61d82009-02-09 13:27:12 +05302728bool ath9k_hw_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302729{
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07002730 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05302731 return false;
2732
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302733 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2734 return false;
2735
2736 ath9k_hw_init_pll(ah, NULL);
2737 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302738}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002739EXPORT_SYMBOL(ath9k_hw_disable);
Sujithf1dc5602008-10-29 10:16:30 +05302740
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002741static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05302742{
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002743 enum eeprom_param gain_param;
Felix Fietkau9c204b42011-07-27 15:01:05 +02002744
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002745 if (IS_CHAN_2GHZ(chan))
2746 gain_param = EEP_ANTENNA_GAIN_2G;
2747 else
2748 gain_param = EEP_ANTENNA_GAIN_5G;
Sujithf1dc5602008-10-29 10:16:30 +05302749
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002750 return ah->eep_ops->get_eeprom(ah, gain_param);
2751}
2752
Gabor Juhos64ea57d2012-04-15 20:38:05 +02002753void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2754 bool test)
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002755{
2756 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2757 struct ieee80211_channel *channel;
2758 int chan_pwr, new_pwr, max_gain;
2759 int ant_gain, ant_reduction = 0;
2760
2761 if (!chan)
2762 return;
2763
2764 channel = chan->chan;
2765 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2766 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2767 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2768
2769 ant_gain = get_antenna_gain(ah, chan);
2770 if (ant_gain > max_gain)
2771 ant_reduction = ant_gain - max_gain;
Sujithf1dc5602008-10-29 10:16:30 +05302772
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07002773 ah->eep_ops->set_txpower(ah, chan,
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002774 ath9k_regd_get_ctl(reg, chan),
Gabor Juhos64ea57d2012-04-15 20:38:05 +02002775 ant_reduction, new_pwr, test);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002776}
2777
2778void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2779{
2780 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2781 struct ath9k_channel *chan = ah->curchan;
2782 struct ieee80211_channel *channel = chan->chan;
2783
Dan Carpenter48ef5c42011-10-17 10:28:23 +03002784 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002785 if (test)
2786 channel->max_power = MAX_RATE_POWER / 2;
2787
Gabor Juhos64ea57d2012-04-15 20:38:05 +02002788 ath9k_hw_apply_txpower(ah, chan, test);
Felix Fietkauca2c68c2011-10-08 20:06:20 +02002789
2790 if (test)
2791 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
Sujithf1dc5602008-10-29 10:16:30 +05302792}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002793EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
Sujithf1dc5602008-10-29 10:16:30 +05302794
Sujithcbe61d82009-02-09 13:27:12 +05302795void ath9k_hw_setopmode(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302796{
Sujith2660b812009-02-09 13:27:26 +05302797 ath9k_hw_set_operating_mode(ah, ah->opmode);
Sujithf1dc5602008-10-29 10:16:30 +05302798}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002799EXPORT_SYMBOL(ath9k_hw_setopmode);
Sujithf1dc5602008-10-29 10:16:30 +05302800
Sujithcbe61d82009-02-09 13:27:12 +05302801void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
Sujithf1dc5602008-10-29 10:16:30 +05302802{
2803 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2804 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2805}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002806EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
Sujithf1dc5602008-10-29 10:16:30 +05302807
Luis R. Rodriguezf2b21432009-09-10 08:50:20 -07002808void ath9k_hw_write_associd(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302809{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07002810 struct ath_common *common = ath9k_hw_common(ah);
2811
2812 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2813 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2814 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
Sujithf1dc5602008-10-29 10:16:30 +05302815}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002816EXPORT_SYMBOL(ath9k_hw_write_associd);
Sujithf1dc5602008-10-29 10:16:30 +05302817
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002818#define ATH9K_MAX_TSF_READ 10
2819
Sujithcbe61d82009-02-09 13:27:12 +05302820u64 ath9k_hw_gettsf64(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302821{
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002822 u32 tsf_lower, tsf_upper1, tsf_upper2;
2823 int i;
Sujithf1dc5602008-10-29 10:16:30 +05302824
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002825 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2826 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2827 tsf_lower = REG_READ(ah, AR_TSF_L32);
2828 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2829 if (tsf_upper2 == tsf_upper1)
2830 break;
2831 tsf_upper1 = tsf_upper2;
2832 }
Sujithf1dc5602008-10-29 10:16:30 +05302833
Benoit Papillault1c0fc652010-04-16 00:07:26 +02002834 WARN_ON( i == ATH9K_MAX_TSF_READ );
2835
2836 return (((u64)tsf_upper1 << 32) | tsf_lower);
Sujithf1dc5602008-10-29 10:16:30 +05302837}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002838EXPORT_SYMBOL(ath9k_hw_gettsf64);
Sujithf1dc5602008-10-29 10:16:30 +05302839
Sujithcbe61d82009-02-09 13:27:12 +05302840void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002841{
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002842 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
Alina Friedrichsenb9a16192009-03-02 23:28:38 +01002843 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002844}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002845EXPORT_SYMBOL(ath9k_hw_settsf64);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01002846
Sujithcbe61d82009-02-09 13:27:12 +05302847void ath9k_hw_reset_tsf(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05302848{
Gabor Juhosf9b604f2009-06-21 00:02:15 +02002849 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2850 AH_TSF_WRITE_TIMEOUT))
Joe Perchesd2182b62011-12-15 14:55:53 -08002851 ath_dbg(ath9k_hw_common(ah), RESET,
Joe Perches226afe62010-12-02 19:12:37 -08002852 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
Gabor Juhosf9b604f2009-06-21 00:02:15 +02002853
Sujithf1dc5602008-10-29 10:16:30 +05302854 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002855}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002856EXPORT_SYMBOL(ath9k_hw_reset_tsf);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002857
Sujith Manoharan60ca9f82012-07-17 17:15:37 +05302858void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002859{
Sujith Manoharan60ca9f82012-07-17 17:15:37 +05302860 if (set)
Sujith2660b812009-02-09 13:27:26 +05302861 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002862 else
Sujith2660b812009-02-09 13:27:26 +05302863 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002864}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002865EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002866
Felix Fietkaue4744ec2013-10-11 23:31:01 +02002867void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002868{
Sujithf1dc5602008-10-29 10:16:30 +05302869 u32 macmode;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002870
Felix Fietkaue4744ec2013-10-11 23:31:01 +02002871 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
Sujithf1dc5602008-10-29 10:16:30 +05302872 macmode = AR_2040_JOINED_RX_CLEAR;
2873 else
2874 macmode = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002875
Sujithf1dc5602008-10-29 10:16:30 +05302876 REG_WRITE(ah, AR_2040_MODE, macmode);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002877}
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302878
2879/* HW Generic timers configuration */
2880
2881static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2882{
2883 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2884 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2885 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2886 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2887 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2888 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2889 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2890 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2891 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2892 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2893 AR_NDP2_TIMER_MODE, 0x0002},
2894 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2895 AR_NDP2_TIMER_MODE, 0x0004},
2896 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2897 AR_NDP2_TIMER_MODE, 0x0008},
2898 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2899 AR_NDP2_TIMER_MODE, 0x0010},
2900 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2901 AR_NDP2_TIMER_MODE, 0x0020},
2902 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2903 AR_NDP2_TIMER_MODE, 0x0040},
2904 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2905 AR_NDP2_TIMER_MODE, 0x0080}
2906};
2907
2908/* HW generic timer primitives */
2909
Felix Fietkaudd347f22011-03-22 21:54:17 +01002910u32 ath9k_hw_gettsf32(struct ath_hw *ah)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302911{
2912 return REG_READ(ah, AR_TSF_L32);
2913}
Felix Fietkaudd347f22011-03-22 21:54:17 +01002914EXPORT_SYMBOL(ath9k_hw_gettsf32);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302915
Sujith Manoharanf4c34af2014-11-16 06:11:03 +05302916void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
2917{
2918 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2919
2920 if (timer_table->tsf2_enabled) {
2921 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
2922 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
2923 }
2924}
2925
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302926struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2927 void (*trigger)(void *),
2928 void (*overflow)(void *),
2929 void *arg,
2930 u8 timer_index)
2931{
2932 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2933 struct ath_gen_timer *timer;
2934
Felix Fietkauc67ce332013-12-14 18:03:38 +01002935 if ((timer_index < AR_FIRST_NDP_TIMER) ||
Sujith Manoharanf4c34af2014-11-16 06:11:03 +05302936 (timer_index >= ATH_MAX_GEN_TIMER))
2937 return NULL;
2938
2939 if ((timer_index > AR_FIRST_NDP_TIMER) &&
2940 !AR_SREV_9300_20_OR_LATER(ah))
Felix Fietkauc67ce332013-12-14 18:03:38 +01002941 return NULL;
2942
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302943 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
Joe Perches14f8dc42013-02-07 11:46:27 +00002944 if (timer == NULL)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302945 return NULL;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302946
2947 /* allocate a hardware generic timer slot */
2948 timer_table->timers[timer_index] = timer;
2949 timer->index = timer_index;
2950 timer->trigger = trigger;
2951 timer->overflow = overflow;
2952 timer->arg = arg;
2953
Sujith Manoharanf4c34af2014-11-16 06:11:03 +05302954 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
2955 timer_table->tsf2_enabled = true;
2956 ath9k_hw_gen_timer_start_tsf2(ah);
2957 }
2958
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302959 return timer;
2960}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002961EXPORT_SYMBOL(ath_gen_timer_alloc);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302962
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07002963void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2964 struct ath_gen_timer *timer,
Felix Fietkauc67ce332013-12-14 18:03:38 +01002965 u32 timer_next,
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07002966 u32 timer_period)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302967{
2968 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
Felix Fietkauc67ce332013-12-14 18:03:38 +01002969 u32 mask = 0;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302970
Felix Fietkauc67ce332013-12-14 18:03:38 +01002971 timer_table->timer_mask |= BIT(timer->index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302972
2973 /*
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302974 * Program generic timer registers
2975 */
2976 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2977 timer_next);
2978 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2979 timer_period);
2980 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2981 gen_tmr_configuration[timer->index].mode_mask);
2982
Sujith Manoharana4a29542012-09-10 09:20:03 +05302983 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302984 /*
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05302985 * Starting from AR9462, each generic timer can select which tsf
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +05302986 * to use. But we still follow the old rule, 0 - 7 use tsf and
2987 * 8 - 15 use tsf2.
2988 */
2989 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2990 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2991 (1 << timer->index));
2992 else
2993 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2994 (1 << timer->index));
2995 }
2996
Felix Fietkauc67ce332013-12-14 18:03:38 +01002997 if (timer->trigger)
2998 mask |= SM(AR_GENTMR_BIT(timer->index),
2999 AR_IMR_S5_GENTIMER_TRIG);
3000 if (timer->overflow)
3001 mask |= SM(AR_GENTMR_BIT(timer->index),
3002 AR_IMR_S5_GENTIMER_THRESH);
3003
3004 REG_SET_BIT(ah, AR_IMR_S5, mask);
3005
3006 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3007 ah->imask |= ATH9K_INT_GENTIMER;
3008 ath9k_hw_set_interrupts(ah);
3009 }
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303010}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003011EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303012
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07003013void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303014{
3015 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3016
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303017 /* Clear generic timer enable bits. */
3018 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3019 gen_tmr_configuration[timer->index].mode_mask);
3020
Sujith Manoharanb7f59762012-09-11 10:46:24 +05303021 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3022 /*
3023 * Need to switch back to TSF if it was using TSF2.
3024 */
3025 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3026 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3027 (1 << timer->index));
3028 }
3029 }
3030
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303031 /* Disable both trigger and thresh interrupt masks */
3032 REG_CLR_BIT(ah, AR_IMR_S5,
3033 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3034 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3035
Felix Fietkauc67ce332013-12-14 18:03:38 +01003036 timer_table->timer_mask &= ~BIT(timer->index);
3037
3038 if (timer_table->timer_mask == 0) {
3039 ah->imask &= ~ATH9K_INT_GENTIMER;
3040 ath9k_hw_set_interrupts(ah);
3041 }
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303042}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003043EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303044
3045void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3046{
3047 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3048
3049 /* free the hardware generic timer slot */
3050 timer_table->timers[timer->index] = NULL;
3051 kfree(timer);
3052}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003053EXPORT_SYMBOL(ath_gen_timer_free);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303054
3055/*
3056 * Generic Timer Interrupts handling
3057 */
3058void ath_gen_timer_isr(struct ath_hw *ah)
3059{
3060 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3061 struct ath_gen_timer *timer;
Felix Fietkauc67ce332013-12-14 18:03:38 +01003062 unsigned long trigger_mask, thresh_mask;
3063 unsigned int index;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303064
3065 /* get hardware generic timer interrupt status */
3066 trigger_mask = ah->intr_gen_timer_trigger;
3067 thresh_mask = ah->intr_gen_timer_thresh;
Felix Fietkauc67ce332013-12-14 18:03:38 +01003068 trigger_mask &= timer_table->timer_mask;
3069 thresh_mask &= timer_table->timer_mask;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303070
Felix Fietkauc67ce332013-12-14 18:03:38 +01003071 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303072 timer = timer_table->timers[index];
Felix Fietkauc67ce332013-12-14 18:03:38 +01003073 if (!timer)
3074 continue;
3075 if (!timer->overflow)
3076 continue;
Felix Fietkaua6a172b2013-12-20 16:18:45 +01003077
3078 trigger_mask &= ~BIT(index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303079 timer->overflow(timer->arg);
3080 }
3081
Felix Fietkauc67ce332013-12-14 18:03:38 +01003082 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303083 timer = timer_table->timers[index];
Felix Fietkauc67ce332013-12-14 18:03:38 +01003084 if (!timer)
3085 continue;
3086 if (!timer->trigger)
3087 continue;
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303088 timer->trigger(timer->arg);
3089 }
3090}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003091EXPORT_SYMBOL(ath_gen_timer_isr);
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003092
Sujith05020d22010-03-17 14:25:23 +05303093/********/
3094/* HTC */
3095/********/
3096
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003097static struct {
3098 u32 version;
3099 const char * name;
3100} ath_mac_bb_names[] = {
3101 /* Devices with external radios */
3102 { AR_SREV_VERSION_5416_PCI, "5416" },
3103 { AR_SREV_VERSION_5416_PCIE, "5418" },
3104 { AR_SREV_VERSION_9100, "9100" },
3105 { AR_SREV_VERSION_9160, "9160" },
3106 /* Single-chip solutions */
3107 { AR_SREV_VERSION_9280, "9280" },
3108 { AR_SREV_VERSION_9285, "9285" },
Luis R. Rodriguez11158472009-10-27 12:59:35 -04003109 { AR_SREV_VERSION_9287, "9287" },
3110 { AR_SREV_VERSION_9271, "9271" },
Luis R. Rodriguezec839032010-04-15 17:39:20 -04003111 { AR_SREV_VERSION_9300, "9300" },
Gabor Juhos2c8e5932011-06-21 11:23:21 +02003112 { AR_SREV_VERSION_9330, "9330" },
Florian Fainelli397e5d52011-08-25 21:33:48 +02003113 { AR_SREV_VERSION_9340, "9340" },
Senthil Balasubramanian8f06ca22011-04-01 17:16:33 +05303114 { AR_SREV_VERSION_9485, "9485" },
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +05303115 { AR_SREV_VERSION_9462, "9462" },
Gabor Juhos485124c2012-07-03 19:13:19 +02003116 { AR_SREV_VERSION_9550, "9550" },
Sujith Manoharan77fac462012-09-11 20:09:18 +05303117 { AR_SREV_VERSION_9565, "9565" },
Sujith Manoharanc08148b2014-03-17 15:02:46 +05303118 { AR_SREV_VERSION_9531, "9531" },
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003119};
3120
3121/* For devices with external radios */
3122static struct {
3123 u16 version;
3124 const char * name;
3125} ath_rf_names[] = {
3126 { 0, "5133" },
3127 { AR_RAD5133_SREV_MAJOR, "5133" },
3128 { AR_RAD5122_SREV_MAJOR, "5122" },
3129 { AR_RAD2133_SREV_MAJOR, "2133" },
3130 { AR_RAD2122_SREV_MAJOR, "2122" }
3131};
3132
3133/*
3134 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3135 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003136static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003137{
3138 int i;
3139
3140 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3141 if (ath_mac_bb_names[i].version == mac_bb_version) {
3142 return ath_mac_bb_names[i].name;
3143 }
3144 }
3145
3146 return "????";
3147}
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003148
3149/*
3150 * Return the RF name. "????" is returned if the RF is unknown.
3151 * Used for devices with external radios.
3152 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003153static const char *ath9k_hw_rf_name(u16 rf_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003154{
3155 int i;
3156
3157 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3158 if (ath_rf_names[i].version == rf_version) {
3159 return ath_rf_names[i].name;
3160 }
3161 }
3162
3163 return "????";
3164}
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003165
3166void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3167{
3168 int used;
3169
3170 /* chipsets >= AR9280 are single-chip */
Felix Fietkau7a370812010-09-22 12:34:52 +02003171 if (AR_SREV_9280_20_OR_LATER(ah)) {
Zefir Kurtisi5e88ba62013-09-05 14:11:57 +02003172 used = scnprintf(hw_name, len,
3173 "Atheros AR%s Rev:%x",
3174 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3175 ah->hw_version.macRev);
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003176 }
3177 else {
Zefir Kurtisi5e88ba62013-09-05 14:11:57 +02003178 used = scnprintf(hw_name, len,
3179 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3180 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3181 ah->hw_version.macRev,
3182 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3183 & AR_RADIO_SREV_MAJOR)),
3184 ah->hw_version.phyRev);
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003185 }
3186
3187 hw_name[used] = '\0';
3188}
3189EXPORT_SYMBOL(ath9k_hw_name);