Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Switch a MMU context. |
| 3 | * |
| 4 | * This file is subject to the terms and conditions of the GNU General Public |
| 5 | * License. See the file "COPYING" in the main directory of this archive |
| 6 | * for more details. |
| 7 | * |
| 8 | * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle |
| 9 | * Copyright (C) 1999 Silicon Graphics, Inc. |
| 10 | */ |
| 11 | #ifndef _ASM_MMU_CONTEXT_H |
| 12 | #define _ASM_MMU_CONTEXT_H |
| 13 | |
| 14 | #include <linux/errno.h> |
| 15 | #include <linux/sched.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 16 | #include <linux/smp.h> |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 17 | #include <linux/slab.h> |
| 18 | #include <asm/cacheflush.h> |
Ralf Baechle | c2ea1d5 | 2009-10-13 23:23:28 +0200 | [diff] [blame] | 19 | #include <asm/hazards.h> |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 20 | #include <asm/tlbflush.h> |
| 21 | #ifdef CONFIG_MIPS_MT_SMTC |
| 22 | #include <asm/mipsmtregs.h> |
| 23 | #include <asm/smtc.h> |
| 24 | #endif /* SMTC */ |
| 25 | #include <asm-generic/mm_hooks.h> |
| 26 | |
Ralf Baechle | 0bfbf6a | 2013-03-21 11:28:10 +0100 | [diff] [blame] | 27 | #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ |
| 28 | do { \ |
Jayachandran C | 6ba045f | 2013-06-23 17:16:19 +0000 | [diff] [blame] | 29 | extern void tlbmiss_handler_setup_pgd(unsigned long); \ |
Ralf Baechle | 0bfbf6a | 2013-03-21 11:28:10 +0100 | [diff] [blame] | 30 | tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ |
| 31 | } while (0) |
David Daney | 8262228 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 32 | |
Jayachandran C | f4ae17a | 2013-09-25 16:28:04 +0530 | [diff] [blame] | 33 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
David Daney | 8262228 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 34 | #define TLBMISS_HANDLER_SETUP() \ |
| 35 | do { \ |
| 36 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ |
Jayachandran C | c2377a4 | 2013-08-11 17:10:16 +0530 | [diff] [blame] | 37 | write_c0_xcontext((unsigned long) smp_processor_id() << \ |
| 38 | SMP_CPUID_REGSHIFT); \ |
David Daney | 8262228 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 39 | } while (0) |
| 40 | |
Jayachandran C | c2377a4 | 2013-08-11 17:10:16 +0530 | [diff] [blame] | 41 | #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ |
David Daney | 8262228 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 42 | |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 43 | /* |
| 44 | * For the fast tlb miss handlers, we keep a per cpu array of pointers |
| 45 | * to the current pgd for each processor. Also, the proc. id is stuffed |
| 46 | * into the context register. |
| 47 | */ |
| 48 | extern unsigned long pgd_current[]; |
| 49 | |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 50 | #define TLBMISS_HANDLER_SETUP() \ |
Jayachandran C | c2377a4 | 2013-08-11 17:10:16 +0530 | [diff] [blame] | 51 | write_c0_context((unsigned long) smp_processor_id() << \ |
| 52 | SMP_CPUID_REGSHIFT); \ |
Ralf Baechle | c2ea1d5 | 2009-10-13 23:23:28 +0200 | [diff] [blame] | 53 | back_to_back_c0_hazard(); \ |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 54 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) |
David Daney | 8262228 | 2009-10-14 12:16:56 -0700 | [diff] [blame] | 55 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 56 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 57 | |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 58 | #define ASID_INC 0x40 |
| 59 | #define ASID_MASK 0xfc0 |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 60 | |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 61 | #elif defined(CONFIG_CPU_R8000) |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 62 | |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 63 | #define ASID_INC 0x10 |
| 64 | #define ASID_MASK 0xff0 |
| 65 | |
| 66 | #elif defined(CONFIG_MIPS_MT_SMTC) |
| 67 | |
| 68 | #define ASID_INC 0x1 |
| 69 | extern unsigned long smtc_asid_mask; |
| 70 | #define ASID_MASK (smtc_asid_mask) |
| 71 | #define HW_ASID_MASK 0xff |
| 72 | /* End SMTC/34K debug hack */ |
| 73 | #else /* FIXME: not correct for R6000 */ |
| 74 | |
| 75 | #define ASID_INC 0x1 |
| 76 | #define ASID_MASK 0xff |
| 77 | |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 78 | #endif |
| 79 | |
David Daney | c52d0d3 | 2010-02-18 16:13:04 -0800 | [diff] [blame] | 80 | #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 81 | #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 82 | #define asid_cache(cpu) (cpu_data[cpu].asid_cache) |
| 83 | |
| 84 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) |
| 85 | { |
| 86 | } |
| 87 | |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 88 | /* |
| 89 | * All unused by hardware upper bits will be considered |
| 90 | * as a software asid extension. |
| 91 | */ |
| 92 | #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) |
| 93 | #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) |
| 94 | |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 95 | #ifndef CONFIG_MIPS_MT_SMTC |
| 96 | /* Normal, classic MIPS get_new_mmu_context */ |
| 97 | static inline void |
| 98 | get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) |
| 99 | { |
Sanjay Lal | f9afbd4 | 2012-11-21 18:34:11 -0800 | [diff] [blame] | 100 | extern void kvm_local_flush_tlb_all(void); |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 101 | unsigned long asid = asid_cache(cpu); |
| 102 | |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 103 | if (! ((asid += ASID_INC) & ASID_MASK) ) { |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 104 | if (cpu_has_vtag_icache) |
| 105 | flush_icache_all(); |
Markos Chandras | d414976 | 2013-06-10 12:16:16 +0000 | [diff] [blame] | 106 | #ifdef CONFIG_KVM |
Sanjay Lal | f9afbd4 | 2012-11-21 18:34:11 -0800 | [diff] [blame] | 107 | kvm_local_flush_tlb_all(); /* start new asid cycle */ |
| 108 | #else |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 109 | local_flush_tlb_all(); /* start new asid cycle */ |
Sanjay Lal | f9afbd4 | 2012-11-21 18:34:11 -0800 | [diff] [blame] | 110 | #endif |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 111 | if (!asid) /* fix version if needed */ |
| 112 | asid = ASID_FIRST_VERSION; |
| 113 | } |
Sanjay Lal | f9afbd4 | 2012-11-21 18:34:11 -0800 | [diff] [blame] | 114 | |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 115 | cpu_context(cpu, mm) = asid_cache(cpu) = asid; |
| 116 | } |
| 117 | |
| 118 | #else /* CONFIG_MIPS_MT_SMTC */ |
| 119 | |
| 120 | #define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) |
| 121 | |
| 122 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 123 | |
| 124 | /* |
| 125 | * Initialize the context related info for a new mm_struct |
| 126 | * instance. |
| 127 | */ |
| 128 | static inline int |
| 129 | init_new_context(struct task_struct *tsk, struct mm_struct *mm) |
| 130 | { |
| 131 | int i; |
| 132 | |
Huacai Chen | 224786779 | 2013-03-17 11:50:14 +0000 | [diff] [blame] | 133 | for_each_possible_cpu(i) |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 134 | cpu_context(i, mm) = 0; |
| 135 | |
| 136 | return 0; |
| 137 | } |
| 138 | |
| 139 | static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 140 | struct task_struct *tsk) |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 141 | { |
| 142 | unsigned int cpu = smp_processor_id(); |
| 143 | unsigned long flags; |
| 144 | #ifdef CONFIG_MIPS_MT_SMTC |
| 145 | unsigned long oldasid; |
| 146 | unsigned long mtflags; |
| 147 | int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; |
| 148 | local_irq_save(flags); |
| 149 | mtflags = dvpe(); |
| 150 | #else /* Not SMTC */ |
| 151 | local_irq_save(flags); |
| 152 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 153 | |
| 154 | /* Check if our ASID is of an older version and thus invalid */ |
| 155 | if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) |
| 156 | get_new_mmu_context(next, cpu); |
| 157 | #ifdef CONFIG_MIPS_MT_SMTC |
| 158 | /* |
| 159 | * If the EntryHi ASID being replaced happens to be |
| 160 | * the value flagged at ASID recycling time as having |
| 161 | * an extended life, clear the bit showing it being |
| 162 | * in use by this "CPU", and if that's the last bit, |
| 163 | * free up the ASID value for use and flush any old |
| 164 | * instances of it from the TLB. |
| 165 | */ |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 166 | oldasid = (read_c0_entryhi() & ASID_MASK); |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 167 | if(smtc_live_asid[mytlb][oldasid]) { |
| 168 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); |
| 169 | if(smtc_live_asid[mytlb][oldasid] == 0) |
| 170 | smtc_flush_tlb_asid(oldasid); |
| 171 | } |
| 172 | /* |
| 173 | * Tread softly on EntryHi, and so long as we support |
| 174 | * having ASID_MASK smaller than the hardware maximum, |
| 175 | * make sure no "soft" bits become "hard"... |
| 176 | */ |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 177 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | |
Ralf Baechle | d30cecbc | 2009-05-27 17:29:37 +0100 | [diff] [blame] | 178 | cpu_asid(cpu, next)); |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 179 | ehb(); /* Make sure it propagates to TCStatus */ |
| 180 | evpe(mtflags); |
| 181 | #else |
Ralf Baechle | d30cecbc | 2009-05-27 17:29:37 +0100 | [diff] [blame] | 182 | write_c0_entryhi(cpu_asid(cpu, next)); |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 183 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 184 | TLBMISS_HANDLER_SETUP_PGD(next->pgd); |
| 185 | |
| 186 | /* |
| 187 | * Mark current->active_mm as not "active" anymore. |
| 188 | * We don't want to mislead possible IPI tlb flush routines. |
| 189 | */ |
Rusty Russell | 55b8cab | 2009-09-24 09:34:50 -0600 | [diff] [blame] | 190 | cpumask_clear_cpu(cpu, mm_cpumask(prev)); |
| 191 | cpumask_set_cpu(cpu, mm_cpumask(next)); |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 192 | |
| 193 | local_irq_restore(flags); |
| 194 | } |
| 195 | |
| 196 | /* |
| 197 | * Destroy context related info for an mm_struct that is about |
| 198 | * to be put to rest. |
| 199 | */ |
| 200 | static inline void destroy_context(struct mm_struct *mm) |
| 201 | { |
| 202 | } |
| 203 | |
| 204 | #define deactivate_mm(tsk, mm) do { } while (0) |
| 205 | |
| 206 | /* |
| 207 | * After we have set current->mm to a new value, this activates |
| 208 | * the context for the new mm so we see the new mappings. |
| 209 | */ |
| 210 | static inline void |
| 211 | activate_mm(struct mm_struct *prev, struct mm_struct *next) |
| 212 | { |
| 213 | unsigned long flags; |
| 214 | unsigned int cpu = smp_processor_id(); |
| 215 | |
| 216 | #ifdef CONFIG_MIPS_MT_SMTC |
| 217 | unsigned long oldasid; |
| 218 | unsigned long mtflags; |
| 219 | int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; |
| 220 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 221 | |
| 222 | local_irq_save(flags); |
| 223 | |
| 224 | /* Unconditionally get a new ASID. */ |
| 225 | get_new_mmu_context(next, cpu); |
| 226 | |
| 227 | #ifdef CONFIG_MIPS_MT_SMTC |
| 228 | /* See comments for similar code above */ |
| 229 | mtflags = dvpe(); |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 230 | oldasid = read_c0_entryhi() & ASID_MASK; |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 231 | if(smtc_live_asid[mytlb][oldasid]) { |
| 232 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); |
| 233 | if(smtc_live_asid[mytlb][oldasid] == 0) |
| 234 | smtc_flush_tlb_asid(oldasid); |
| 235 | } |
| 236 | /* See comments for similar code above */ |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 237 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | |
| 238 | cpu_asid(cpu, next)); |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 239 | ehb(); /* Make sure it propagates to TCStatus */ |
| 240 | evpe(mtflags); |
| 241 | #else |
Ralf Baechle | d30cecbc | 2009-05-27 17:29:37 +0100 | [diff] [blame] | 242 | write_c0_entryhi(cpu_asid(cpu, next)); |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 243 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 244 | TLBMISS_HANDLER_SETUP_PGD(next->pgd); |
| 245 | |
| 246 | /* mark mmu ownership change */ |
Rusty Russell | 55b8cab | 2009-09-24 09:34:50 -0600 | [diff] [blame] | 247 | cpumask_clear_cpu(cpu, mm_cpumask(prev)); |
| 248 | cpumask_set_cpu(cpu, mm_cpumask(next)); |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 249 | |
| 250 | local_irq_restore(flags); |
| 251 | } |
| 252 | |
| 253 | /* |
| 254 | * If mm is currently active_mm, we can't really drop it. Instead, |
| 255 | * we will get a new one for it. |
| 256 | */ |
| 257 | static inline void |
| 258 | drop_mmu_context(struct mm_struct *mm, unsigned cpu) |
| 259 | { |
| 260 | unsigned long flags; |
| 261 | #ifdef CONFIG_MIPS_MT_SMTC |
| 262 | unsigned long oldasid; |
| 263 | /* Can't use spinlock because called from TLB flush within DVPE */ |
| 264 | unsigned int prevvpe; |
| 265 | int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; |
| 266 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 267 | |
| 268 | local_irq_save(flags); |
| 269 | |
Rusty Russell | 55b8cab | 2009-09-24 09:34:50 -0600 | [diff] [blame] | 270 | if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 271 | get_new_mmu_context(mm, cpu); |
| 272 | #ifdef CONFIG_MIPS_MT_SMTC |
| 273 | /* See comments for similar code above */ |
| 274 | prevvpe = dvpe(); |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 275 | oldasid = (read_c0_entryhi() & ASID_MASK); |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 276 | if (smtc_live_asid[mytlb][oldasid]) { |
| 277 | smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); |
| 278 | if(smtc_live_asid[mytlb][oldasid] == 0) |
| 279 | smtc_flush_tlb_asid(oldasid); |
| 280 | } |
| 281 | /* See comments for similar code above */ |
David Daney | 48c4ac9 | 2013-05-13 13:56:44 -0700 | [diff] [blame] | 282 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
Ralf Baechle | 384740d | 2008-09-16 19:48:51 +0200 | [diff] [blame] | 283 | | cpu_asid(cpu, mm)); |
| 284 | ehb(); /* Make sure it propagates to TCStatus */ |
| 285 | evpe(prevvpe); |
| 286 | #else /* not CONFIG_MIPS_MT_SMTC */ |
| 287 | write_c0_entryhi(cpu_asid(cpu, mm)); |
| 288 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 289 | } else { |
| 290 | /* will get a new context next time */ |
| 291 | #ifndef CONFIG_MIPS_MT_SMTC |
| 292 | cpu_context(cpu, mm) = 0; |
| 293 | #else /* SMTC */ |
| 294 | int i; |
| 295 | |
| 296 | /* SMTC shares the TLB (and ASIDs) across VPEs */ |
| 297 | for_each_online_cpu(i) { |
| 298 | if((smtc_status & SMTC_TLB_SHARED) |
| 299 | || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) |
| 300 | cpu_context(i, mm) = 0; |
| 301 | } |
| 302 | #endif /* CONFIG_MIPS_MT_SMTC */ |
| 303 | } |
| 304 | local_irq_restore(flags); |
| 305 | } |
| 306 | |
| 307 | #endif /* _ASM_MMU_CONTEXT_H */ |