blob: d7006ef18a0da69be1ea8b7e78c1854616218fc5 [file] [log] [blame]
Thomas Gleixnercaab2772019-06-03 07:44:50 +02001// SPDX-License-Identifier: GPL-2.0-only
Marc Zyngier021f6532014-06-30 16:01:31 +01002/*
Marc Zyngier0edc23e2016-12-19 17:01:52 +00003 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
Marc Zyngier021f6532014-06-30 16:01:31 +01004 * Author: Marc Zyngier <marc.zyngier@arm.com>
Marc Zyngier021f6532014-06-30 16:01:31 +01005 */
6
Julien Grall68628bb2016-04-11 16:32:55 +01007#define pr_fmt(fmt) "GICv3: " fmt
8
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01009#include <linux/acpi.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010010#include <linux/cpu.h>
Sudeep Holla3708d522014-08-26 16:03:35 +010011#include <linux/cpu_pm.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010012#include <linux/delay.h>
13#include <linux/interrupt.h>
Tomasz Nowickiffa7d612016-01-19 14:11:15 +010014#include <linux/irqdomain.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010015#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/of_irq.h>
18#include <linux/percpu.h>
Julien Thierry101b35f2019-01-31 14:58:59 +000019#include <linux/refcount.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010020#include <linux/slab.h>
21
Joel Porquet41a83e062015-07-07 17:11:46 -040022#include <linux/irqchip.h>
Julien Grall1839e572016-04-11 16:32:57 +010023#include <linux/irqchip/arm-gic-common.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010024#include <linux/irqchip/arm-gic-v3.h>
Marc Zyngiere3825ba2016-04-11 09:57:54 +010025#include <linux/irqchip/irq-partition-percpu.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010026
27#include <asm/cputype.h>
28#include <asm/exception.h>
29#include <asm/smp_plat.h>
Marc Zyngier0b6a3da2015-08-26 17:00:42 +010030#include <asm/virt.h>
Marc Zyngier021f6532014-06-30 16:01:31 +010031
32#include "irq-gic-common.h"
Marc Zyngier021f6532014-06-30 16:01:31 +010033
Julien Thierryf32c9262019-01-31 14:58:58 +000034#define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
35
Srinivas Kandagatla9c8114c2018-12-10 13:56:32 +000036#define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
Marc Zyngierd01fd162020-03-11 11:56:49 +000037#define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
Srinivas Kandagatla9c8114c2018-12-10 13:56:32 +000038
Marc Zyngierf5c14342014-11-24 14:35:10 +000039struct redist_region {
40 void __iomem *redist_base;
41 phys_addr_t phys_base;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +010042 bool single_redist;
Marc Zyngierf5c14342014-11-24 14:35:10 +000043};
44
Marc Zyngier021f6532014-06-30 16:01:31 +010045struct gic_chip_data {
Marc Zyngiere3825ba2016-04-11 09:57:54 +010046 struct fwnode_handle *fwnode;
Marc Zyngier021f6532014-06-30 16:01:31 +010047 void __iomem *dist_base;
Marc Zyngierf5c14342014-11-24 14:35:10 +000048 struct redist_region *redist_regions;
49 struct rdists rdists;
Marc Zyngier021f6532014-06-30 16:01:31 +010050 struct irq_domain *domain;
51 u64 redist_stride;
Marc Zyngierf5c14342014-11-24 14:35:10 +000052 u32 nr_redist_regions;
Srinivas Kandagatla9c8114c2018-12-10 13:56:32 +000053 u64 flags;
Shanker Donthinenieda0d042017-10-06 10:24:00 -050054 bool has_rss;
Marc Zyngier1a60e1e2019-07-18 11:15:14 +010055 unsigned int ppi_nr;
Marc Zyngier52085d32019-07-18 13:05:17 +010056 struct partition_desc **ppi_descs;
Marc Zyngier021f6532014-06-30 16:01:31 +010057};
58
59static struct gic_chip_data gic_data __read_mostly;
Davidlohr Buesod01d3272018-03-26 14:09:25 -070060static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
Marc Zyngier021f6532014-06-30 16:01:31 +010061
Marc Zyngier211bddd2019-07-16 15:17:31 +010062#define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
Zenghui Yuc107d612019-09-18 06:57:30 +000063#define GIC_LINE_NR min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
Marc Zyngier211bddd2019-07-16 15:17:31 +010064#define GIC_ESPI_NR GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
65
Julien Thierryd98d0a92019-01-31 14:58:57 +000066/*
67 * The behaviours of RPR and PMR registers differ depending on the value of
68 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
69 * distributor and redistributors depends on whether security is enabled in the
70 * GIC.
71 *
72 * When security is enabled, non-secure priority values from the (re)distributor
73 * are presented to the GIC CPUIF as follow:
74 * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80;
75 *
76 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
77 * EL1 are subject to a similar operation thus matching the priorities presented
78 * from the (re)distributor when security is enabled.
79 *
80 * see GICv3/GICv4 Architecture Specification (IHI0069D):
81 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
82 * priorities.
83 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
84 * interrupt.
85 *
86 * For now, we only support pseudo-NMIs if we have non-secure view of
87 * priorities.
88 */
89static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
90
Marc Zyngierf2266502019-10-02 10:06:12 +010091/*
92 * Global static key controlling whether an update to PMR allowing more
93 * interrupts requires to be propagated to the redistributor (DSB SY).
94 * And this needs to be exported for modules to be able to enable
95 * interrupts...
96 */
97DEFINE_STATIC_KEY_FALSE(gic_pmr_sync);
98EXPORT_SYMBOL(gic_pmr_sync);
99
Julien Thierry101b35f2019-01-31 14:58:59 +0000100/* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
Marc Zyngier81a43272019-07-18 12:53:05 +0100101static refcount_t *ppi_nmi_refs;
Julien Thierry101b35f2019-01-31 14:58:59 +0000102
Julien Grall1839e572016-04-11 16:32:57 +0100103static struct gic_kvm_info gic_v3_kvm_info;
Shanker Donthinenieda0d042017-10-06 10:24:00 -0500104static DEFINE_PER_CPU(bool, has_rss);
Julien Grall1839e572016-04-11 16:32:57 +0100105
Shanker Donthinenieda0d042017-10-06 10:24:00 -0500106#define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4)
Marc Zyngierf5c14342014-11-24 14:35:10 +0000107#define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
108#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
Marc Zyngier021f6532014-06-30 16:01:31 +0100109#define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
110
111/* Our default, arbitrary priority value. Linux only uses one anyway. */
112#define DEFAULT_PMR_VALUE 0xf0
113
Marc Zyngiere91b0362019-07-16 14:41:40 +0100114enum gic_intid_range {
115 PPI_RANGE,
116 SPI_RANGE,
Marc Zyngier5f51f802019-07-18 13:19:25 +0100117 EPPI_RANGE,
Marc Zyngier211bddd2019-07-16 15:17:31 +0100118 ESPI_RANGE,
Marc Zyngiere91b0362019-07-16 14:41:40 +0100119 LPI_RANGE,
120 __INVALID_RANGE__
121};
122
123static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
124{
125 switch (hwirq) {
126 case 16 ... 31:
127 return PPI_RANGE;
128 case 32 ... 1019:
129 return SPI_RANGE;
Marc Zyngier5f51f802019-07-18 13:19:25 +0100130 case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63):
131 return EPPI_RANGE;
Marc Zyngier211bddd2019-07-16 15:17:31 +0100132 case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023):
133 return ESPI_RANGE;
Marc Zyngiere91b0362019-07-16 14:41:40 +0100134 case 8192 ... GENMASK(23, 0):
135 return LPI_RANGE;
136 default:
137 return __INVALID_RANGE__;
138 }
139}
140
141static enum gic_intid_range get_intid_range(struct irq_data *d)
142{
143 return __get_intid_range(d->hwirq);
144}
145
Marc Zyngier021f6532014-06-30 16:01:31 +0100146static inline unsigned int gic_irq(struct irq_data *d)
147{
148 return d->hwirq;
149}
150
151static inline int gic_irq_in_rdist(struct irq_data *d)
152{
Marc Zyngier5f51f802019-07-18 13:19:25 +0100153 enum gic_intid_range range = get_intid_range(d);
154 return range == PPI_RANGE || range == EPPI_RANGE;
Marc Zyngier021f6532014-06-30 16:01:31 +0100155}
156
157static inline void __iomem *gic_dist_base(struct irq_data *d)
158{
Marc Zyngiere91b0362019-07-16 14:41:40 +0100159 switch (get_intid_range(d)) {
160 case PPI_RANGE:
Marc Zyngier5f51f802019-07-18 13:19:25 +0100161 case EPPI_RANGE:
Marc Zyngiere91b0362019-07-16 14:41:40 +0100162 /* SGI+PPI -> SGI_base for this CPU */
Marc Zyngier021f6532014-06-30 16:01:31 +0100163 return gic_data_rdist_sgi_base();
164
Marc Zyngiere91b0362019-07-16 14:41:40 +0100165 case SPI_RANGE:
Marc Zyngier211bddd2019-07-16 15:17:31 +0100166 case ESPI_RANGE:
Marc Zyngiere91b0362019-07-16 14:41:40 +0100167 /* SPI -> dist_base */
Marc Zyngier021f6532014-06-30 16:01:31 +0100168 return gic_data.dist_base;
169
Marc Zyngiere91b0362019-07-16 14:41:40 +0100170 default:
171 return NULL;
172 }
Marc Zyngier021f6532014-06-30 16:01:31 +0100173}
174
175static void gic_do_wait_for_rwp(void __iomem *base)
176{
177 u32 count = 1000000; /* 1s! */
178
179 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
180 count--;
181 if (!count) {
182 pr_err_ratelimited("RWP timeout, gone fishing\n");
183 return;
184 }
185 cpu_relax();
186 udelay(1);
Daode Huang2c542422019-10-17 16:25:29 +0800187 }
Marc Zyngier021f6532014-06-30 16:01:31 +0100188}
189
190/* Wait for completion of a distributor change */
191static void gic_dist_wait_for_rwp(void)
192{
193 gic_do_wait_for_rwp(gic_data.dist_base);
194}
195
196/* Wait for completion of a redistributor change */
197static void gic_redist_wait_for_rwp(void)
198{
199 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
200}
201
Jean-Philippe Brucker7936e912015-10-01 13:47:14 +0100202#ifdef CONFIG_ARM64
Robert Richter6d4e11c2015-09-21 22:58:35 +0200203
204static u64 __maybe_unused gic_read_iar(void)
205{
Suzuki K Poulosea4023f682016-11-08 13:56:20 +0000206 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154))
Robert Richter6d4e11c2015-09-21 22:58:35 +0200207 return gic_read_iar_cavium_thunderx();
208 else
209 return gic_read_iar_common();
210}
Jean-Philippe Brucker7936e912015-10-01 13:47:14 +0100211#endif
Marc Zyngier021f6532014-06-30 16:01:31 +0100212
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100213static void gic_enable_redist(bool enable)
Marc Zyngier021f6532014-06-30 16:01:31 +0100214{
215 void __iomem *rbase;
216 u32 count = 1000000; /* 1s! */
217 u32 val;
218
Srinivas Kandagatla9c8114c2018-12-10 13:56:32 +0000219 if (gic_data.flags & FLAGS_WORKAROUND_GICR_WAKER_MSM8996)
220 return;
221
Marc Zyngier021f6532014-06-30 16:01:31 +0100222 rbase = gic_data_rdist_rd_base();
223
Marc Zyngier021f6532014-06-30 16:01:31 +0100224 val = readl_relaxed(rbase + GICR_WAKER);
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100225 if (enable)
226 /* Wake up this CPU redistributor */
227 val &= ~GICR_WAKER_ProcessorSleep;
228 else
229 val |= GICR_WAKER_ProcessorSleep;
Marc Zyngier021f6532014-06-30 16:01:31 +0100230 writel_relaxed(val, rbase + GICR_WAKER);
231
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100232 if (!enable) { /* Check that GICR_WAKER is writeable */
233 val = readl_relaxed(rbase + GICR_WAKER);
234 if (!(val & GICR_WAKER_ProcessorSleep))
235 return; /* No PM support in this redistributor */
236 }
237
Dan Carpenterd102eb52016-10-14 10:26:21 +0300238 while (--count) {
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100239 val = readl_relaxed(rbase + GICR_WAKER);
Andrew Jonescf1d9d12016-05-11 21:23:17 +0200240 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep))
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100241 break;
Marc Zyngier021f6532014-06-30 16:01:31 +0100242 cpu_relax();
243 udelay(1);
Daode Huang2c542422019-10-17 16:25:29 +0800244 }
Sudeep Hollaa2c22512014-08-26 16:03:34 +0100245 if (!count)
246 pr_err_ratelimited("redistributor failed to %s...\n",
247 enable ? "wakeup" : "sleep");
Marc Zyngier021f6532014-06-30 16:01:31 +0100248}
249
250/*
251 * Routines to disable, enable, EOI and route interrupts
252 */
Marc Zyngiere91b0362019-07-16 14:41:40 +0100253static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index)
254{
255 switch (get_intid_range(d)) {
256 case PPI_RANGE:
257 case SPI_RANGE:
258 *index = d->hwirq;
259 return offset;
Marc Zyngier5f51f802019-07-18 13:19:25 +0100260 case EPPI_RANGE:
261 /*
262 * Contrary to the ESPI range, the EPPI range is contiguous
263 * to the PPI range in the registers, so let's adjust the
264 * displacement accordingly. Consistency is overrated.
265 */
266 *index = d->hwirq - EPPI_BASE_INTID + 32;
267 return offset;
Marc Zyngier211bddd2019-07-16 15:17:31 +0100268 case ESPI_RANGE:
269 *index = d->hwirq - ESPI_BASE_INTID;
270 switch (offset) {
271 case GICD_ISENABLER:
272 return GICD_ISENABLERnE;
273 case GICD_ICENABLER:
274 return GICD_ICENABLERnE;
275 case GICD_ISPENDR:
276 return GICD_ISPENDRnE;
277 case GICD_ICPENDR:
278 return GICD_ICPENDRnE;
279 case GICD_ISACTIVER:
280 return GICD_ISACTIVERnE;
281 case GICD_ICACTIVER:
282 return GICD_ICACTIVERnE;
283 case GICD_IPRIORITYR:
284 return GICD_IPRIORITYRnE;
285 case GICD_ICFGR:
286 return GICD_ICFGRnE;
287 case GICD_IROUTER:
288 return GICD_IROUTERnE;
289 default:
290 break;
291 }
292 break;
Marc Zyngiere91b0362019-07-16 14:41:40 +0100293 default:
294 break;
295 }
296
297 WARN_ON(1);
298 *index = d->hwirq;
299 return offset;
300}
301
Marc Zyngierb594c6e2015-03-18 11:01:24 +0000302static int gic_peek_irq(struct irq_data *d, u32 offset)
303{
Marc Zyngierb594c6e2015-03-18 11:01:24 +0000304 void __iomem *base;
Marc Zyngiere91b0362019-07-16 14:41:40 +0100305 u32 index, mask;
306
307 offset = convert_offset_index(d, offset, &index);
308 mask = 1 << (index % 32);
Marc Zyngierb594c6e2015-03-18 11:01:24 +0000309
310 if (gic_irq_in_rdist(d))
311 base = gic_data_rdist_sgi_base();
312 else
313 base = gic_data.dist_base;
314
Marc Zyngiere91b0362019-07-16 14:41:40 +0100315 return !!(readl_relaxed(base + offset + (index / 32) * 4) & mask);
Marc Zyngierb594c6e2015-03-18 11:01:24 +0000316}
317
Marc Zyngier021f6532014-06-30 16:01:31 +0100318static void gic_poke_irq(struct irq_data *d, u32 offset)
319{
Marc Zyngier021f6532014-06-30 16:01:31 +0100320 void (*rwp_wait)(void);
321 void __iomem *base;
Marc Zyngiere91b0362019-07-16 14:41:40 +0100322 u32 index, mask;
323
324 offset = convert_offset_index(d, offset, &index);
325 mask = 1 << (index % 32);
Marc Zyngier021f6532014-06-30 16:01:31 +0100326
327 if (gic_irq_in_rdist(d)) {
328 base = gic_data_rdist_sgi_base();
329 rwp_wait = gic_redist_wait_for_rwp;
330 } else {
331 base = gic_data.dist_base;
332 rwp_wait = gic_dist_wait_for_rwp;
333 }
334
Marc Zyngiere91b0362019-07-16 14:41:40 +0100335 writel_relaxed(mask, base + offset + (index / 32) * 4);
Marc Zyngier021f6532014-06-30 16:01:31 +0100336 rwp_wait();
337}
338
Marc Zyngier021f6532014-06-30 16:01:31 +0100339static void gic_mask_irq(struct irq_data *d)
340{
341 gic_poke_irq(d, GICD_ICENABLER);
342}
343
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100344static void gic_eoimode1_mask_irq(struct irq_data *d)
345{
346 gic_mask_irq(d);
Marc Zyngier530bf352015-08-26 17:00:43 +0100347 /*
348 * When masking a forwarded interrupt, make sure it is
349 * deactivated as well.
350 *
351 * This ensures that an interrupt that is getting
352 * disabled/masked will not get "stuck", because there is
353 * noone to deactivate it (guest is being terminated).
354 */
Thomas Gleixner4df7f542015-09-15 13:19:16 +0200355 if (irqd_is_forwarded_to_vcpu(d))
Marc Zyngier530bf352015-08-26 17:00:43 +0100356 gic_poke_irq(d, GICD_ICACTIVER);
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100357}
358
Marc Zyngier021f6532014-06-30 16:01:31 +0100359static void gic_unmask_irq(struct irq_data *d)
360{
361 gic_poke_irq(d, GICD_ISENABLER);
362}
363
Julien Thierryd98d0a92019-01-31 14:58:57 +0000364static inline bool gic_supports_nmi(void)
365{
366 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
367 static_branch_likely(&supports_pseudo_nmis);
368}
369
Marc Zyngierb594c6e2015-03-18 11:01:24 +0000370static int gic_irq_set_irqchip_state(struct irq_data *d,
371 enum irqchip_irq_state which, bool val)
372{
373 u32 reg;
374
Marc Zyngier211bddd2019-07-16 15:17:31 +0100375 if (d->hwirq >= 8192) /* PPI/SPI only */
Marc Zyngierb594c6e2015-03-18 11:01:24 +0000376 return -EINVAL;
377
378 switch (which) {
379 case IRQCHIP_STATE_PENDING:
380 reg = val ? GICD_ISPENDR : GICD_ICPENDR;
381 break;
382
383 case IRQCHIP_STATE_ACTIVE:
384 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER;
385 break;
386
387 case IRQCHIP_STATE_MASKED:
388 reg = val ? GICD_ICENABLER : GICD_ISENABLER;
389 break;
390
391 default:
392 return -EINVAL;
393 }
394
395 gic_poke_irq(d, reg);
396 return 0;
397}
398
399static int gic_irq_get_irqchip_state(struct irq_data *d,
400 enum irqchip_irq_state which, bool *val)
401{
Marc Zyngier211bddd2019-07-16 15:17:31 +0100402 if (d->hwirq >= 8192) /* PPI/SPI only */
Marc Zyngierb594c6e2015-03-18 11:01:24 +0000403 return -EINVAL;
404
405 switch (which) {
406 case IRQCHIP_STATE_PENDING:
407 *val = gic_peek_irq(d, GICD_ISPENDR);
408 break;
409
410 case IRQCHIP_STATE_ACTIVE:
411 *val = gic_peek_irq(d, GICD_ISACTIVER);
412 break;
413
414 case IRQCHIP_STATE_MASKED:
415 *val = !gic_peek_irq(d, GICD_ISENABLER);
416 break;
417
418 default:
419 return -EINVAL;
420 }
421
422 return 0;
423}
424
Julien Thierry101b35f2019-01-31 14:58:59 +0000425static void gic_irq_set_prio(struct irq_data *d, u8 prio)
426{
427 void __iomem *base = gic_dist_base(d);
Marc Zyngiere91b0362019-07-16 14:41:40 +0100428 u32 offset, index;
Julien Thierry101b35f2019-01-31 14:58:59 +0000429
Marc Zyngiere91b0362019-07-16 14:41:40 +0100430 offset = convert_offset_index(d, GICD_IPRIORITYR, &index);
431
432 writeb_relaxed(prio, base + offset + index);
Julien Thierry101b35f2019-01-31 14:58:59 +0000433}
434
Marc Zyngier81a43272019-07-18 12:53:05 +0100435static u32 gic_get_ppi_index(struct irq_data *d)
436{
437 switch (get_intid_range(d)) {
438 case PPI_RANGE:
439 return d->hwirq - 16;
Marc Zyngier5f51f802019-07-18 13:19:25 +0100440 case EPPI_RANGE:
441 return d->hwirq - EPPI_BASE_INTID + 16;
Marc Zyngier81a43272019-07-18 12:53:05 +0100442 default:
443 unreachable();
444 }
445}
446
Julien Thierry101b35f2019-01-31 14:58:59 +0000447static int gic_irq_nmi_setup(struct irq_data *d)
448{
449 struct irq_desc *desc = irq_to_desc(d->irq);
450
451 if (!gic_supports_nmi())
452 return -EINVAL;
453
454 if (gic_peek_irq(d, GICD_ISENABLER)) {
455 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
456 return -EINVAL;
457 }
458
459 /*
460 * A secondary irq_chip should be in charge of LPI request,
461 * it should not be possible to get there
462 */
463 if (WARN_ON(gic_irq(d) >= 8192))
464 return -EINVAL;
465
466 /* desc lock should already be held */
Marc Zyngier81a43272019-07-18 12:53:05 +0100467 if (gic_irq_in_rdist(d)) {
468 u32 idx = gic_get_ppi_index(d);
469
Julien Thierry101b35f2019-01-31 14:58:59 +0000470 /* Setting up PPI as NMI, only switch handler for first NMI */
Marc Zyngier81a43272019-07-18 12:53:05 +0100471 if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
472 refcount_set(&ppi_nmi_refs[idx], 1);
Julien Thierry101b35f2019-01-31 14:58:59 +0000473 desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
474 }
475 } else {
476 desc->handle_irq = handle_fasteoi_nmi;
477 }
478
479 gic_irq_set_prio(d, GICD_INT_NMI_PRI);
480
481 return 0;
482}
483
484static void gic_irq_nmi_teardown(struct irq_data *d)
485{
486 struct irq_desc *desc = irq_to_desc(d->irq);
487
488 if (WARN_ON(!gic_supports_nmi()))
489 return;
490
491 if (gic_peek_irq(d, GICD_ISENABLER)) {
492 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq);
493 return;
494 }
495
496 /*
497 * A secondary irq_chip should be in charge of LPI request,
498 * it should not be possible to get there
499 */
500 if (WARN_ON(gic_irq(d) >= 8192))
501 return;
502
503 /* desc lock should already be held */
Marc Zyngier81a43272019-07-18 12:53:05 +0100504 if (gic_irq_in_rdist(d)) {
505 u32 idx = gic_get_ppi_index(d);
506
Julien Thierry101b35f2019-01-31 14:58:59 +0000507 /* Tearing down NMI, only switch handler for last NMI */
Marc Zyngier81a43272019-07-18 12:53:05 +0100508 if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
Julien Thierry101b35f2019-01-31 14:58:59 +0000509 desc->handle_irq = handle_percpu_devid_irq;
510 } else {
511 desc->handle_irq = handle_fasteoi_irq;
512 }
513
514 gic_irq_set_prio(d, GICD_INT_DEF_PRI);
515}
516
Marc Zyngier021f6532014-06-30 16:01:31 +0100517static void gic_eoi_irq(struct irq_data *d)
518{
519 gic_write_eoir(gic_irq(d));
520}
521
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100522static void gic_eoimode1_eoi_irq(struct irq_data *d)
523{
524 /*
Marc Zyngier530bf352015-08-26 17:00:43 +0100525 * No need to deactivate an LPI, or an interrupt that
526 * is is getting forwarded to a vcpu.
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100527 */
Thomas Gleixner4df7f542015-09-15 13:19:16 +0200528 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100529 return;
530 gic_write_dir(gic_irq(d));
531}
532
Marc Zyngier021f6532014-06-30 16:01:31 +0100533static int gic_set_type(struct irq_data *d, unsigned int type)
534{
Marc Zyngier5f51f802019-07-18 13:19:25 +0100535 enum gic_intid_range range;
Marc Zyngier021f6532014-06-30 16:01:31 +0100536 unsigned int irq = gic_irq(d);
537 void (*rwp_wait)(void);
538 void __iomem *base;
Marc Zyngiere91b0362019-07-16 14:41:40 +0100539 u32 offset, index;
Marc Zyngier13d22e22019-07-16 14:35:17 +0100540 int ret;
Marc Zyngier021f6532014-06-30 16:01:31 +0100541
542 /* Interrupt configuration for SGIs can't be changed */
543 if (irq < 16)
544 return -EINVAL;
545
Marc Zyngier5f51f802019-07-18 13:19:25 +0100546 range = get_intid_range(d);
547
Liviu Dudaufb7e7de2015-01-20 16:52:59 +0000548 /* SPIs have restrictions on the supported types */
Marc Zyngier5f51f802019-07-18 13:19:25 +0100549 if ((range == SPI_RANGE || range == ESPI_RANGE) &&
550 type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
Marc Zyngier021f6532014-06-30 16:01:31 +0100551 return -EINVAL;
552
553 if (gic_irq_in_rdist(d)) {
554 base = gic_data_rdist_sgi_base();
555 rwp_wait = gic_redist_wait_for_rwp;
556 } else {
557 base = gic_data.dist_base;
558 rwp_wait = gic_dist_wait_for_rwp;
559 }
560
Marc Zyngiere91b0362019-07-16 14:41:40 +0100561 offset = convert_offset_index(d, GICD_ICFGR, &index);
Marc Zyngier13d22e22019-07-16 14:35:17 +0100562
Marc Zyngiere91b0362019-07-16 14:41:40 +0100563 ret = gic_configure_irq(index, type, base + offset, rwp_wait);
Marc Zyngier5f51f802019-07-18 13:19:25 +0100564 if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) {
Marc Zyngier13d22e22019-07-16 14:35:17 +0100565 /* Misconfigured PPIs are usually not fatal */
Marc Zyngier5f51f802019-07-18 13:19:25 +0100566 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
Marc Zyngier13d22e22019-07-16 14:35:17 +0100567 ret = 0;
568 }
569
570 return ret;
Marc Zyngier021f6532014-06-30 16:01:31 +0100571}
572
Marc Zyngier530bf352015-08-26 17:00:43 +0100573static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
574{
Thomas Gleixner4df7f542015-09-15 13:19:16 +0200575 if (vcpu)
576 irqd_set_forwarded_to_vcpu(d);
577 else
578 irqd_clr_forwarded_to_vcpu(d);
Marc Zyngier530bf352015-08-26 17:00:43 +0100579 return 0;
580}
581
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100582static u64 gic_mpidr_to_affinity(unsigned long mpidr)
Marc Zyngier021f6532014-06-30 16:01:31 +0100583{
584 u64 aff;
585
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100586 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 |
Marc Zyngier021f6532014-06-30 16:01:31 +0100587 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
588 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
589 MPIDR_AFFINITY_LEVEL(mpidr, 0));
590
591 return aff;
592}
593
Julien Thierryf32c9262019-01-31 14:58:58 +0000594static void gic_deactivate_unhandled(u32 irqnr)
595{
596 if (static_branch_likely(&supports_deactivate_key)) {
597 if (irqnr < 8192)
598 gic_write_dir(irqnr);
599 } else {
600 gic_write_eoir(irqnr);
601 }
602}
603
604static inline void gic_handle_nmi(u32 irqnr, struct pt_regs *regs)
605{
Julien Thierry17ce3022019-06-11 10:38:09 +0100606 bool irqs_enabled = interrupts_enabled(regs);
Julien Thierryf32c9262019-01-31 14:58:58 +0000607 int err;
608
Julien Thierry17ce3022019-06-11 10:38:09 +0100609 if (irqs_enabled)
610 nmi_enter();
611
Julien Thierryf32c9262019-01-31 14:58:58 +0000612 if (static_branch_likely(&supports_deactivate_key))
613 gic_write_eoir(irqnr);
614 /*
615 * Leave the PSR.I bit set to prevent other NMIs to be
616 * received while handling this one.
617 * PSR.I will be restored when we ERET to the
618 * interrupted context.
619 */
620 err = handle_domain_nmi(gic_data.domain, irqnr, regs);
621 if (err)
622 gic_deactivate_unhandled(irqnr);
Julien Thierry17ce3022019-06-11 10:38:09 +0100623
624 if (irqs_enabled)
625 nmi_exit();
Julien Thierryf32c9262019-01-31 14:58:58 +0000626}
627
Marc Zyngier021f6532014-06-30 16:01:31 +0100628static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
629{
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100630 u32 irqnr;
Marc Zyngier021f6532014-06-30 16:01:31 +0100631
Julien Thierry342677d2018-08-28 16:51:29 +0100632 irqnr = gic_read_iar();
Marc Zyngier021f6532014-06-30 16:01:31 +0100633
Julien Thierryf32c9262019-01-31 14:58:58 +0000634 if (gic_supports_nmi() &&
635 unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) {
636 gic_handle_nmi(irqnr, regs);
637 return;
638 }
639
Julien Thierry3f1f3232019-01-31 14:58:44 +0000640 if (gic_prio_masking_enabled()) {
641 gic_pmr_mask_irqs();
642 gic_arch_enable_irqs();
643 }
644
Marc Zyngier211bddd2019-07-16 15:17:31 +0100645 /* Check for special IDs first */
646 if ((irqnr >= 1020 && irqnr <= 1023))
647 return;
648
649 /* Treat anything but SGIs in a uniform way */
650 if (likely(irqnr > 15)) {
Julien Thierry342677d2018-08-28 16:51:29 +0100651 int err;
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100652
Julien Thierry342677d2018-08-28 16:51:29 +0100653 if (static_branch_likely(&supports_deactivate_key))
Marc Zyngier021f6532014-06-30 16:01:31 +0100654 gic_write_eoir(irqnr);
Julien Thierry342677d2018-08-28 16:51:29 +0100655 else
656 isb();
657
658 err = handle_domain_irq(gic_data.domain, irqnr, regs);
659 if (err) {
660 WARN_ONCE(true, "Unexpected interrupt received!\n");
Julien Thierryf32c9262019-01-31 14:58:58 +0000661 gic_deactivate_unhandled(irqnr);
Marc Zyngier021f6532014-06-30 16:01:31 +0100662 }
Julien Thierry342677d2018-08-28 16:51:29 +0100663 return;
664 }
665 if (irqnr < 16) {
666 gic_write_eoir(irqnr);
667 if (static_branch_likely(&supports_deactivate_key))
668 gic_write_dir(irqnr);
669#ifdef CONFIG_SMP
670 /*
671 * Unlike GICv2, we don't need an smp_rmb() here.
672 * The control dependency from gic_read_iar to
673 * the ISB in gic_write_eoir is enough to ensure
674 * that any shared data read by handle_IPI will
675 * be read after the ACK.
676 */
677 handle_IPI(irqnr, regs);
678#else
679 WARN_ONCE(true, "Unexpected SGI received!\n");
680#endif
681 }
Marc Zyngier021f6532014-06-30 16:01:31 +0100682}
683
Julien Thierryb5cf6072019-01-31 14:58:54 +0000684static u32 gic_get_pribits(void)
685{
686 u32 pribits;
687
688 pribits = gic_read_ctlr();
689 pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
690 pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
691 pribits++;
692
693 return pribits;
694}
695
696static bool gic_has_group0(void)
697{
698 u32 val;
Julien Thierrye7932182019-01-31 14:58:55 +0000699 u32 old_pmr;
700
701 old_pmr = gic_read_pmr();
Julien Thierryb5cf6072019-01-31 14:58:54 +0000702
703 /*
704 * Let's find out if Group0 is under control of EL3 or not by
705 * setting the highest possible, non-zero priority in PMR.
706 *
707 * If SCR_EL3.FIQ is set, the priority gets shifted down in
708 * order for the CPU interface to set bit 7, and keep the
709 * actual priority in the non-secure range. In the process, it
710 * looses the least significant bit and the actual priority
711 * becomes 0x80. Reading it back returns 0, indicating that
712 * we're don't have access to Group0.
713 */
714 gic_write_pmr(BIT(8 - gic_get_pribits()));
715 val = gic_read_pmr();
716
Julien Thierrye7932182019-01-31 14:58:55 +0000717 gic_write_pmr(old_pmr);
718
Julien Thierryb5cf6072019-01-31 14:58:54 +0000719 return val != 0;
720}
721
Marc Zyngier021f6532014-06-30 16:01:31 +0100722static void __init gic_dist_init(void)
723{
724 unsigned int i;
725 u64 affinity;
726 void __iomem *base = gic_data.dist_base;
Marc Zyngier0b047582020-03-04 20:33:08 +0000727 u32 val;
Marc Zyngier021f6532014-06-30 16:01:31 +0100728
729 /* Disable the distributor */
730 writel_relaxed(0, base + GICD_CTLR);
731 gic_dist_wait_for_rwp();
732
Marc Zyngier7c9b9732016-05-06 19:41:56 +0100733 /*
734 * Configure SPIs as non-secure Group-1. This will only matter
735 * if the GIC only has a single security state. This will not
736 * do the right thing if the kernel is running in secure mode,
737 * but that's not the intended use case anyway.
738 */
Marc Zyngier211bddd2019-07-16 15:17:31 +0100739 for (i = 32; i < GIC_LINE_NR; i += 32)
Marc Zyngier7c9b9732016-05-06 19:41:56 +0100740 writel_relaxed(~0, base + GICD_IGROUPR + i / 8);
741
Marc Zyngier211bddd2019-07-16 15:17:31 +0100742 /* Extended SPI range, not handled by the GICv2/GICv3 common code */
743 for (i = 0; i < GIC_ESPI_NR; i += 32) {
744 writel_relaxed(~0U, base + GICD_ICENABLERnE + i / 8);
745 writel_relaxed(~0U, base + GICD_ICACTIVERnE + i / 8);
746 }
747
748 for (i = 0; i < GIC_ESPI_NR; i += 32)
749 writel_relaxed(~0U, base + GICD_IGROUPRnE + i / 8);
750
751 for (i = 0; i < GIC_ESPI_NR; i += 16)
752 writel_relaxed(0, base + GICD_ICFGRnE + i / 4);
753
754 for (i = 0; i < GIC_ESPI_NR; i += 4)
755 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRnE + i);
756
757 /* Now do the common stuff, and wait for the distributor to drain */
758 gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp);
Marc Zyngier021f6532014-06-30 16:01:31 +0100759
Marc Zyngier0b047582020-03-04 20:33:08 +0000760 val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1;
761 if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) {
762 pr_info("Enabling SGIs without active state\n");
763 val |= GICD_CTLR_nASSGIreq;
764 }
765
Marc Zyngier021f6532014-06-30 16:01:31 +0100766 /* Enable distributor with ARE, Group1 */
Marc Zyngier0b047582020-03-04 20:33:08 +0000767 writel_relaxed(val, base + GICD_CTLR);
Marc Zyngier021f6532014-06-30 16:01:31 +0100768
769 /*
770 * Set all global interrupts to the boot CPU only. ARE must be
771 * enabled.
772 */
773 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
Marc Zyngier211bddd2019-07-16 15:17:31 +0100774 for (i = 32; i < GIC_LINE_NR; i++)
Jean-Philippe Brucker72c97122015-10-01 13:47:16 +0100775 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8);
Marc Zyngier211bddd2019-07-16 15:17:31 +0100776
777 for (i = 0; i < GIC_ESPI_NR; i++)
778 gic_write_irouter(affinity, base + GICD_IROUTERnE + i * 8);
Marc Zyngier021f6532014-06-30 16:01:31 +0100779}
780
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000781static int gic_iterate_rdists(int (*fn)(struct redist_region *, void __iomem *))
Marc Zyngier021f6532014-06-30 16:01:31 +0100782{
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000783 int ret = -ENODEV;
Marc Zyngier021f6532014-06-30 16:01:31 +0100784 int i;
785
Marc Zyngierf5c14342014-11-24 14:35:10 +0000786 for (i = 0; i < gic_data.nr_redist_regions; i++) {
787 void __iomem *ptr = gic_data.redist_regions[i].redist_base;
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000788 u64 typer;
Marc Zyngier021f6532014-06-30 16:01:31 +0100789 u32 reg;
790
791 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK;
792 if (reg != GIC_PIDR2_ARCH_GICv3 &&
793 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */
794 pr_warn("No redistributor present @%p\n", ptr);
795 break;
796 }
797
798 do {
Jean-Philippe Brucker72c97122015-10-01 13:47:16 +0100799 typer = gic_read_typer(ptr + GICR_TYPER);
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000800 ret = fn(gic_data.redist_regions + i, ptr);
801 if (!ret)
Marc Zyngier021f6532014-06-30 16:01:31 +0100802 return 0;
Marc Zyngier021f6532014-06-30 16:01:31 +0100803
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +0100804 if (gic_data.redist_regions[i].single_redist)
805 break;
806
Marc Zyngier021f6532014-06-30 16:01:31 +0100807 if (gic_data.redist_stride) {
808 ptr += gic_data.redist_stride;
809 } else {
810 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */
811 if (typer & GICR_TYPER_VLPIS)
812 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */
813 }
814 } while (!(typer & GICR_TYPER_LAST));
815 }
816
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000817 return ret ? -ENODEV : 0;
818}
819
820static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr)
821{
822 unsigned long mpidr = cpu_logical_map(smp_processor_id());
823 u64 typer;
824 u32 aff;
825
826 /*
827 * Convert affinity to a 32bit value that can be matched to
828 * GICR_TYPER bits [63:32].
829 */
830 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 |
831 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 |
832 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 |
833 MPIDR_AFFINITY_LEVEL(mpidr, 0));
834
835 typer = gic_read_typer(ptr + GICR_TYPER);
836 if ((typer >> 32) == aff) {
837 u64 offset = ptr - region->redist_base;
Marc Zyngier9058a4e2020-03-04 20:33:12 +0000838 raw_spin_lock_init(&gic_data_rdist()->rd_lock);
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000839 gic_data_rdist_rd_base() = ptr;
840 gic_data_rdist()->phys_base = region->phys_base + offset;
841
842 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
843 smp_processor_id(), mpidr,
844 (int)(region - gic_data.redist_regions),
845 &gic_data_rdist()->phys_base);
846 return 0;
847 }
848
849 /* Try next one */
850 return 1;
851}
852
853static int gic_populate_rdist(void)
854{
855 if (gic_iterate_rdists(__gic_populate_rdist) == 0)
856 return 0;
857
Marc Zyngier021f6532014-06-30 16:01:31 +0100858 /* We couldn't even deal with ourselves... */
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +0100859 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
Marc Zyngier0d94ded2016-12-19 17:00:38 +0000860 smp_processor_id(),
861 (unsigned long)cpu_logical_map(smp_processor_id()));
Marc Zyngier021f6532014-06-30 16:01:31 +0100862 return -ENODEV;
863}
864
Marc Zyngier1a60e1e2019-07-18 11:15:14 +0100865static int __gic_update_rdist_properties(struct redist_region *region,
866 void __iomem *ptr)
Marc Zyngier0edc23e2016-12-19 17:01:52 +0000867{
868 u64 typer = gic_read_typer(ptr + GICR_TYPER);
Marc Zyngierb25319d2019-12-24 11:10:24 +0000869
Marc Zyngier0edc23e2016-12-19 17:01:52 +0000870 gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
Marc Zyngierb25319d2019-12-24 11:10:24 +0000871
872 /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */
873 gic_data.rdists.has_rvpeid &= !!(typer & GICR_TYPER_RVPEID);
874 gic_data.rdists.has_direct_lpi &= (!!(typer & GICR_TYPER_DirectLPIS) |
875 gic_data.rdists.has_rvpeid);
Marc Zyngier96806222020-04-10 11:13:26 +0100876 gic_data.rdists.has_vpend_valid_dirty &= !!(typer & GICR_TYPER_DIRTY);
Marc Zyngierb25319d2019-12-24 11:10:24 +0000877
878 /* Detect non-sensical configurations */
879 if (WARN_ON_ONCE(gic_data.rdists.has_rvpeid && !gic_data.rdists.has_vlpis)) {
880 gic_data.rdists.has_direct_lpi = false;
881 gic_data.rdists.has_vlpis = false;
882 gic_data.rdists.has_rvpeid = false;
883 }
884
Marc Zyngier5f51f802019-07-18 13:19:25 +0100885 gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr);
Marc Zyngier0edc23e2016-12-19 17:01:52 +0000886
887 return 1;
888}
889
Marc Zyngier1a60e1e2019-07-18 11:15:14 +0100890static void gic_update_rdist_properties(void)
Marc Zyngier0edc23e2016-12-19 17:01:52 +0000891{
Marc Zyngier1a60e1e2019-07-18 11:15:14 +0100892 gic_data.ppi_nr = UINT_MAX;
893 gic_iterate_rdists(__gic_update_rdist_properties);
894 if (WARN_ON(gic_data.ppi_nr == UINT_MAX))
895 gic_data.ppi_nr = 0;
896 pr_info("%d PPIs implemented\n", gic_data.ppi_nr);
Marc Zyngier96806222020-04-10 11:13:26 +0100897 if (gic_data.rdists.has_vlpis)
898 pr_info("GICv4 features: %s%s%s\n",
899 gic_data.rdists.has_direct_lpi ? "DirectLPI " : "",
900 gic_data.rdists.has_rvpeid ? "RVPEID " : "",
901 gic_data.rdists.has_vpend_valid_dirty ? "Valid+Dirty " : "");
Marc Zyngier0edc23e2016-12-19 17:01:52 +0000902}
903
Julien Thierryd98d0a92019-01-31 14:58:57 +0000904/* Check whether it's single security state view */
905static inline bool gic_dist_security_disabled(void)
906{
907 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS;
908}
909
Sudeep Holla3708d522014-08-26 16:03:35 +0100910static void gic_cpu_sys_reg_init(void)
Marc Zyngier021f6532014-06-30 16:01:31 +0100911{
Shanker Donthinenieda0d042017-10-06 10:24:00 -0500912 int i, cpu = smp_processor_id();
913 u64 mpidr = cpu_logical_map(cpu);
914 u64 need_rss = MPIDR_RS(mpidr);
Marc Zyngier33625282018-03-20 09:46:42 +0000915 bool group0;
Julien Thierryb5cf6072019-01-31 14:58:54 +0000916 u32 pribits;
Shanker Donthinenieda0d042017-10-06 10:24:00 -0500917
Marc Zyngier7cabd002015-09-30 11:48:01 +0100918 /*
919 * Need to check that the SRE bit has actually been set. If
920 * not, it means that SRE is disabled at EL2. We're going to
921 * die painfully, and there is nothing we can do about it.
922 *
923 * Kindly inform the luser.
924 */
925 if (!gic_enable_sre())
926 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
Marc Zyngier021f6532014-06-30 16:01:31 +0100927
Julien Thierryb5cf6072019-01-31 14:58:54 +0000928 pribits = gic_get_pribits();
Marc Zyngier33625282018-03-20 09:46:42 +0000929
Julien Thierryb5cf6072019-01-31 14:58:54 +0000930 group0 = gic_has_group0();
Marc Zyngier33625282018-03-20 09:46:42 +0000931
Marc Zyngier021f6532014-06-30 16:01:31 +0100932 /* Set priority mask register */
Julien Thierryd98d0a92019-01-31 14:58:57 +0000933 if (!gic_prio_masking_enabled()) {
Julien Thierrye7932182019-01-31 14:58:55 +0000934 write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
Julien Thierryd98d0a92019-01-31 14:58:57 +0000935 } else {
936 /*
937 * Mismatch configuration with boot CPU, the system is likely
938 * to die as interrupt masking will not work properly on all
939 * CPUs
940 */
941 WARN_ON(gic_supports_nmi() && group0 &&
942 !gic_dist_security_disabled());
943 }
Marc Zyngier021f6532014-06-30 16:01:31 +0100944
Daniel Thompson91ef8442016-08-19 17:13:09 +0100945 /*
946 * Some firmwares hand over to the kernel with the BPR changed from
947 * its reset value (and with a value large enough to prevent
948 * any pre-emptive interrupts from working at all). Writing a zero
949 * to BPR restores is reset value.
950 */
951 gic_write_bpr1(0);
952
Davidlohr Buesod01d3272018-03-26 14:09:25 -0700953 if (static_branch_likely(&supports_deactivate_key)) {
Marc Zyngier0b6a3da2015-08-26 17:00:42 +0100954 /* EOI drops priority only (mode 1) */
955 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop);
956 } else {
957 /* EOI deactivates interrupt too (mode 0) */
958 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir);
959 }
Marc Zyngier021f6532014-06-30 16:01:31 +0100960
Marc Zyngier33625282018-03-20 09:46:42 +0000961 /* Always whack Group0 before Group1 */
962 if (group0) {
963 switch(pribits) {
964 case 8:
965 case 7:
966 write_gicreg(0, ICC_AP0R3_EL1);
967 write_gicreg(0, ICC_AP0R2_EL1);
Anders Roxell52f8c8b2019-07-26 13:28:26 +0200968 /* Fall through */
Marc Zyngier33625282018-03-20 09:46:42 +0000969 case 6:
970 write_gicreg(0, ICC_AP0R1_EL1);
Anders Roxell52f8c8b2019-07-26 13:28:26 +0200971 /* Fall through */
Marc Zyngier33625282018-03-20 09:46:42 +0000972 case 5:
973 case 4:
974 write_gicreg(0, ICC_AP0R0_EL1);
975 }
Marc Zyngierd6062a62018-03-09 14:53:19 +0000976
Marc Zyngier33625282018-03-20 09:46:42 +0000977 isb();
978 }
979
980 switch(pribits) {
Marc Zyngierd6062a62018-03-09 14:53:19 +0000981 case 8:
982 case 7:
Marc Zyngierd6062a62018-03-09 14:53:19 +0000983 write_gicreg(0, ICC_AP1R3_EL1);
Marc Zyngierd6062a62018-03-09 14:53:19 +0000984 write_gicreg(0, ICC_AP1R2_EL1);
Anders Roxell52f8c8b2019-07-26 13:28:26 +0200985 /* Fall through */
Marc Zyngierd6062a62018-03-09 14:53:19 +0000986 case 6:
Marc Zyngierd6062a62018-03-09 14:53:19 +0000987 write_gicreg(0, ICC_AP1R1_EL1);
Anders Roxell52f8c8b2019-07-26 13:28:26 +0200988 /* Fall through */
Marc Zyngierd6062a62018-03-09 14:53:19 +0000989 case 5:
990 case 4:
Marc Zyngierd6062a62018-03-09 14:53:19 +0000991 write_gicreg(0, ICC_AP1R0_EL1);
992 }
993
994 isb();
995
Marc Zyngier021f6532014-06-30 16:01:31 +0100996 /* ... and let's hit the road... */
997 gic_write_grpen1(1);
Shanker Donthinenieda0d042017-10-06 10:24:00 -0500998
999 /* Keep the RSS capability status in per_cpu variable */
1000 per_cpu(has_rss, cpu) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS);
1001
1002 /* Check all the CPUs have capable of sending SGIs to other CPUs */
1003 for_each_online_cpu(i) {
1004 bool have_rss = per_cpu(has_rss, i) && per_cpu(has_rss, cpu);
1005
1006 need_rss |= MPIDR_RS(cpu_logical_map(i));
1007 if (need_rss && (!have_rss))
1008 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
1009 cpu, (unsigned long)mpidr,
1010 i, (unsigned long)cpu_logical_map(i));
1011 }
1012
1013 /**
1014 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
1015 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
1016 * UNPREDICTABLE choice of :
1017 * - The write is ignored.
1018 * - The RS field is treated as 0.
1019 */
1020 if (need_rss && (!gic_data.has_rss))
1021 pr_crit_once("RSS is required but GICD doesn't support it\n");
Marc Zyngier021f6532014-06-30 16:01:31 +01001022}
1023
Marc Zyngierf736d652018-02-25 11:27:04 +00001024static bool gicv3_nolpi;
1025
1026static int __init gicv3_nolpi_cfg(char *buf)
1027{
1028 return strtobool(buf, &gicv3_nolpi);
1029}
1030early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg);
1031
Marc Zyngierda33f312014-11-24 14:35:18 +00001032static int gic_dist_supports_lpis(void)
1033{
Marc Zyngierd38a71c2018-07-27 14:51:04 +01001034 return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) &&
1035 !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS) &&
1036 !gicv3_nolpi);
Marc Zyngierda33f312014-11-24 14:35:18 +00001037}
1038
Marc Zyngier021f6532014-06-30 16:01:31 +01001039static void gic_cpu_init(void)
1040{
1041 void __iomem *rbase;
Marc Zyngier1a60e1e2019-07-18 11:15:14 +01001042 int i;
Marc Zyngier021f6532014-06-30 16:01:31 +01001043
1044 /* Register ourselves with the rest of the world */
1045 if (gic_populate_rdist())
1046 return;
1047
Sudeep Hollaa2c22512014-08-26 16:03:34 +01001048 gic_enable_redist(true);
Marc Zyngier021f6532014-06-30 16:01:31 +01001049
Marc Zyngierad5a78d2019-07-25 15:30:51 +01001050 WARN((gic_data.ppi_nr > 16 || GIC_ESPI_NR != 0) &&
1051 !(gic_read_ctlr() & ICC_CTLR_EL1_ExtRange),
1052 "Distributor has extended ranges, but CPU%d doesn't\n",
1053 smp_processor_id());
1054
Marc Zyngier021f6532014-06-30 16:01:31 +01001055 rbase = gic_data_rdist_sgi_base();
1056
Marc Zyngier7c9b9732016-05-06 19:41:56 +01001057 /* Configure SGIs/PPIs as non-secure Group-1 */
Marc Zyngier1a60e1e2019-07-18 11:15:14 +01001058 for (i = 0; i < gic_data.ppi_nr + 16; i += 32)
1059 writel_relaxed(~0, rbase + GICR_IGROUPR0 + i / 8);
Marc Zyngier7c9b9732016-05-06 19:41:56 +01001060
Marc Zyngier1a60e1e2019-07-18 11:15:14 +01001061 gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp);
Marc Zyngier021f6532014-06-30 16:01:31 +01001062
Sudeep Holla3708d522014-08-26 16:03:35 +01001063 /* initialise system registers */
1064 gic_cpu_sys_reg_init();
Marc Zyngier021f6532014-06-30 16:01:31 +01001065}
1066
1067#ifdef CONFIG_SMP
Marc Zyngier021f6532014-06-30 16:01:31 +01001068
Shanker Donthinenieda0d042017-10-06 10:24:00 -05001069#define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
1070#define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL)
1071
Richard Cochran6670a6d2016-07-13 17:16:05 +00001072static int gic_starting_cpu(unsigned int cpu)
1073{
1074 gic_cpu_init();
Marc Zyngierd38a71c2018-07-27 14:51:04 +01001075
1076 if (gic_dist_supports_lpis())
1077 its_cpu_init();
1078
Richard Cochran6670a6d2016-07-13 17:16:05 +00001079 return 0;
1080}
Marc Zyngier021f6532014-06-30 16:01:31 +01001081
1082static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +01001083 unsigned long cluster_id)
Marc Zyngier021f6532014-06-30 16:01:31 +01001084{
James Morse727653d2016-09-19 18:29:15 +01001085 int next_cpu, cpu = *base_cpu;
Jean-Philippe Bruckerf6c86a42015-10-01 13:47:15 +01001086 unsigned long mpidr = cpu_logical_map(cpu);
Marc Zyngier021f6532014-06-30 16:01:31 +01001087 u16 tlist = 0;
1088
1089 while (cpu < nr_cpu_ids) {
Marc Zyngier021f6532014-06-30 16:01:31 +01001090 tlist |= 1 << (mpidr & 0xf);
1091
James Morse727653d2016-09-19 18:29:15 +01001092 next_cpu = cpumask_next(cpu, mask);
1093 if (next_cpu >= nr_cpu_ids)
Marc Zyngier021f6532014-06-30 16:01:31 +01001094 goto out;
James Morse727653d2016-09-19 18:29:15 +01001095 cpu = next_cpu;
Marc Zyngier021f6532014-06-30 16:01:31 +01001096
1097 mpidr = cpu_logical_map(cpu);
1098
Shanker Donthinenieda0d042017-10-06 10:24:00 -05001099 if (cluster_id != MPIDR_TO_SGI_CLUSTER_ID(mpidr)) {
Marc Zyngier021f6532014-06-30 16:01:31 +01001100 cpu--;
1101 goto out;
1102 }
1103 }
1104out:
1105 *base_cpu = cpu;
1106 return tlist;
1107}
1108
Andre Przywara7e580272014-11-12 13:46:06 +00001109#define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
1110 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
1111 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
1112
Marc Zyngier021f6532014-06-30 16:01:31 +01001113static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
1114{
1115 u64 val;
1116
Andre Przywara7e580272014-11-12 13:46:06 +00001117 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) |
1118 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) |
1119 irq << ICC_SGI1R_SGI_ID_SHIFT |
1120 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) |
Shanker Donthinenieda0d042017-10-06 10:24:00 -05001121 MPIDR_TO_SGI_RS(cluster_id) |
Andre Przywara7e580272014-11-12 13:46:06 +00001122 tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
Marc Zyngier021f6532014-06-30 16:01:31 +01001123
Mark Salterb6dd4d82018-02-02 09:20:29 -05001124 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
Marc Zyngier021f6532014-06-30 16:01:31 +01001125 gic_write_sgi1r(val);
1126}
1127
1128static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
1129{
1130 int cpu;
1131
1132 if (WARN_ON(irq >= 16))
1133 return;
1134
1135 /*
1136 * Ensure that stores to Normal memory are visible to the
1137 * other CPUs before issuing the IPI.
1138 */
Shanker Donthineni21ec30c2018-01-31 18:03:42 -06001139 wmb();
Marc Zyngier021f6532014-06-30 16:01:31 +01001140
Rusty Russellf9b531f2015-03-05 10:49:16 +10301141 for_each_cpu(cpu, mask) {
Shanker Donthinenieda0d042017-10-06 10:24:00 -05001142 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
Marc Zyngier021f6532014-06-30 16:01:31 +01001143 u16 tlist;
1144
1145 tlist = gic_compute_target_list(&cpu, mask, cluster_id);
1146 gic_send_sgi(cluster_id, tlist, irq);
1147 }
1148
1149 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
1150 isb();
1151}
1152
1153static void gic_smp_init(void)
1154{
1155 set_smp_cross_call(gic_raise_softirq);
Thomas Gleixner6896bcd2016-12-21 20:19:56 +01001156 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
Thomas Gleixner73c1b412016-12-21 20:19:54 +01001157 "irqchip/arm/gicv3:starting",
1158 gic_starting_cpu, NULL);
Marc Zyngier021f6532014-06-30 16:01:31 +01001159}
1160
1161static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1162 bool force)
1163{
Suzuki K Poulose65a30f82017-07-04 10:56:35 +01001164 unsigned int cpu;
Marc Zyngiere91b0362019-07-16 14:41:40 +01001165 u32 offset, index;
Marc Zyngier021f6532014-06-30 16:01:31 +01001166 void __iomem *reg;
1167 int enabled;
1168 u64 val;
1169
Suzuki K Poulose65a30f82017-07-04 10:56:35 +01001170 if (force)
1171 cpu = cpumask_first(mask_val);
1172 else
1173 cpu = cpumask_any_and(mask_val, cpu_online_mask);
1174
Suzuki K Poulose866d7c12017-06-30 10:58:28 +01001175 if (cpu >= nr_cpu_ids)
1176 return -EINVAL;
1177
Marc Zyngier021f6532014-06-30 16:01:31 +01001178 if (gic_irq_in_rdist(d))
1179 return -EINVAL;
1180
1181 /* If interrupt was enabled, disable it first */
1182 enabled = gic_peek_irq(d, GICD_ISENABLER);
1183 if (enabled)
1184 gic_mask_irq(d);
1185
Marc Zyngiere91b0362019-07-16 14:41:40 +01001186 offset = convert_offset_index(d, GICD_IROUTER, &index);
1187 reg = gic_dist_base(d) + offset + (index * 8);
Marc Zyngier021f6532014-06-30 16:01:31 +01001188 val = gic_mpidr_to_affinity(cpu_logical_map(cpu));
1189
Jean-Philippe Brucker72c97122015-10-01 13:47:16 +01001190 gic_write_irouter(val, reg);
Marc Zyngier021f6532014-06-30 16:01:31 +01001191
1192 /*
1193 * If the interrupt was enabled, enabled it again. Otherwise,
1194 * just wait for the distributor to have digested our changes.
1195 */
1196 if (enabled)
1197 gic_unmask_irq(d);
1198 else
1199 gic_dist_wait_for_rwp();
1200
Marc Zyngier956ae912017-08-18 09:39:17 +01001201 irq_data_update_effective_affinity(d, cpumask_of(cpu));
1202
Antoine Tenart0fc6fa22016-02-19 16:22:43 +01001203 return IRQ_SET_MASK_OK_DONE;
Marc Zyngier021f6532014-06-30 16:01:31 +01001204}
1205#else
1206#define gic_set_affinity NULL
1207#define gic_smp_init() do { } while(0)
1208#endif
1209
Sudeep Holla3708d522014-08-26 16:03:35 +01001210#ifdef CONFIG_CPU_PM
1211static int gic_cpu_pm_notifier(struct notifier_block *self,
1212 unsigned long cmd, void *v)
1213{
1214 if (cmd == CPU_PM_EXIT) {
Sudeep Hollaccd94322016-08-17 13:49:19 +01001215 if (gic_dist_security_disabled())
1216 gic_enable_redist(true);
Sudeep Holla3708d522014-08-26 16:03:35 +01001217 gic_cpu_sys_reg_init();
Sudeep Hollaccd94322016-08-17 13:49:19 +01001218 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) {
Sudeep Holla3708d522014-08-26 16:03:35 +01001219 gic_write_grpen1(0);
1220 gic_enable_redist(false);
1221 }
1222 return NOTIFY_OK;
1223}
1224
1225static struct notifier_block gic_cpu_pm_notifier_block = {
1226 .notifier_call = gic_cpu_pm_notifier,
1227};
1228
1229static void gic_cpu_pm_init(void)
1230{
1231 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block);
1232}
1233
1234#else
1235static inline void gic_cpu_pm_init(void) { }
1236#endif /* CONFIG_CPU_PM */
1237
Marc Zyngier021f6532014-06-30 16:01:31 +01001238static struct irq_chip gic_chip = {
1239 .name = "GICv3",
1240 .irq_mask = gic_mask_irq,
1241 .irq_unmask = gic_unmask_irq,
1242 .irq_eoi = gic_eoi_irq,
1243 .irq_set_type = gic_set_type,
1244 .irq_set_affinity = gic_set_affinity,
Marc Zyngierb594c6e2015-03-18 11:01:24 +00001245 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1246 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
Julien Thierry101b35f2019-01-31 14:58:59 +00001247 .irq_nmi_setup = gic_irq_nmi_setup,
1248 .irq_nmi_teardown = gic_irq_nmi_teardown,
Marc Zyngier4110b5c2018-08-17 09:18:01 +01001249 .flags = IRQCHIP_SET_TYPE_MASKED |
1250 IRQCHIP_SKIP_SET_WAKE |
1251 IRQCHIP_MASK_ON_SUSPEND,
Marc Zyngier021f6532014-06-30 16:01:31 +01001252};
1253
Marc Zyngier0b6a3da2015-08-26 17:00:42 +01001254static struct irq_chip gic_eoimode1_chip = {
1255 .name = "GICv3",
1256 .irq_mask = gic_eoimode1_mask_irq,
1257 .irq_unmask = gic_unmask_irq,
1258 .irq_eoi = gic_eoimode1_eoi_irq,
1259 .irq_set_type = gic_set_type,
1260 .irq_set_affinity = gic_set_affinity,
1261 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
1262 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
Marc Zyngier530bf352015-08-26 17:00:43 +01001263 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
Julien Thierry101b35f2019-01-31 14:58:59 +00001264 .irq_nmi_setup = gic_irq_nmi_setup,
1265 .irq_nmi_teardown = gic_irq_nmi_teardown,
Marc Zyngier4110b5c2018-08-17 09:18:01 +01001266 .flags = IRQCHIP_SET_TYPE_MASKED |
1267 IRQCHIP_SKIP_SET_WAKE |
1268 IRQCHIP_MASK_ON_SUSPEND,
Marc Zyngier0b6a3da2015-08-26 17:00:42 +01001269};
1270
Marc Zyngier021f6532014-06-30 16:01:31 +01001271static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1272 irq_hw_number_t hw)
1273{
Marc Zyngier0b6a3da2015-08-26 17:00:42 +01001274 struct irq_chip *chip = &gic_chip;
1275
Davidlohr Buesod01d3272018-03-26 14:09:25 -07001276 if (static_branch_likely(&supports_deactivate_key))
Marc Zyngier0b6a3da2015-08-26 17:00:42 +01001277 chip = &gic_eoimode1_chip;
1278
Marc Zyngiere91b0362019-07-16 14:41:40 +01001279 switch (__get_intid_range(hw)) {
1280 case PPI_RANGE:
Marc Zyngier5f51f802019-07-18 13:19:25 +01001281 case EPPI_RANGE:
Marc Zyngier021f6532014-06-30 16:01:31 +01001282 irq_set_percpu_devid(irq);
Marc Zyngier0b6a3da2015-08-26 17:00:42 +01001283 irq_domain_set_info(d, irq, hw, chip, d->host_data,
Marc Zyngier443acc42014-11-24 14:35:09 +00001284 handle_percpu_devid_irq, NULL, NULL);
Rob Herringd17cab42015-08-29 18:01:22 -05001285 irq_set_status_flags(irq, IRQ_NOAUTOEN);
Marc Zyngiere91b0362019-07-16 14:41:40 +01001286 break;
1287
1288 case SPI_RANGE:
Marc Zyngier211bddd2019-07-16 15:17:31 +01001289 case ESPI_RANGE:
Marc Zyngier0b6a3da2015-08-26 17:00:42 +01001290 irq_domain_set_info(d, irq, hw, chip, d->host_data,
Marc Zyngier443acc42014-11-24 14:35:09 +00001291 handle_fasteoi_irq, NULL, NULL);
Rob Herringd17cab42015-08-29 18:01:22 -05001292 irq_set_probe(irq);
Marc Zyngier956ae912017-08-18 09:39:17 +01001293 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
Marc Zyngiere91b0362019-07-16 14:41:40 +01001294 break;
1295
1296 case LPI_RANGE:
Marc Zyngierda33f312014-11-24 14:35:18 +00001297 if (!gic_dist_supports_lpis())
1298 return -EPERM;
Marc Zyngier0b6a3da2015-08-26 17:00:42 +01001299 irq_domain_set_info(d, irq, hw, chip, d->host_data,
Marc Zyngierda33f312014-11-24 14:35:18 +00001300 handle_fasteoi_irq, NULL, NULL);
Marc Zyngiere91b0362019-07-16 14:41:40 +01001301 break;
1302
1303 default:
1304 return -EPERM;
Marc Zyngierda33f312014-11-24 14:35:18 +00001305 }
1306
Marc Zyngier021f6532014-06-30 16:01:31 +01001307 return 0;
1308}
1309
Marc Zyngier65da7d12018-03-20 13:44:09 +00001310#define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
1311
Marc Zyngierf833f572015-10-13 12:51:33 +01001312static int gic_irq_domain_translate(struct irq_domain *d,
1313 struct irq_fwspec *fwspec,
1314 unsigned long *hwirq,
1315 unsigned int *type)
Marc Zyngier021f6532014-06-30 16:01:31 +01001316{
Marc Zyngierf833f572015-10-13 12:51:33 +01001317 if (is_of_node(fwspec->fwnode)) {
1318 if (fwspec->param_count < 3)
1319 return -EINVAL;
Marc Zyngier021f6532014-06-30 16:01:31 +01001320
Marc Zyngierdb8c70e2015-10-14 12:27:16 +01001321 switch (fwspec->param[0]) {
1322 case 0: /* SPI */
1323 *hwirq = fwspec->param[1] + 32;
1324 break;
1325 case 1: /* PPI */
1326 *hwirq = fwspec->param[1] + 16;
1327 break;
Marc Zyngier211bddd2019-07-16 15:17:31 +01001328 case 2: /* ESPI */
1329 *hwirq = fwspec->param[1] + ESPI_BASE_INTID;
1330 break;
Marc Zyngier5f51f802019-07-18 13:19:25 +01001331 case 3: /* EPPI */
1332 *hwirq = fwspec->param[1] + EPPI_BASE_INTID;
1333 break;
Marc Zyngierdb8c70e2015-10-14 12:27:16 +01001334 case GIC_IRQ_TYPE_LPI: /* LPI */
1335 *hwirq = fwspec->param[1];
1336 break;
Marc Zyngier5f51f802019-07-18 13:19:25 +01001337 case GIC_IRQ_TYPE_PARTITION:
1338 *hwirq = fwspec->param[1];
1339 if (fwspec->param[1] >= 16)
1340 *hwirq += EPPI_BASE_INTID - 16;
1341 else
1342 *hwirq += 16;
1343 break;
Marc Zyngierdb8c70e2015-10-14 12:27:16 +01001344 default:
1345 return -EINVAL;
1346 }
Marc Zyngierf833f572015-10-13 12:51:33 +01001347
1348 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
Marc Zyngier6ef63862018-03-16 14:35:17 +00001349
Marc Zyngier65da7d12018-03-20 13:44:09 +00001350 /*
1351 * Make it clear that broken DTs are... broken.
1352 * Partitionned PPIs are an unfortunate exception.
1353 */
1354 WARN_ON(*type == IRQ_TYPE_NONE &&
1355 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION);
Marc Zyngierf833f572015-10-13 12:51:33 +01001356 return 0;
Marc Zyngier021f6532014-06-30 16:01:31 +01001357 }
1358
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001359 if (is_fwnode_irqchip(fwspec->fwnode)) {
1360 if(fwspec->param_count != 2)
1361 return -EINVAL;
1362
1363 *hwirq = fwspec->param[0];
1364 *type = fwspec->param[1];
Marc Zyngier6ef63862018-03-16 14:35:17 +00001365
1366 WARN_ON(*type == IRQ_TYPE_NONE);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001367 return 0;
1368 }
1369
Marc Zyngierf833f572015-10-13 12:51:33 +01001370 return -EINVAL;
Marc Zyngier021f6532014-06-30 16:01:31 +01001371}
1372
Marc Zyngier443acc42014-11-24 14:35:09 +00001373static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1374 unsigned int nr_irqs, void *arg)
1375{
1376 int i, ret;
1377 irq_hw_number_t hwirq;
1378 unsigned int type = IRQ_TYPE_NONE;
Marc Zyngierf833f572015-10-13 12:51:33 +01001379 struct irq_fwspec *fwspec = arg;
Marc Zyngier443acc42014-11-24 14:35:09 +00001380
Marc Zyngierf833f572015-10-13 12:51:33 +01001381 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
Marc Zyngier443acc42014-11-24 14:35:09 +00001382 if (ret)
1383 return ret;
1384
Suzuki K Poulose63c16c62017-07-04 10:56:33 +01001385 for (i = 0; i < nr_irqs; i++) {
1386 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1387 if (ret)
1388 return ret;
1389 }
Marc Zyngier443acc42014-11-24 14:35:09 +00001390
1391 return 0;
1392}
1393
1394static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1395 unsigned int nr_irqs)
1396{
1397 int i;
1398
1399 for (i = 0; i < nr_irqs; i++) {
1400 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
1401 irq_set_handler(virq + i, NULL);
1402 irq_domain_reset_irq_data(d);
1403 }
1404}
1405
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001406static int gic_irq_domain_select(struct irq_domain *d,
1407 struct irq_fwspec *fwspec,
1408 enum irq_domain_bus_token bus_token)
1409{
1410 /* Not for us */
1411 if (fwspec->fwnode != d->fwnode)
1412 return 0;
1413
1414 /* If this is not DT, then we have a single domain */
1415 if (!is_of_node(fwspec->fwnode))
1416 return 1;
1417
1418 /*
1419 * If this is a PPI and we have a 4th (non-null) parameter,
1420 * then we need to match the partition domain.
1421 */
1422 if (fwspec->param_count >= 4 &&
Marc Zyngier52085d32019-07-18 13:05:17 +01001423 fwspec->param[0] == 1 && fwspec->param[3] != 0 &&
1424 gic_data.ppi_descs)
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001425 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]);
1426
1427 return d == gic_data.domain;
1428}
1429
Marc Zyngier021f6532014-06-30 16:01:31 +01001430static const struct irq_domain_ops gic_irq_domain_ops = {
Marc Zyngierf833f572015-10-13 12:51:33 +01001431 .translate = gic_irq_domain_translate,
Marc Zyngier443acc42014-11-24 14:35:09 +00001432 .alloc = gic_irq_domain_alloc,
1433 .free = gic_irq_domain_free,
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001434 .select = gic_irq_domain_select,
1435};
1436
1437static int partition_domain_translate(struct irq_domain *d,
1438 struct irq_fwspec *fwspec,
1439 unsigned long *hwirq,
1440 unsigned int *type)
1441{
1442 struct device_node *np;
1443 int ret;
1444
Marc Zyngier52085d32019-07-18 13:05:17 +01001445 if (!gic_data.ppi_descs)
1446 return -ENOMEM;
1447
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001448 np = of_find_node_by_phandle(fwspec->param[3]);
1449 if (WARN_ON(!np))
1450 return -EINVAL;
1451
1452 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]],
1453 of_node_to_fwnode(np));
1454 if (ret < 0)
1455 return ret;
1456
1457 *hwirq = ret;
1458 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1459
1460 return 0;
1461}
1462
1463static const struct irq_domain_ops partition_domain_ops = {
1464 .translate = partition_domain_translate,
1465 .select = gic_irq_domain_select,
Marc Zyngier021f6532014-06-30 16:01:31 +01001466};
1467
Srinivas Kandagatla9c8114c2018-12-10 13:56:32 +00001468static bool gic_enable_quirk_msm8996(void *data)
1469{
1470 struct gic_chip_data *d = data;
1471
1472 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996;
1473
1474 return true;
1475}
1476
Marc Zyngierd01fd162020-03-11 11:56:49 +00001477static bool gic_enable_quirk_cavium_38539(void *data)
1478{
1479 struct gic_chip_data *d = data;
1480
1481 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
1482
1483 return true;
1484}
1485
Marc Zyngier7f2481b2019-07-31 17:29:33 +01001486static bool gic_enable_quirk_hip06_07(void *data)
1487{
1488 struct gic_chip_data *d = data;
1489
1490 /*
1491 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite
1492 * not being an actual ARM implementation). The saving grace is
1493 * that GIC-600 doesn't have ESPI, so nothing to do in that case.
1494 * HIP07 doesn't even have a proper IIDR, and still pretends to
1495 * have ESPI. In both cases, put them right.
1496 */
1497 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) {
1498 /* Zero both ESPI and the RES0 field next to it... */
1499 d->rdists.gicd_typer &= ~GENMASK(9, 8);
1500 return true;
1501 }
1502
1503 return false;
1504}
1505
1506static const struct gic_quirk gic_quirks[] = {
1507 {
1508 .desc = "GICv3: Qualcomm MSM8996 broken firmware",
1509 .compatible = "qcom,msm8996-gic-v3",
1510 .init = gic_enable_quirk_msm8996,
1511 },
1512 {
1513 .desc = "GICv3: HIP06 erratum 161010803",
1514 .iidr = 0x0204043b,
1515 .mask = 0xffffffff,
1516 .init = gic_enable_quirk_hip06_07,
1517 },
1518 {
1519 .desc = "GICv3: HIP07 erratum 161010803",
1520 .iidr = 0x00000000,
1521 .mask = 0xffffffff,
1522 .init = gic_enable_quirk_hip06_07,
1523 },
1524 {
Marc Zyngierd01fd162020-03-11 11:56:49 +00001525 /*
1526 * Reserved register accesses generate a Synchronous
1527 * External Abort. This erratum applies to:
1528 * - ThunderX: CN88xx
1529 * - OCTEON TX: CN83xx, CN81xx
1530 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1531 */
1532 .desc = "GICv3: Cavium erratum 38539",
1533 .iidr = 0xa000034c,
1534 .mask = 0xe8f00fff,
1535 .init = gic_enable_quirk_cavium_38539,
1536 },
1537 {
Marc Zyngier7f2481b2019-07-31 17:29:33 +01001538 }
1539};
1540
Julien Thierryd98d0a92019-01-31 14:58:57 +00001541static void gic_enable_nmi_support(void)
1542{
Julien Thierry101b35f2019-01-31 14:58:59 +00001543 int i;
1544
Marc Zyngier81a43272019-07-18 12:53:05 +01001545 if (!gic_prio_masking_enabled())
1546 return;
1547
1548 if (gic_has_group0() && !gic_dist_security_disabled()) {
1549 pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n");
1550 return;
1551 }
1552
1553 ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
1554 if (!ppi_nmi_refs)
1555 return;
1556
1557 for (i = 0; i < gic_data.ppi_nr; i++)
Julien Thierry101b35f2019-01-31 14:58:59 +00001558 refcount_set(&ppi_nmi_refs[i], 0);
1559
Marc Zyngierf2266502019-10-02 10:06:12 +01001560 /*
1561 * Linux itself doesn't use 1:N distribution, so has no need to
1562 * set PMHE. The only reason to have it set is if EL3 requires it
1563 * (and we can't change it).
1564 */
1565 if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK)
1566 static_branch_enable(&gic_pmr_sync);
1567
1568 pr_info("%s ICC_PMR_EL1 synchronisation\n",
1569 static_branch_unlikely(&gic_pmr_sync) ? "Forcing" : "Relaxing");
1570
Julien Thierryd98d0a92019-01-31 14:58:57 +00001571 static_branch_enable(&supports_pseudo_nmis);
Julien Thierry101b35f2019-01-31 14:58:59 +00001572
1573 if (static_branch_likely(&supports_deactivate_key))
1574 gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI;
1575 else
1576 gic_chip.flags |= IRQCHIP_SUPPORTS_NMI;
Julien Thierryd98d0a92019-01-31 14:58:57 +00001577}
1578
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001579static int __init gic_init_bases(void __iomem *dist_base,
1580 struct redist_region *rdist_regs,
1581 u32 nr_redist_regions,
1582 u64 redist_stride,
1583 struct fwnode_handle *handle)
1584{
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001585 u32 typer;
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001586 int err;
1587
1588 if (!is_hyp_mode_available())
Davidlohr Buesod01d3272018-03-26 14:09:25 -07001589 static_branch_disable(&supports_deactivate_key);
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001590
Davidlohr Buesod01d3272018-03-26 14:09:25 -07001591 if (static_branch_likely(&supports_deactivate_key))
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001592 pr_info("GIC: Using split EOI/Deactivate mode\n");
1593
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001594 gic_data.fwnode = handle;
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001595 gic_data.dist_base = dist_base;
1596 gic_data.redist_regions = rdist_regs;
1597 gic_data.nr_redist_regions = nr_redist_regions;
1598 gic_data.redist_stride = redist_stride;
1599
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001600 /*
1601 * Find out how many interrupts are supported.
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001602 */
1603 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER);
Marc Zyngiera4f9edb2018-05-30 17:29:52 +01001604 gic_data.rdists.gicd_typer = typer;
Marc Zyngier7f2481b2019-07-31 17:29:33 +01001605
1606 gic_enable_quirks(readl_relaxed(gic_data.dist_base + GICD_IIDR),
1607 gic_quirks, &gic_data);
1608
Marc Zyngier211bddd2019-07-16 15:17:31 +01001609 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
1610 pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
Marc Zyngierf2d83402019-12-24 11:10:25 +00001611
Marc Zyngierd01fd162020-03-11 11:56:49 +00001612 /*
1613 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
1614 * architecture spec (which says that reserved registers are RES0).
1615 */
1616 if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
1617 gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
Marc Zyngierf2d83402019-12-24 11:10:25 +00001618
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001619 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
1620 &gic_data);
1621 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist));
Marc Zyngierb25319d2019-12-24 11:10:24 +00001622 gic_data.rdists.has_rvpeid = true;
Marc Zyngier0edc23e2016-12-19 17:01:52 +00001623 gic_data.rdists.has_vlpis = true;
1624 gic_data.rdists.has_direct_lpi = true;
Marc Zyngier96806222020-04-10 11:13:26 +01001625 gic_data.rdists.has_vpend_valid_dirty = true;
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001626
1627 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) {
1628 err = -ENOMEM;
1629 goto out_free;
1630 }
1631
luanshieeaa4b22020-03-12 11:20:55 +08001632 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED);
1633
Shanker Donthinenieda0d042017-10-06 10:24:00 -05001634 gic_data.has_rss = !!(typer & GICD_TYPER_RSS);
1635 pr_info("Distributor has %sRange Selector support\n",
1636 gic_data.has_rss ? "" : "no ");
1637
Marc Zyngier50528752018-05-08 13:14:36 +01001638 if (typer & GICD_TYPER_MBIS) {
1639 err = mbi_init(handle, gic_data.domain);
1640 if (err)
1641 pr_err("Failed to initialize MBIs\n");
1642 }
1643
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001644 set_handle_irq(gic_handle_irq);
1645
Marc Zyngier1a60e1e2019-07-18 11:15:14 +01001646 gic_update_rdist_properties();
Marc Zyngier0edc23e2016-12-19 17:01:52 +00001647
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001648 gic_smp_init();
1649 gic_dist_init();
1650 gic_cpu_init();
1651 gic_cpu_pm_init();
1652
Marc Zyngierd38a71c2018-07-27 14:51:04 +01001653 if (gic_dist_supports_lpis()) {
1654 its_init(handle, &gic_data.rdists, gic_data.domain);
1655 its_cpu_init();
Zeev Zilberman90b4c552019-06-10 13:52:01 +03001656 } else {
1657 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1658 gicv2m_init(handle, gic_data.domain);
Marc Zyngierd38a71c2018-07-27 14:51:04 +01001659 }
1660
Marc Zyngier81a43272019-07-18 12:53:05 +01001661 gic_enable_nmi_support();
Julien Thierryd98d0a92019-01-31 14:58:57 +00001662
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001663 return 0;
1664
1665out_free:
1666 if (gic_data.domain)
1667 irq_domain_remove(gic_data.domain);
1668 free_percpu(gic_data.rdists.rdist);
1669 return err;
1670}
1671
1672static int __init gic_validate_dist_version(void __iomem *dist_base)
1673{
1674 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
1675
1676 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
1677 return -ENODEV;
1678
1679 return 0;
1680}
1681
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001682/* Create all possible partitions at boot time */
Linus Torvalds7beaa242016-05-19 11:27:09 -07001683static void __init gic_populate_ppi_partitions(struct device_node *gic_node)
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001684{
1685 struct device_node *parts_node, *child_part;
1686 int part_idx = 0, i;
1687 int nr_parts;
1688 struct partition_affinity *parts;
1689
Johan Hovold00ee9a12017-11-11 17:51:25 +01001690 parts_node = of_get_child_by_name(gic_node, "ppi-partitions");
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001691 if (!parts_node)
1692 return;
1693
Marc Zyngier52085d32019-07-18 13:05:17 +01001694 gic_data.ppi_descs = kcalloc(gic_data.ppi_nr, sizeof(*gic_data.ppi_descs), GFP_KERNEL);
1695 if (!gic_data.ppi_descs)
1696 return;
1697
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001698 nr_parts = of_get_child_count(parts_node);
1699
1700 if (!nr_parts)
Johan Hovold00ee9a12017-11-11 17:51:25 +01001701 goto out_put_node;
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001702
Kees Cook6396bb22018-06-12 14:03:40 -07001703 parts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001704 if (WARN_ON(!parts))
Johan Hovold00ee9a12017-11-11 17:51:25 +01001705 goto out_put_node;
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001706
1707 for_each_child_of_node(parts_node, child_part) {
1708 struct partition_affinity *part;
1709 int n;
1710
1711 part = &parts[part_idx];
1712
1713 part->partition_id = of_node_to_fwnode(child_part);
1714
Rob Herring2ef790dc2018-08-27 19:56:15 -05001715 pr_info("GIC: PPI partition %pOFn[%d] { ",
1716 child_part, part_idx);
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001717
1718 n = of_property_count_elems_of_size(child_part, "affinity",
1719 sizeof(u32));
1720 WARN_ON(n <= 0);
1721
1722 for (i = 0; i < n; i++) {
1723 int err, cpu;
1724 u32 cpu_phandle;
1725 struct device_node *cpu_node;
1726
1727 err = of_property_read_u32_index(child_part, "affinity",
1728 i, &cpu_phandle);
1729 if (WARN_ON(err))
1730 continue;
1731
1732 cpu_node = of_find_node_by_phandle(cpu_phandle);
1733 if (WARN_ON(!cpu_node))
1734 continue;
1735
Suzuki K Poulosec08ec7d2018-01-02 11:25:29 +00001736 cpu = of_cpu_node_to_id(cpu_node);
1737 if (WARN_ON(cpu < 0))
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001738 continue;
1739
Rob Herringe81f54c2017-07-18 16:43:10 -05001740 pr_cont("%pOF[%d] ", cpu_node, cpu);
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001741
1742 cpumask_set_cpu(cpu, &part->mask);
1743 }
1744
1745 pr_cont("}\n");
1746 part_idx++;
1747 }
1748
Marc Zyngier52085d32019-07-18 13:05:17 +01001749 for (i = 0; i < gic_data.ppi_nr; i++) {
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001750 unsigned int irq;
1751 struct partition_desc *desc;
1752 struct irq_fwspec ppi_fwspec = {
1753 .fwnode = gic_data.fwnode,
1754 .param_count = 3,
1755 .param = {
Marc Zyngier65da7d12018-03-20 13:44:09 +00001756 [0] = GIC_IRQ_TYPE_PARTITION,
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001757 [1] = i,
1758 [2] = IRQ_TYPE_NONE,
1759 },
1760 };
1761
1762 irq = irq_create_fwspec_mapping(&ppi_fwspec);
1763 if (WARN_ON(!irq))
1764 continue;
1765 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts,
1766 irq, &partition_domain_ops);
1767 if (WARN_ON(!desc))
1768 continue;
1769
1770 gic_data.ppi_descs[i] = desc;
1771 }
Johan Hovold00ee9a12017-11-11 17:51:25 +01001772
1773out_put_node:
1774 of_node_put(parts_node);
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001775}
1776
Julien Grall1839e572016-04-11 16:32:57 +01001777static void __init gic_of_setup_kvm_info(struct device_node *node)
1778{
1779 int ret;
1780 struct resource r;
1781 u32 gicv_idx;
1782
1783 gic_v3_kvm_info.type = GIC_V3;
1784
1785 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1786 if (!gic_v3_kvm_info.maint_irq)
1787 return;
1788
1789 if (of_property_read_u32(node, "#redistributor-regions",
1790 &gicv_idx))
1791 gicv_idx = 1;
1792
1793 gicv_idx += 3; /* Also skip GICD, GICC, GICH */
1794 ret = of_address_to_resource(node, gicv_idx, &r);
1795 if (!ret)
1796 gic_v3_kvm_info.vcpu = r;
1797
Marc Zyngier4bdf5022017-06-25 14:10:46 +01001798 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
Marc Zyngier3c407062020-03-04 20:33:13 +00001799 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
Julien Grall1839e572016-04-11 16:32:57 +01001800 gic_set_kvm_info(&gic_v3_kvm_info);
1801}
1802
Marc Zyngier021f6532014-06-30 16:01:31 +01001803static int __init gic_of_init(struct device_node *node, struct device_node *parent)
1804{
1805 void __iomem *dist_base;
Marc Zyngierf5c14342014-11-24 14:35:10 +00001806 struct redist_region *rdist_regs;
Marc Zyngier021f6532014-06-30 16:01:31 +01001807 u64 redist_stride;
Marc Zyngierf5c14342014-11-24 14:35:10 +00001808 u32 nr_redist_regions;
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001809 int err, i;
Marc Zyngier021f6532014-06-30 16:01:31 +01001810
1811 dist_base = of_iomap(node, 0);
1812 if (!dist_base) {
Rob Herringe81f54c2017-07-18 16:43:10 -05001813 pr_err("%pOF: unable to map gic dist registers\n", node);
Marc Zyngier021f6532014-06-30 16:01:31 +01001814 return -ENXIO;
1815 }
1816
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001817 err = gic_validate_dist_version(dist_base);
1818 if (err) {
Rob Herringe81f54c2017-07-18 16:43:10 -05001819 pr_err("%pOF: no distributor detected, giving up\n", node);
Marc Zyngier021f6532014-06-30 16:01:31 +01001820 goto out_unmap_dist;
1821 }
1822
Marc Zyngierf5c14342014-11-24 14:35:10 +00001823 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions))
1824 nr_redist_regions = 1;
Marc Zyngier021f6532014-06-30 16:01:31 +01001825
Kees Cook6396bb22018-06-12 14:03:40 -07001826 rdist_regs = kcalloc(nr_redist_regions, sizeof(*rdist_regs),
1827 GFP_KERNEL);
Marc Zyngierf5c14342014-11-24 14:35:10 +00001828 if (!rdist_regs) {
Marc Zyngier021f6532014-06-30 16:01:31 +01001829 err = -ENOMEM;
1830 goto out_unmap_dist;
1831 }
1832
Marc Zyngierf5c14342014-11-24 14:35:10 +00001833 for (i = 0; i < nr_redist_regions; i++) {
1834 struct resource res;
1835 int ret;
1836
1837 ret = of_address_to_resource(node, 1 + i, &res);
1838 rdist_regs[i].redist_base = of_iomap(node, 1 + i);
1839 if (ret || !rdist_regs[i].redist_base) {
Rob Herringe81f54c2017-07-18 16:43:10 -05001840 pr_err("%pOF: couldn't map region %d\n", node, i);
Marc Zyngier021f6532014-06-30 16:01:31 +01001841 err = -ENODEV;
1842 goto out_unmap_rdist;
1843 }
Marc Zyngierf5c14342014-11-24 14:35:10 +00001844 rdist_regs[i].phys_base = res.start;
Marc Zyngier021f6532014-06-30 16:01:31 +01001845 }
1846
1847 if (of_property_read_u64(node, "redistributor-stride", &redist_stride))
1848 redist_stride = 0;
1849
Srinivas Kandagatlaf70fdb42018-12-10 13:56:31 +00001850 gic_enable_of_quirks(node, gic_quirks, &gic_data);
1851
Tomasz Nowickidb57d742016-01-19 14:11:14 +01001852 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions,
1853 redist_stride, &node->fwnode);
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001854 if (err)
1855 goto out_unmap_rdist;
1856
1857 gic_populate_ppi_partitions(node);
Christoffer Dalld33a3c82016-12-06 22:00:52 +01001858
Davidlohr Buesod01d3272018-03-26 14:09:25 -07001859 if (static_branch_likely(&supports_deactivate_key))
Christoffer Dalld33a3c82016-12-06 22:00:52 +01001860 gic_of_setup_kvm_info(node);
Marc Zyngiere3825ba2016-04-11 09:57:54 +01001861 return 0;
Marc Zyngier0b6a3da2015-08-26 17:00:42 +01001862
Marc Zyngier021f6532014-06-30 16:01:31 +01001863out_unmap_rdist:
Marc Zyngierf5c14342014-11-24 14:35:10 +00001864 for (i = 0; i < nr_redist_regions; i++)
1865 if (rdist_regs[i].redist_base)
1866 iounmap(rdist_regs[i].redist_base);
1867 kfree(rdist_regs);
Marc Zyngier021f6532014-06-30 16:01:31 +01001868out_unmap_dist:
1869 iounmap(dist_base);
1870 return err;
1871}
1872
1873IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001874
1875#ifdef CONFIG_ACPI
Julien Grall611f0392016-04-11 16:32:56 +01001876static struct
1877{
1878 void __iomem *dist_base;
1879 struct redist_region *redist_regs;
1880 u32 nr_redist_regions;
1881 bool single_redist;
Marc Zyngier926b5df2019-12-16 11:24:57 +00001882 int enabled_rdists;
Julien Grall1839e572016-04-11 16:32:57 +01001883 u32 maint_irq;
1884 int maint_irq_mode;
1885 phys_addr_t vcpu_base;
Julien Grall611f0392016-04-11 16:32:56 +01001886} acpi_data __initdata;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001887
1888static void __init
1889gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base)
1890{
1891 static int count = 0;
1892
Julien Grall611f0392016-04-11 16:32:56 +01001893 acpi_data.redist_regs[count].phys_base = phys_base;
1894 acpi_data.redist_regs[count].redist_base = redist_base;
1895 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001896 count++;
1897}
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001898
1899static int __init
Keith Busch60574d12019-03-11 14:55:57 -06001900gic_acpi_parse_madt_redist(union acpi_subtable_headers *header,
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001901 const unsigned long end)
1902{
1903 struct acpi_madt_generic_redistributor *redist =
1904 (struct acpi_madt_generic_redistributor *)header;
1905 void __iomem *redist_base;
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001906
1907 redist_base = ioremap(redist->base_address, redist->length);
1908 if (!redist_base) {
1909 pr_err("Couldn't map GICR region @%llx\n", redist->base_address);
1910 return -ENOMEM;
1911 }
1912
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001913 gic_acpi_register_redist(redist->base_address, redist_base);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001914 return 0;
1915}
1916
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001917static int __init
Keith Busch60574d12019-03-11 14:55:57 -06001918gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001919 const unsigned long end)
1920{
1921 struct acpi_madt_generic_interrupt *gicc =
1922 (struct acpi_madt_generic_interrupt *)header;
Julien Grall611f0392016-04-11 16:32:56 +01001923 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001924 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
1925 void __iomem *redist_base;
1926
Shanker Donthineniebe2f872017-12-05 13:16:21 -06001927 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
1928 if (!(gicc->flags & ACPI_MADT_ENABLED))
1929 return 0;
1930
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001931 redist_base = ioremap(gicc->gicr_base_address, size);
1932 if (!redist_base)
1933 return -ENOMEM;
1934
1935 gic_acpi_register_redist(gicc->gicr_base_address, redist_base);
1936 return 0;
1937}
1938
1939static int __init gic_acpi_collect_gicr_base(void)
1940{
1941 acpi_tbl_entry_handler redist_parser;
1942 enum acpi_madt_type type;
1943
Julien Grall611f0392016-04-11 16:32:56 +01001944 if (acpi_data.single_redist) {
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001945 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT;
1946 redist_parser = gic_acpi_parse_madt_gicc;
1947 } else {
1948 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR;
1949 redist_parser = gic_acpi_parse_madt_redist;
1950 }
1951
1952 /* Collect redistributor base addresses in GICR entries */
1953 if (acpi_table_parse_madt(type, redist_parser, 0) > 0)
1954 return 0;
1955
1956 pr_info("No valid GICR entries exist\n");
1957 return -ENODEV;
1958}
1959
Keith Busch60574d12019-03-11 14:55:57 -06001960static int __init gic_acpi_match_gicr(union acpi_subtable_headers *header,
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01001961 const unsigned long end)
1962{
1963 /* Subtable presence means that redist exists, that's it */
1964 return 0;
1965}
1966
Keith Busch60574d12019-03-11 14:55:57 -06001967static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001968 const unsigned long end)
1969{
1970 struct acpi_madt_generic_interrupt *gicc =
1971 (struct acpi_madt_generic_interrupt *)header;
1972
1973 /*
1974 * If GICC is enabled and has valid gicr base address, then it means
1975 * GICR base is presented via GICC
1976 */
Marc Zyngier926b5df2019-12-16 11:24:57 +00001977 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) {
1978 acpi_data.enabled_rdists++;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001979 return 0;
Marc Zyngier926b5df2019-12-16 11:24:57 +00001980 }
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001981
Shanker Donthineniebe2f872017-12-05 13:16:21 -06001982 /*
1983 * It's perfectly valid firmware can pass disabled GICC entry, driver
1984 * should not treat as errors, skip the entry instead of probe fail.
1985 */
1986 if (!(gicc->flags & ACPI_MADT_ENABLED))
1987 return 0;
1988
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01001989 return -ENODEV;
1990}
1991
1992static int __init gic_acpi_count_gicr_regions(void)
1993{
1994 int count;
1995
1996 /*
1997 * Count how many redistributor regions we have. It is not allowed
1998 * to mix redistributor description, GICR and GICC subtables have to be
1999 * mutually exclusive.
2000 */
2001 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
2002 gic_acpi_match_gicr, 0);
2003 if (count > 0) {
Julien Grall611f0392016-04-11 16:32:56 +01002004 acpi_data.single_redist = false;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01002005 return count;
2006 }
2007
2008 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2009 gic_acpi_match_gicc, 0);
Marc Zyngier926b5df2019-12-16 11:24:57 +00002010 if (count > 0) {
Julien Grall611f0392016-04-11 16:32:56 +01002011 acpi_data.single_redist = true;
Marc Zyngier926b5df2019-12-16 11:24:57 +00002012 count = acpi_data.enabled_rdists;
2013 }
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01002014
2015 return count;
2016}
2017
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002018static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,
2019 struct acpi_probe_entry *ape)
2020{
2021 struct acpi_madt_generic_distributor *dist;
2022 int count;
2023
2024 dist = (struct acpi_madt_generic_distributor *)header;
2025 if (dist->version != ape->driver_data)
2026 return false;
2027
2028 /* We need to do that exercise anyway, the sooner the better */
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01002029 count = gic_acpi_count_gicr_regions();
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002030 if (count <= 0)
2031 return false;
2032
Julien Grall611f0392016-04-11 16:32:56 +01002033 acpi_data.nr_redist_regions = count;
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002034 return true;
2035}
2036
Keith Busch60574d12019-03-11 14:55:57 -06002037static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *header,
Julien Grall1839e572016-04-11 16:32:57 +01002038 const unsigned long end)
2039{
2040 struct acpi_madt_generic_interrupt *gicc =
2041 (struct acpi_madt_generic_interrupt *)header;
2042 int maint_irq_mode;
2043 static int first_madt = true;
2044
2045 /* Skip unusable CPUs */
2046 if (!(gicc->flags & ACPI_MADT_ENABLED))
2047 return 0;
2048
2049 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
2050 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
2051
2052 if (first_madt) {
2053 first_madt = false;
2054
2055 acpi_data.maint_irq = gicc->vgic_interrupt;
2056 acpi_data.maint_irq_mode = maint_irq_mode;
2057 acpi_data.vcpu_base = gicc->gicv_base_address;
2058
2059 return 0;
2060 }
2061
2062 /*
2063 * The maintenance interrupt and GICV should be the same for every CPU
2064 */
2065 if ((acpi_data.maint_irq != gicc->vgic_interrupt) ||
2066 (acpi_data.maint_irq_mode != maint_irq_mode) ||
2067 (acpi_data.vcpu_base != gicc->gicv_base_address))
2068 return -EINVAL;
2069
2070 return 0;
2071}
2072
2073static bool __init gic_acpi_collect_virt_info(void)
2074{
2075 int count;
2076
2077 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
2078 gic_acpi_parse_virt_madt_gicc, 0);
2079
2080 return (count > 0);
2081}
2082
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002083#define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
Julien Grall1839e572016-04-11 16:32:57 +01002084#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
2085#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
2086
2087static void __init gic_acpi_setup_kvm_info(void)
2088{
2089 int irq;
2090
2091 if (!gic_acpi_collect_virt_info()) {
2092 pr_warn("Unable to get hardware information used for virtualization\n");
2093 return;
2094 }
2095
2096 gic_v3_kvm_info.type = GIC_V3;
2097
2098 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
2099 acpi_data.maint_irq_mode,
2100 ACPI_ACTIVE_HIGH);
2101 if (irq <= 0)
2102 return;
2103
2104 gic_v3_kvm_info.maint_irq = irq;
2105
2106 if (acpi_data.vcpu_base) {
2107 struct resource *vcpu = &gic_v3_kvm_info.vcpu;
2108
2109 vcpu->flags = IORESOURCE_MEM;
2110 vcpu->start = acpi_data.vcpu_base;
2111 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
2112 }
2113
Marc Zyngier4bdf5022017-06-25 14:10:46 +01002114 gic_v3_kvm_info.has_v4 = gic_data.rdists.has_vlpis;
Marc Zyngier3c407062020-03-04 20:33:13 +00002115 gic_v3_kvm_info.has_v4_1 = gic_data.rdists.has_rvpeid;
Julien Grall1839e572016-04-11 16:32:57 +01002116 gic_set_kvm_info(&gic_v3_kvm_info);
2117}
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002118
2119static int __init
2120gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end)
2121{
2122 struct acpi_madt_generic_distributor *dist;
2123 struct fwnode_handle *domain_handle;
Julien Grall611f0392016-04-11 16:32:56 +01002124 size_t size;
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01002125 int i, err;
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002126
2127 /* Get distributor base address */
2128 dist = (struct acpi_madt_generic_distributor *)header;
Julien Grall611f0392016-04-11 16:32:56 +01002129 acpi_data.dist_base = ioremap(dist->base_address,
2130 ACPI_GICV3_DIST_MEM_SIZE);
2131 if (!acpi_data.dist_base) {
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002132 pr_err("Unable to map GICD registers\n");
2133 return -ENOMEM;
2134 }
2135
Julien Grall611f0392016-04-11 16:32:56 +01002136 err = gic_validate_dist_version(acpi_data.dist_base);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002137 if (err) {
Arvind Yadav71192a682017-11-13 19:23:49 +05302138 pr_err("No distributor detected at @%p, giving up\n",
Julien Grall611f0392016-04-11 16:32:56 +01002139 acpi_data.dist_base);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002140 goto out_dist_unmap;
2141 }
2142
Julien Grall611f0392016-04-11 16:32:56 +01002143 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions;
2144 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL);
2145 if (!acpi_data.redist_regs) {
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002146 err = -ENOMEM;
2147 goto out_dist_unmap;
2148 }
2149
Tomasz Nowickib70fb7a2016-01-19 14:11:16 +01002150 err = gic_acpi_collect_gicr_base();
2151 if (err)
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002152 goto out_redist_unmap;
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002153
Marc Zyngiereeee0d02019-07-31 16:13:42 +01002154 domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002155 if (!domain_handle) {
2156 err = -ENOMEM;
2157 goto out_redist_unmap;
2158 }
2159
Julien Grall611f0392016-04-11 16:32:56 +01002160 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs,
2161 acpi_data.nr_redist_regions, 0, domain_handle);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002162 if (err)
2163 goto out_fwhandle_free;
2164
2165 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
Christoffer Dalld33a3c82016-12-06 22:00:52 +01002166
Davidlohr Buesod01d3272018-03-26 14:09:25 -07002167 if (static_branch_likely(&supports_deactivate_key))
Christoffer Dalld33a3c82016-12-06 22:00:52 +01002168 gic_acpi_setup_kvm_info();
Julien Grall1839e572016-04-11 16:32:57 +01002169
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002170 return 0;
2171
2172out_fwhandle_free:
2173 irq_domain_free_fwnode(domain_handle);
2174out_redist_unmap:
Julien Grall611f0392016-04-11 16:32:56 +01002175 for (i = 0; i < acpi_data.nr_redist_regions; i++)
2176 if (acpi_data.redist_regs[i].redist_base)
2177 iounmap(acpi_data.redist_regs[i].redist_base);
2178 kfree(acpi_data.redist_regs);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002179out_dist_unmap:
Julien Grall611f0392016-04-11 16:32:56 +01002180 iounmap(acpi_data.dist_base);
Tomasz Nowickiffa7d612016-01-19 14:11:15 +01002181 return err;
2182}
2183IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2184 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3,
2185 gic_acpi_init);
2186IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2187 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4,
2188 gic_acpi_init);
2189IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
2190 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE,
2191 gic_acpi_init);
2192#endif