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Thomas Gleixner386b05e2009-06-06 14:56:33 +02001perf-list(1)
Ingo Molnar6e6b7542008-04-15 22:39:31 +02002============
Thomas Gleixner386b05e2009-06-06 14:56:33 +02003
4NAME
5----
6perf-list - List all symbolic event types
7
8SYNOPSIS
9--------
10[verse]
Andi Kleen71b0acc2017-08-31 12:40:32 -070011'perf list' [--no-desc] [--long-desc]
12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob]
Thomas Gleixner386b05e2009-06-06 14:56:33 +020013
14DESCRIPTION
15-----------
16This command displays the symbolic event types which can be selected in the
17various perf commands with the -e option.
18
Andi Kleen1c5f01f2016-09-15 15:24:45 -070019OPTIONS
20-------
Sangwon Hong6feb3fe2018-07-17 20:07:38 +090021-d::
22--desc::
23Print extra event descriptions. (default)
24
Andi Kleen1c5f01f2016-09-15 15:24:45 -070025--no-desc::
26Don't print descriptions.
27
Sukadev Bhattiproluc8d68282016-09-15 15:24:48 -070028-v::
29--long-desc::
30Print longer event descriptions.
31
Sangwon Hong6feb3fe2018-07-17 20:07:38 +090032--debug::
33Enable debugging output.
34
Andi Kleenbf874fc2017-03-20 13:17:11 -070035--details::
36Print how named events are resolved internally into perf events, and also
37any extra expressions computed by perf stat.
38
Jin Yaoa7f6c8c2019-10-15 10:53:57 +080039--deprecated::
40Print deprecated events. By default the deprecated events are hidden.
41
Ian Rogersca0fe622022-11-14 13:07:18 -080042--unit::
43Print PMU events and metrics limited to the specific PMU name.
44(e.g. --unit cpu, --unit msr, --unit cpu_core, --unit cpu_atom)
Jin Yao0e0ae872021-09-03 10:52:39 +080045
Ian Rogers6ed24942022-11-17 13:43:37 -030046-j::
47--json::
48Output in JSON format.
49
Robert Richter75bc5ca2012-08-07 19:43:15 +020050[[EVENT_MODIFIERS]]
Sonny Raoffec5162010-10-14 20:51:00 -050051EVENT MODIFIERS
52---------------
53
Masanari Iida96355f22014-09-10 00:18:50 +090054Events can optionally have a modifier by appending a colon and one or
Robert Richter2055fda2012-08-07 19:43:16 +020055more modifiers. Modifiers allow the user to restrict the events to be
56counted. The following modifiers exist:
57
58 u - user-space counting
59 k - kernel counting
60 h - hypervisor counting
Jiri Olsaa1e12da2015-04-07 23:25:14 +020061 I - non idle counting
Robert Richter2055fda2012-08-07 19:43:16 +020062 G - guest counting (in KVM guests)
63 H - host counting (not in KVM guests)
64 p - precise level
Jiri Olsa7f94af72015-10-05 20:06:05 +020065 P - use maximum detected precise level
Jiri Olsa3c176312012-10-10 17:39:03 +020066 S - read sample value (PERF_SAMPLE_READ)
Michael Ellermane9a7c412013-08-06 23:28:05 +100067 D - pin the event to the PMU
Andi Kleen5a5dfe42017-08-31 12:40:26 -070068 W - group is weak and will fallback to non-group if not schedulable,
Andi Kleen0997a262020-10-14 07:42:55 -070069 e - group or event are exclusive and do not share the PMU
Sonny Raoffec5162010-10-14 20:51:00 -050070
71The 'p' modifier can be used for specifying how precise the instruction
Robert Richter2055fda2012-08-07 19:43:16 +020072address should be. The 'p' modifier can be specified multiple times:
Sonny Raoffec5162010-10-14 20:51:00 -050073
Robert Richter2055fda2012-08-07 19:43:16 +020074 0 - SAMPLE_IP can have arbitrary skid
75 1 - SAMPLE_IP must have constant skid
76 2 - SAMPLE_IP requested to have 0 skid
Andi Kleen4ca0d812016-03-21 08:56:33 -070077 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
78 sample shadowing effects.
Robert Richter2055fda2012-08-07 19:43:16 +020079
80For Intel systems precise event sampling is implemented with PEBS
Andi Kleen4ca0d812016-03-21 08:56:33 -070081which supports up to precise-level 2, and precise level 3 for
82some special cases
Robert Richter2055fda2012-08-07 19:43:16 +020083
84On AMD systems it is implemented using IBS (up to precise-level 2).
85The precise modifier works with event types 0x76 (cpu-cycles, CPU
86clocks not halted) and 0xC1 (micro-ops retired). Both events map to
87IBS execution sampling (IBS op) with the IBS Op Counter Control bit
Sandipan Das7a2e1492021-11-23 14:16:13 +053088(IbsOpCntCtl) set respectively (see the
89Core Complex (CCX) -> Processor x86 Core -> Instruction Based Sampling (IBS)
90section of the [AMD Processor Programming Reference (PPR)] relevant to the
91family, model and stepping of the processor being used).
92
Robert Richter2055fda2012-08-07 19:43:16 +020093Manual Volume 2: System Programming, 13.3 Instruction-Based
94Sampling). Examples to use IBS:
95
96 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
97 perf record -a -e r076:p ... # same as -e cpu-cycles:p
98 perf record -a -e r0C1:p ... # use ibs op counting micro-ops
Sonny Raoffec5162010-10-14 20:51:00 -050099
Arnaldo Carvalho de Melo9e32a3c2010-05-05 11:20:05 -0300100RAW HARDWARE EVENT DESCRIPTOR
101-----------------------------
102Even when an event is not available in a symbolic form within perf right now,
Arnaldo Carvalho de Melo1cf4a062010-05-07 14:07:05 -0300103it can be encoded in a per processor specific way.
104
Sandipan Das4edb1172021-11-23 14:16:12 +0530105For instance on x86 CPUs, N is a hexadecimal value that represents the raw register encoding with the
Arnaldo Carvalho de Melo1cf4a062010-05-07 14:07:05 -0300106layout of IA32_PERFEVTSELx MSRs (see [IntelĀ® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
Sandipan Das7a2e1492021-11-23 14:16:13 +0530107of IA32_PERFEVTSELx MSRs) or AMD's PERF_CTL MSRs (see the
108Core Complex (CCX) -> Processor x86 Core -> MSR Registers section of the
109[AMD Processor Programming Reference (PPR)] relevant to the family, model
110and stepping of the processor being used).
Arnaldo Carvalho de Melo1cf4a062010-05-07 14:07:05 -0300111
Robert Richter75bc5ca2012-08-07 19:43:15 +0200112Note: Only the following bit fields can be set in x86 counter
113registers: event, umask, edge, inv, cmask. Esp. guest/host only and
114OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
115MODIFIERS>>.
116
Arnaldo Carvalho de Melo1cf4a062010-05-07 14:07:05 -0300117Example:
118
119If the Intel docs for a QM720 Core i7 describe an event as:
Arnaldo Carvalho de Melo9e32a3c2010-05-05 11:20:05 -0300120
121 Event Umask Event Mask
122 Num. Value Mnemonic Description Comment
123
124 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
125 delivered by loop stream detector invert to count
126 cycles
127
128raw encoding of 0x1A8 can be used:
129
130 perf stat -e r1a8 -a sleep 1
131 perf record -e r1a8 ...
132
Jiri Olsa3a6c51e2020-04-17 00:14:05 +0200133It's also possible to use pmu syntax:
134
135 perf record -e r1a8 -a sleep 1
136 perf record -e cpu/r1a8/ ...
Jiri Olsac33cdf52020-07-25 14:19:58 +0200137 perf record -e cpu/r0x1a8/ ...
Jiri Olsa3a6c51e2020-04-17 00:14:05 +0200138
Sandipan Das4edb1172021-11-23 14:16:12 +0530139Some processors, like those from AMD, support event codes and unit masks
140larger than a byte. In such cases, the bits corresponding to the event
141configuration parameters can be seen with:
142
143 cat /sys/bus/event_source/devices/<pmu>/format/<config>
144
145Example:
146
147If the AMD docs for an EPYC 7713 processor describe an event as:
148
149 Event Umask Event Mask
150 Num. Value Mnemonic Description
151
152 28FH 03H op_cache_hit_miss.op_cache_hit Counts Op Cache micro-tag
153 hit events.
154
155raw encoding of 0x0328F cannot be used since the upper nibble of the
156EventSelect bits have to be specified via bits 32-35 as can be seen with:
157
158 cat /sys/bus/event_source/devices/cpu/format/event
159
160raw encoding of 0x20000038F should be used instead:
161
162 perf stat -e r20000038f -a sleep 1
163 perf record -e r20000038f ...
164
165It's also possible to use pmu syntax:
166
167 perf record -e r20000038f -a sleep 1
168 perf record -e cpu/r20000038f/ ...
169 perf record -e cpu/r0x20000038f/ ...
170
Arnaldo Carvalho de Melo1cf4a062010-05-07 14:07:05 -0300171You should refer to the processor specific documentation for getting these
172details. Some of them are referenced in the SEE ALSO section below.
173
Andi Kleen85f8f962016-04-04 15:58:06 -0700174ARBITRARY PMUS
175--------------
176
177perf also supports an extended syntax for specifying raw parameters
178to PMUs. Using this typically requires looking up the specific event
179in the CPU vendor specific documentation.
180
181The available PMUs and their raw parameters can be listed with
182
183 ls /sys/devices/*/format
184
185For example the raw event "LSD.UOPS" core pmu event above could
186be specified as
187
Alexey Budankovf92da712018-06-04 09:50:56 +0300188 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ...
189
190 or using extended name syntax
191
192 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ...
Andi Kleen85f8f962016-04-04 15:58:06 -0700193
194PER SOCKET PMUS
195---------------
196
197Some PMUs are not associated with a core, but with a whole CPU socket.
198Events on these PMUs generally cannot be sampled, but only counted globally
199with perf stat -a. They can be bound to one logical CPU, but will measure
200all the CPUs in the same socket.
201
202This example measures memory bandwidth every second
203on the first memory controller on socket 0 of a Intel Xeon system
204
205 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
206
207Each memory controller has its own PMU. Measuring the complete system
208bandwidth would require specifying all imc PMUs (see perf list output),
Agustin Vega-Friasb2b9d3a2018-03-06 09:04:42 -0500209and adding the values together. To simplify creation of multiple events,
210prefix and glob matching is supported in the PMU name, and the prefix
211'uncore_' is also ignored when performing the match. So the command above
212can be expanded to all memory controllers by using the syntaxes:
213
214 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
215 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
Andi Kleen85f8f962016-04-04 15:58:06 -0700216
217This example measures the combined core power every second
218
219 perf stat -I 1000 -e power/energy-cores/ -a
220
221ACCESS RESTRICTIONS
222-------------------
223
224For non root users generally only context switched PMU events are available.
225This is normally only the events in the cpu PMU, the predefined events
226like cycles and instructions and some software events.
227
228Other PMUs and global measurements are normally root only.
229Some event qualifiers, such as "any", are also root only.
230
Ingo Molnar1a7ea322018-12-03 11:22:00 +0100231This can be overridden by setting the kernel.perf_event_paranoid
Andi Kleen85f8f962016-04-04 15:58:06 -0700232sysctl to -1, which allows non root to use these events.
233
234For accessing trace point events perf needs to have read access to
235/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed
236setting.
237
238TRACING
239-------
240
241Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
242that allows low overhead execution tracing. These are described in a separate
243intel-pt.txt document.
244
Cody P Schaferf9ab9c12015-01-07 17:13:53 -0800245PARAMETERIZED EVENTS
246--------------------
247
248Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
249example:
250
251 hv_gpci/dtbp_ptitc,phys_processor_idx=?/
252
253This means that when provided as an event, a value for '?' must
254also be supplied. For example:
255
256 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
257
Jin Yao064b4e82019-04-12 21:59:47 +0800258EVENT QUALIFIERS:
259
260It is also possible to add extra qualifiers to an event:
261
262percore:
263
264Sums up the event counts for all hardware threads in a core, e.g.:
265
266
267 perf stat -e cpu/event=0,umask=0x3,percore=1/
268
269
Andi Kleen85f8f962016-04-04 15:58:06 -0700270EVENT GROUPS
271------------
272
273Perf supports time based multiplexing of events, when the number of events
274active exceeds the number of hardware performance counters. Multiplexing
275can cause measurement errors when the workload changes its execution
276profile.
277
278When metrics are computed using formulas from event counts, it is useful to
279ensure some events are always measured together as a group to minimize multiplexing
280errors. Event groups can be specified using { }.
281
282 perf stat -e '{instructions,cycles}' ...
283
284The number of available performance counters depend on the CPU. A group
285cannot contain more events than available counters.
286For example Intel Core CPUs typically have four generic performance counters
287for the core, plus three fixed counters for instructions, cycles and
288ref-cycles. Some special events have restrictions on which counter they
289can schedule, and may not support multiple instances in a single group.
Andi Kleen98ad7612017-10-10 15:43:22 -0700290When too many events are specified in the group some of them will not
Andi Kleen85f8f962016-04-04 15:58:06 -0700291be measured.
292
293Globally pinned events can limit the number of counters available for
294other groups. On x86 systems, the NMI watchdog pins a counter by default.
295The nmi watchdog can be disabled as root with
296
297 echo 0 > /proc/sys/kernel/nmi_watchdog
298
299Events from multiple different PMUs cannot be mixed in a group, with
300some exceptions for software events.
301
302LEADER SAMPLING
303---------------
304
305perf also supports group leader sampling using the :S specifier.
306
307 perf record -e '{cycles,instructions}:S' ...
308 perf report --group
309
Tobias Tefke788faab2018-07-09 12:57:15 +0200310Normally all events in an event group sample, but with :S only
Andi Kleen85f8f962016-04-04 15:58:06 -0700311the first event (the leader) samples, and it only reads the values of the
312other events in the group.
313
Adrian Huntere3459972020-04-01 13:16:13 +0300314However, in the case AUX area events (e.g. Intel PT or CoreSight), the AUX
315area event must be the leader, so then the second event samples, not the first.
316
Thomas Gleixner386b05e2009-06-06 14:56:33 +0200317OPTIONS
318-------
Arnaldo Carvalho de Melo668b8782011-02-17 15:38:58 -0200319
320Without options all known events will be listed.
321
322To limit the list use:
323
324. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
325
326. 'sw' or 'software' to list software events such as context switches, etc.
327
328. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
329
330. 'tracepoint' to list all tracepoint events, alternatively use
331 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
332 block, etc.
333
Andi Kleendc098b32013-04-20 11:02:29 -0700334. 'pmu' to print the kernel supplied PMU events.
335
Ravi Bangoria6963d3c2017-03-27 08:25:38 +0530336. 'sdt' to list all Statically Defined Tracepoint events.
337
Andi Kleen71b0acc2017-08-31 12:40:32 -0700338. 'metric' to list metrics
339
340. 'metricgroup' to list metricgroups with metrics.
341
Arnaldo Carvalho de Melo668b8782011-02-17 15:38:58 -0200342. If none of the above is matched, it will apply the supplied glob to all
343 events, printing the ones that match.
344
Arnaldo Carvalho de Melodbc67402015-10-01 12:12:22 -0300345. As a last resort, it will do a substring search in all event names.
346
Arnaldo Carvalho de Melo668b8782011-02-17 15:38:58 -0200347One or more types can be used at the same time, listing the events for the
348types specified.
Thomas Gleixner386b05e2009-06-06 14:56:33 +0200349
Yunlong Song5ef803e2015-02-27 18:21:28 +0800350Support raw format:
351
352. '--raw-dump', shows the raw-dump of all the events.
353. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
354 a certain kind of events.
355
Thomas Gleixner386b05e2009-06-06 14:56:33 +0200356SEE ALSO
357--------
358linkperf:perf-stat[1], linkperf:perf-top[1],
Arnaldo Carvalho de Melo1cf4a062010-05-07 14:07:05 -0300359linkperf:perf-record[1],
Andi Kleen85f8f962016-04-04 15:58:06 -0700360http://www.intel.com/sdm/[IntelĀ® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
Sandipan Das7a2e1492021-11-23 14:16:13 +0530361https://bugzilla.kernel.org/show_bug.cgi?id=206537[AMD Processor Programming Reference (PPR)]