Kozlov Sergey | dacf9ce | 2015-07-28 11:33:01 -0300 | [diff] [blame] | 1 | /* |
| 2 | * ascot2e.c |
| 3 | * |
| 4 | * Sony Ascot3E DVB-T/T2/C/C2 tuner driver |
| 5 | * |
| 6 | * Copyright 2012 Sony Corporation |
| 7 | * Copyright (C) 2014 NetUP Inc. |
| 8 | * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru> |
| 9 | * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru> |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | */ |
| 21 | |
| 22 | #include <linux/slab.h> |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/dvb/frontend.h> |
| 25 | #include <linux/types.h> |
| 26 | #include "ascot2e.h" |
| 27 | #include "dvb_frontend.h" |
| 28 | |
Mauro Carvalho Chehab | 8853780 | 2015-08-11 15:36:15 -0300 | [diff] [blame] | 29 | #define MAX_WRITE_REGSIZE 10 |
| 30 | |
Kozlov Sergey | dacf9ce | 2015-07-28 11:33:01 -0300 | [diff] [blame] | 31 | enum ascot2e_state { |
| 32 | STATE_UNKNOWN, |
| 33 | STATE_SLEEP, |
| 34 | STATE_ACTIVE |
| 35 | }; |
| 36 | |
| 37 | struct ascot2e_priv { |
| 38 | u32 frequency; |
| 39 | u8 i2c_address; |
| 40 | struct i2c_adapter *i2c; |
| 41 | enum ascot2e_state state; |
| 42 | void *set_tuner_data; |
| 43 | int (*set_tuner)(void *, int); |
| 44 | }; |
| 45 | |
| 46 | enum ascot2e_tv_system_t { |
| 47 | ASCOT2E_DTV_DVBT_5, |
| 48 | ASCOT2E_DTV_DVBT_6, |
| 49 | ASCOT2E_DTV_DVBT_7, |
| 50 | ASCOT2E_DTV_DVBT_8, |
| 51 | ASCOT2E_DTV_DVBT2_1_7, |
| 52 | ASCOT2E_DTV_DVBT2_5, |
| 53 | ASCOT2E_DTV_DVBT2_6, |
| 54 | ASCOT2E_DTV_DVBT2_7, |
| 55 | ASCOT2E_DTV_DVBT2_8, |
| 56 | ASCOT2E_DTV_DVBC_6, |
| 57 | ASCOT2E_DTV_DVBC_8, |
| 58 | ASCOT2E_DTV_DVBC2_6, |
| 59 | ASCOT2E_DTV_DVBC2_8, |
| 60 | ASCOT2E_DTV_UNKNOWN |
| 61 | }; |
| 62 | |
| 63 | struct ascot2e_band_sett { |
| 64 | u8 if_out_sel; |
| 65 | u8 agc_sel; |
| 66 | u8 mix_oll; |
| 67 | u8 rf_gain; |
| 68 | u8 if_bpf_gc; |
| 69 | u8 fif_offset; |
| 70 | u8 bw_offset; |
| 71 | u8 bw; |
| 72 | u8 rf_oldet; |
| 73 | u8 if_bpf_f0; |
| 74 | }; |
| 75 | |
| 76 | #define ASCOT2E_AUTO 0xff |
| 77 | #define ASCOT2E_OFFSET(ofs) ((u8)(ofs) & 0x1F) |
| 78 | #define ASCOT2E_BW_6 0x00 |
| 79 | #define ASCOT2E_BW_7 0x01 |
| 80 | #define ASCOT2E_BW_8 0x02 |
| 81 | #define ASCOT2E_BW_1_7 0x03 |
| 82 | |
| 83 | static struct ascot2e_band_sett ascot2e_sett[] = { |
| 84 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, |
| 85 | ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 }, |
| 86 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, |
| 87 | ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 }, |
| 88 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, |
| 89 | ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_7, 0x0B, 0x00 }, |
| 90 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, |
| 91 | ASCOT2E_OFFSET(-4), ASCOT2E_OFFSET(-2), ASCOT2E_BW_8, 0x0B, 0x00 }, |
| 92 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, |
| 93 | ASCOT2E_OFFSET(-10), ASCOT2E_OFFSET(-16), ASCOT2E_BW_1_7, 0x0B, 0x00 }, |
| 94 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, |
| 95 | ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 }, |
| 96 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, |
| 97 | ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 }, |
| 98 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, |
| 99 | ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_7, 0x0B, 0x00 }, |
| 100 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06, |
| 101 | ASCOT2E_OFFSET(-4), ASCOT2E_OFFSET(-2), ASCOT2E_BW_8, 0x0B, 0x00 }, |
| 102 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x02, ASCOT2E_AUTO, 0x03, |
| 103 | ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-8), ASCOT2E_BW_6, 0x09, 0x00 }, |
| 104 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x02, ASCOT2E_AUTO, 0x03, |
| 105 | ASCOT2E_OFFSET(-2), ASCOT2E_OFFSET(-1), ASCOT2E_BW_8, 0x09, 0x00 }, |
| 106 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x01, |
| 107 | ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_6, 0x09, 0x00 }, |
| 108 | { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x01, |
| 109 | ASCOT2E_OFFSET(-2), ASCOT2E_OFFSET(2), ASCOT2E_BW_8, 0x09, 0x00 } |
| 110 | }; |
| 111 | |
| 112 | static void ascot2e_i2c_debug(struct ascot2e_priv *priv, |
| 113 | u8 reg, u8 write, const u8 *data, u32 len) |
| 114 | { |
| 115 | dev_dbg(&priv->i2c->dev, "ascot2e: I2C %s reg 0x%02x size %d\n", |
| 116 | (write == 0 ? "read" : "write"), reg, len); |
| 117 | print_hex_dump_bytes("ascot2e: I2C data: ", |
| 118 | DUMP_PREFIX_OFFSET, data, len); |
| 119 | } |
| 120 | |
| 121 | static int ascot2e_write_regs(struct ascot2e_priv *priv, |
| 122 | u8 reg, const u8 *data, u32 len) |
| 123 | { |
| 124 | int ret; |
Mauro Carvalho Chehab | 8853780 | 2015-08-11 15:36:15 -0300 | [diff] [blame] | 125 | u8 buf[MAX_WRITE_REGSIZE + 1]; |
Kozlov Sergey | dacf9ce | 2015-07-28 11:33:01 -0300 | [diff] [blame] | 126 | struct i2c_msg msg[1] = { |
| 127 | { |
| 128 | .addr = priv->i2c_address, |
| 129 | .flags = 0, |
Mauro Carvalho Chehab | 8853780 | 2015-08-11 15:36:15 -0300 | [diff] [blame] | 130 | .len = len + 1, |
Kozlov Sergey | dacf9ce | 2015-07-28 11:33:01 -0300 | [diff] [blame] | 131 | .buf = buf, |
| 132 | } |
| 133 | }; |
| 134 | |
Saso Slavicic | cd82982 | 2016-07-13 11:56:22 -0300 | [diff] [blame] | 135 | if (len + 1 > sizeof(buf)) { |
Mauro Carvalho Chehab | 8853780 | 2015-08-11 15:36:15 -0300 | [diff] [blame] | 136 | dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n", |
| 137 | reg, len + 1); |
| 138 | return -E2BIG; |
| 139 | } |
| 140 | |
Kozlov Sergey | dacf9ce | 2015-07-28 11:33:01 -0300 | [diff] [blame] | 141 | ascot2e_i2c_debug(priv, reg, 1, data, len); |
| 142 | buf[0] = reg; |
| 143 | memcpy(&buf[1], data, len); |
| 144 | ret = i2c_transfer(priv->i2c, msg, 1); |
| 145 | if (ret >= 0 && ret != 1) |
| 146 | ret = -EREMOTEIO; |
| 147 | if (ret < 0) { |
| 148 | dev_warn(&priv->i2c->dev, |
| 149 | "%s: i2c wr failed=%d reg=%02x len=%d\n", |
| 150 | KBUILD_MODNAME, ret, reg, len); |
| 151 | return ret; |
| 152 | } |
| 153 | return 0; |
| 154 | } |
| 155 | |
| 156 | static int ascot2e_write_reg(struct ascot2e_priv *priv, u8 reg, u8 val) |
| 157 | { |
| 158 | return ascot2e_write_regs(priv, reg, &val, 1); |
| 159 | } |
| 160 | |
| 161 | static int ascot2e_read_regs(struct ascot2e_priv *priv, |
| 162 | u8 reg, u8 *val, u32 len) |
| 163 | { |
| 164 | int ret; |
| 165 | struct i2c_msg msg[2] = { |
| 166 | { |
| 167 | .addr = priv->i2c_address, |
| 168 | .flags = 0, |
| 169 | .len = 1, |
| 170 | .buf = ®, |
| 171 | }, { |
| 172 | .addr = priv->i2c_address, |
| 173 | .flags = I2C_M_RD, |
| 174 | .len = len, |
| 175 | .buf = val, |
| 176 | } |
| 177 | }; |
| 178 | |
| 179 | ret = i2c_transfer(priv->i2c, &msg[0], 1); |
| 180 | if (ret >= 0 && ret != 1) |
| 181 | ret = -EREMOTEIO; |
| 182 | if (ret < 0) { |
| 183 | dev_warn(&priv->i2c->dev, |
| 184 | "%s: I2C rw failed=%d addr=%02x reg=%02x\n", |
| 185 | KBUILD_MODNAME, ret, priv->i2c_address, reg); |
| 186 | return ret; |
| 187 | } |
| 188 | ret = i2c_transfer(priv->i2c, &msg[1], 1); |
| 189 | if (ret >= 0 && ret != 1) |
| 190 | ret = -EREMOTEIO; |
| 191 | if (ret < 0) { |
| 192 | dev_warn(&priv->i2c->dev, |
| 193 | "%s: i2c rd failed=%d addr=%02x reg=%02x\n", |
| 194 | KBUILD_MODNAME, ret, priv->i2c_address, reg); |
| 195 | return ret; |
| 196 | } |
| 197 | ascot2e_i2c_debug(priv, reg, 0, val, len); |
| 198 | return 0; |
| 199 | } |
| 200 | |
| 201 | static int ascot2e_read_reg(struct ascot2e_priv *priv, u8 reg, u8 *val) |
| 202 | { |
| 203 | return ascot2e_read_regs(priv, reg, val, 1); |
| 204 | } |
| 205 | |
| 206 | static int ascot2e_set_reg_bits(struct ascot2e_priv *priv, |
| 207 | u8 reg, u8 data, u8 mask) |
| 208 | { |
| 209 | int res; |
| 210 | u8 rdata; |
| 211 | |
| 212 | if (mask != 0xff) { |
| 213 | res = ascot2e_read_reg(priv, reg, &rdata); |
| 214 | if (res != 0) |
| 215 | return res; |
| 216 | data = ((data & mask) | (rdata & (mask ^ 0xFF))); |
| 217 | } |
| 218 | return ascot2e_write_reg(priv, reg, data); |
| 219 | } |
| 220 | |
| 221 | static int ascot2e_enter_power_save(struct ascot2e_priv *priv) |
| 222 | { |
| 223 | u8 data[2]; |
| 224 | |
| 225 | dev_dbg(&priv->i2c->dev, "%s()\n", __func__); |
| 226 | if (priv->state == STATE_SLEEP) |
| 227 | return 0; |
| 228 | data[0] = 0x00; |
| 229 | data[1] = 0x04; |
| 230 | ascot2e_write_regs(priv, 0x14, data, 2); |
| 231 | ascot2e_write_reg(priv, 0x50, 0x01); |
| 232 | priv->state = STATE_SLEEP; |
| 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | static int ascot2e_leave_power_save(struct ascot2e_priv *priv) |
| 237 | { |
| 238 | u8 data[2] = { 0xFB, 0x0F }; |
| 239 | |
| 240 | dev_dbg(&priv->i2c->dev, "%s()\n", __func__); |
| 241 | if (priv->state == STATE_ACTIVE) |
| 242 | return 0; |
| 243 | ascot2e_write_regs(priv, 0x14, data, 2); |
| 244 | ascot2e_write_reg(priv, 0x50, 0x00); |
| 245 | priv->state = STATE_ACTIVE; |
| 246 | return 0; |
| 247 | } |
| 248 | |
| 249 | static int ascot2e_init(struct dvb_frontend *fe) |
| 250 | { |
| 251 | struct ascot2e_priv *priv = fe->tuner_priv; |
| 252 | |
| 253 | dev_dbg(&priv->i2c->dev, "%s()\n", __func__); |
| 254 | return ascot2e_leave_power_save(priv); |
| 255 | } |
| 256 | |
Max Kellermann | 194ced7 | 2016-08-09 18:32:31 -0300 | [diff] [blame] | 257 | static void ascot2e_release(struct dvb_frontend *fe) |
Kozlov Sergey | dacf9ce | 2015-07-28 11:33:01 -0300 | [diff] [blame] | 258 | { |
| 259 | struct ascot2e_priv *priv = fe->tuner_priv; |
| 260 | |
| 261 | dev_dbg(&priv->i2c->dev, "%s()\n", __func__); |
| 262 | kfree(fe->tuner_priv); |
| 263 | fe->tuner_priv = NULL; |
Kozlov Sergey | dacf9ce | 2015-07-28 11:33:01 -0300 | [diff] [blame] | 264 | } |
| 265 | |
| 266 | static int ascot2e_sleep(struct dvb_frontend *fe) |
| 267 | { |
| 268 | struct ascot2e_priv *priv = fe->tuner_priv; |
| 269 | |
| 270 | dev_dbg(&priv->i2c->dev, "%s()\n", __func__); |
| 271 | ascot2e_enter_power_save(priv); |
| 272 | return 0; |
| 273 | } |
| 274 | |
| 275 | static enum ascot2e_tv_system_t ascot2e_get_tv_system(struct dvb_frontend *fe) |
| 276 | { |
| 277 | enum ascot2e_tv_system_t system = ASCOT2E_DTV_UNKNOWN; |
| 278 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
| 279 | struct ascot2e_priv *priv = fe->tuner_priv; |
| 280 | |
| 281 | if (p->delivery_system == SYS_DVBT) { |
| 282 | if (p->bandwidth_hz <= 5000000) |
| 283 | system = ASCOT2E_DTV_DVBT_5; |
| 284 | else if (p->bandwidth_hz <= 6000000) |
| 285 | system = ASCOT2E_DTV_DVBT_6; |
| 286 | else if (p->bandwidth_hz <= 7000000) |
| 287 | system = ASCOT2E_DTV_DVBT_7; |
| 288 | else if (p->bandwidth_hz <= 8000000) |
| 289 | system = ASCOT2E_DTV_DVBT_8; |
| 290 | else { |
| 291 | system = ASCOT2E_DTV_DVBT_8; |
| 292 | p->bandwidth_hz = 8000000; |
| 293 | } |
| 294 | } else if (p->delivery_system == SYS_DVBT2) { |
| 295 | if (p->bandwidth_hz <= 5000000) |
| 296 | system = ASCOT2E_DTV_DVBT2_5; |
| 297 | else if (p->bandwidth_hz <= 6000000) |
| 298 | system = ASCOT2E_DTV_DVBT2_6; |
| 299 | else if (p->bandwidth_hz <= 7000000) |
| 300 | system = ASCOT2E_DTV_DVBT2_7; |
| 301 | else if (p->bandwidth_hz <= 8000000) |
| 302 | system = ASCOT2E_DTV_DVBT2_8; |
| 303 | else { |
| 304 | system = ASCOT2E_DTV_DVBT2_8; |
| 305 | p->bandwidth_hz = 8000000; |
| 306 | } |
| 307 | } else if (p->delivery_system == SYS_DVBC_ANNEX_A) { |
| 308 | if (p->bandwidth_hz <= 6000000) |
| 309 | system = ASCOT2E_DTV_DVBC_6; |
| 310 | else if (p->bandwidth_hz <= 8000000) |
| 311 | system = ASCOT2E_DTV_DVBC_8; |
| 312 | } |
| 313 | dev_dbg(&priv->i2c->dev, |
| 314 | "%s(): ASCOT2E DTV system %d (delsys %d, bandwidth %d)\n", |
| 315 | __func__, (int)system, p->delivery_system, p->bandwidth_hz); |
| 316 | return system; |
| 317 | } |
| 318 | |
| 319 | static int ascot2e_set_params(struct dvb_frontend *fe) |
| 320 | { |
| 321 | u8 data[10]; |
| 322 | u32 frequency; |
| 323 | enum ascot2e_tv_system_t tv_system; |
| 324 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
| 325 | struct ascot2e_priv *priv = fe->tuner_priv; |
| 326 | |
| 327 | dev_dbg(&priv->i2c->dev, "%s(): tune frequency %dkHz\n", |
| 328 | __func__, p->frequency / 1000); |
| 329 | tv_system = ascot2e_get_tv_system(fe); |
| 330 | |
| 331 | if (tv_system == ASCOT2E_DTV_UNKNOWN) { |
| 332 | dev_dbg(&priv->i2c->dev, "%s(): unknown DTV system\n", |
| 333 | __func__); |
| 334 | return -EINVAL; |
| 335 | } |
| 336 | if (priv->set_tuner) |
| 337 | priv->set_tuner(priv->set_tuner_data, 1); |
| 338 | frequency = roundup(p->frequency / 1000, 25); |
| 339 | if (priv->state == STATE_SLEEP) |
| 340 | ascot2e_leave_power_save(priv); |
| 341 | |
| 342 | /* IF_OUT_SEL / AGC_SEL setting */ |
| 343 | data[0] = 0x00; |
| 344 | if (ascot2e_sett[tv_system].agc_sel != ASCOT2E_AUTO) { |
| 345 | /* AGC pin setting from parameter table */ |
| 346 | data[0] |= (u8)( |
| 347 | (ascot2e_sett[tv_system].agc_sel & 0x03) << 3); |
| 348 | } |
| 349 | if (ascot2e_sett[tv_system].if_out_sel != ASCOT2E_AUTO) { |
| 350 | /* IFOUT pin setting from parameter table */ |
| 351 | data[0] |= (u8)( |
| 352 | (ascot2e_sett[tv_system].if_out_sel & 0x01) << 2); |
| 353 | } |
| 354 | /* Set bit[4:2] only */ |
| 355 | ascot2e_set_reg_bits(priv, 0x05, data[0], 0x1c); |
| 356 | /* 0x06 - 0x0F */ |
| 357 | /* REF_R setting (0x06) */ |
| 358 | if (tv_system == ASCOT2E_DTV_DVBC_6 || |
| 359 | tv_system == ASCOT2E_DTV_DVBC_8) { |
| 360 | /* xtal, xtal*2 */ |
| 361 | data[0] = (frequency > 500000) ? 16 : 32; |
| 362 | } else { |
| 363 | /* xtal/8, xtal/4 */ |
| 364 | data[0] = (frequency > 500000) ? 2 : 4; |
| 365 | } |
| 366 | /* XOSC_SEL=100uA */ |
| 367 | data[1] = 0x04; |
| 368 | /* KBW setting (0x08), KC0 setting (0x09), KC1 setting (0x0A) */ |
| 369 | if (tv_system == ASCOT2E_DTV_DVBC_6 || |
| 370 | tv_system == ASCOT2E_DTV_DVBC_8) { |
| 371 | data[2] = 18; |
| 372 | data[3] = 120; |
| 373 | data[4] = 20; |
| 374 | } else { |
| 375 | data[2] = 48; |
| 376 | data[3] = 10; |
| 377 | data[4] = 30; |
| 378 | } |
| 379 | /* ORDER/R2_RANGE/R2_BANK/C2_BANK setting (0x0B) */ |
| 380 | if (tv_system == ASCOT2E_DTV_DVBC_6 || |
| 381 | tv_system == ASCOT2E_DTV_DVBC_8) |
| 382 | data[5] = (frequency > 500000) ? 0x08 : 0x0c; |
| 383 | else |
| 384 | data[5] = (frequency > 500000) ? 0x30 : 0x38; |
| 385 | /* Set MIX_OLL (0x0C) value from parameter table */ |
| 386 | data[6] = ascot2e_sett[tv_system].mix_oll; |
| 387 | /* Set RF_GAIN (0x0D) setting from parameter table */ |
| 388 | if (ascot2e_sett[tv_system].rf_gain == ASCOT2E_AUTO) { |
| 389 | /* RF_GAIN auto control enable */ |
| 390 | ascot2e_write_reg(priv, 0x4E, 0x01); |
| 391 | /* RF_GAIN Default value */ |
| 392 | data[7] = 0x00; |
| 393 | } else { |
| 394 | /* RF_GAIN auto control disable */ |
| 395 | ascot2e_write_reg(priv, 0x4E, 0x00); |
| 396 | data[7] = ascot2e_sett[tv_system].rf_gain; |
| 397 | } |
| 398 | /* Set IF_BPF_GC/FIF_OFFSET (0x0E) value from parameter table */ |
| 399 | data[8] = (u8)((ascot2e_sett[tv_system].fif_offset << 3) | |
| 400 | (ascot2e_sett[tv_system].if_bpf_gc & 0x07)); |
| 401 | /* Set BW_OFFSET (0x0F) value from parameter table */ |
| 402 | data[9] = ascot2e_sett[tv_system].bw_offset; |
| 403 | ascot2e_write_regs(priv, 0x06, data, 10); |
| 404 | /* |
| 405 | * 0x45 - 0x47 |
| 406 | * LNA optimization setting |
| 407 | * RF_LNA_DIST1-5, RF_LNA_CM |
| 408 | */ |
| 409 | if (tv_system == ASCOT2E_DTV_DVBC_6 || |
| 410 | tv_system == ASCOT2E_DTV_DVBC_8) { |
| 411 | data[0] = 0x0F; |
| 412 | data[1] = 0x00; |
| 413 | data[2] = 0x01; |
| 414 | } else { |
| 415 | data[0] = 0x0F; |
| 416 | data[1] = 0x00; |
| 417 | data[2] = 0x03; |
| 418 | } |
| 419 | ascot2e_write_regs(priv, 0x45, data, 3); |
| 420 | /* 0x49 - 0x4A |
| 421 | Set RF_OLDET_ENX/RF_OLDET_OLL value from parameter table */ |
| 422 | data[0] = ascot2e_sett[tv_system].rf_oldet; |
| 423 | /* Set IF_BPF_F0 value from parameter table */ |
| 424 | data[1] = ascot2e_sett[tv_system].if_bpf_f0; |
| 425 | ascot2e_write_regs(priv, 0x49, data, 2); |
| 426 | /* |
| 427 | * Tune now |
| 428 | * RFAGC fast mode / RFAGC auto control enable |
| 429 | * (set bit[7], bit[5:4] only) |
| 430 | * vco_cal = 1, set MIX_OL_CPU_EN |
| 431 | */ |
| 432 | ascot2e_set_reg_bits(priv, 0x0c, 0x90, 0xb0); |
| 433 | /* Logic wake up, CPU wake up */ |
| 434 | data[0] = 0xc4; |
| 435 | data[1] = 0x40; |
| 436 | ascot2e_write_regs(priv, 0x03, data, 2); |
| 437 | /* 0x10 - 0x14 */ |
| 438 | data[0] = (u8)(frequency & 0xFF); /* 0x10: FRF_L */ |
| 439 | data[1] = (u8)((frequency >> 8) & 0xFF); /* 0x11: FRF_M */ |
| 440 | data[2] = (u8)((frequency >> 16) & 0x0F); /* 0x12: FRF_H (bit[3:0]) */ |
| 441 | /* 0x12: BW (bit[5:4]) */ |
| 442 | data[2] |= (u8)(ascot2e_sett[tv_system].bw << 4); |
| 443 | data[3] = 0xFF; /* 0x13: VCO calibration enable */ |
| 444 | data[4] = 0xFF; /* 0x14: Analog block enable */ |
| 445 | /* Tune (Burst write) */ |
| 446 | ascot2e_write_regs(priv, 0x10, data, 5); |
| 447 | msleep(50); |
| 448 | /* CPU deep sleep */ |
| 449 | ascot2e_write_reg(priv, 0x04, 0x00); |
| 450 | /* Logic sleep */ |
| 451 | ascot2e_write_reg(priv, 0x03, 0xC0); |
| 452 | /* RFAGC normal mode (set bit[5:4] only) */ |
| 453 | ascot2e_set_reg_bits(priv, 0x0C, 0x00, 0x30); |
| 454 | priv->frequency = frequency; |
| 455 | return 0; |
| 456 | } |
| 457 | |
| 458 | static int ascot2e_get_frequency(struct dvb_frontend *fe, u32 *frequency) |
| 459 | { |
| 460 | struct ascot2e_priv *priv = fe->tuner_priv; |
| 461 | |
| 462 | *frequency = priv->frequency * 1000; |
| 463 | return 0; |
| 464 | } |
| 465 | |
Julia Lawall | 14c4bf3 | 2016-09-11 11:44:12 -0300 | [diff] [blame] | 466 | static const struct dvb_tuner_ops ascot2e_tuner_ops = { |
Kozlov Sergey | dacf9ce | 2015-07-28 11:33:01 -0300 | [diff] [blame] | 467 | .info = { |
| 468 | .name = "Sony ASCOT2E", |
| 469 | .frequency_min = 1000000, |
| 470 | .frequency_max = 1200000000, |
| 471 | .frequency_step = 25000, |
| 472 | }, |
| 473 | .init = ascot2e_init, |
| 474 | .release = ascot2e_release, |
| 475 | .sleep = ascot2e_sleep, |
| 476 | .set_params = ascot2e_set_params, |
| 477 | .get_frequency = ascot2e_get_frequency, |
| 478 | }; |
| 479 | |
| 480 | struct dvb_frontend *ascot2e_attach(struct dvb_frontend *fe, |
| 481 | const struct ascot2e_config *config, |
| 482 | struct i2c_adapter *i2c) |
| 483 | { |
| 484 | u8 data[4]; |
| 485 | struct ascot2e_priv *priv = NULL; |
| 486 | |
| 487 | priv = kzalloc(sizeof(struct ascot2e_priv), GFP_KERNEL); |
| 488 | if (priv == NULL) |
| 489 | return NULL; |
| 490 | priv->i2c_address = (config->i2c_address >> 1); |
| 491 | priv->i2c = i2c; |
| 492 | priv->set_tuner_data = config->set_tuner_priv; |
| 493 | priv->set_tuner = config->set_tuner_callback; |
| 494 | |
| 495 | if (fe->ops.i2c_gate_ctrl) |
| 496 | fe->ops.i2c_gate_ctrl(fe, 1); |
| 497 | |
| 498 | /* 16 MHz xTal frequency */ |
| 499 | data[0] = 16; |
| 500 | /* VCO current setting */ |
| 501 | data[1] = 0x06; |
| 502 | /* Logic wake up, CPU boot */ |
| 503 | data[2] = 0xC4; |
| 504 | data[3] = 0x40; |
| 505 | ascot2e_write_regs(priv, 0x01, data, 4); |
| 506 | /* RFVGA optimization setting (RF_DIST0 - RF_DIST2) */ |
| 507 | data[0] = 0x10; |
| 508 | data[1] = 0x3F; |
| 509 | data[2] = 0x25; |
| 510 | ascot2e_write_regs(priv, 0x22, data, 3); |
| 511 | /* PLL mode setting */ |
| 512 | ascot2e_write_reg(priv, 0x28, 0x1e); |
| 513 | /* RSSI setting */ |
| 514 | ascot2e_write_reg(priv, 0x59, 0x04); |
| 515 | /* TODO check CPU HW error state here */ |
| 516 | msleep(80); |
| 517 | /* Xtal oscillator current control setting */ |
| 518 | ascot2e_write_reg(priv, 0x4c, 0x01); |
| 519 | /* XOSC_SEL=100uA */ |
| 520 | ascot2e_write_reg(priv, 0x07, 0x04); |
| 521 | /* CPU deep sleep */ |
| 522 | ascot2e_write_reg(priv, 0x04, 0x00); |
| 523 | /* Logic sleep */ |
| 524 | ascot2e_write_reg(priv, 0x03, 0xc0); |
| 525 | /* Power save setting */ |
| 526 | data[0] = 0x00; |
| 527 | data[1] = 0x04; |
| 528 | ascot2e_write_regs(priv, 0x14, data, 2); |
| 529 | ascot2e_write_reg(priv, 0x50, 0x01); |
| 530 | priv->state = STATE_SLEEP; |
| 531 | |
| 532 | if (fe->ops.i2c_gate_ctrl) |
| 533 | fe->ops.i2c_gate_ctrl(fe, 0); |
| 534 | |
| 535 | memcpy(&fe->ops.tuner_ops, &ascot2e_tuner_ops, |
| 536 | sizeof(struct dvb_tuner_ops)); |
| 537 | fe->tuner_priv = priv; |
| 538 | dev_info(&priv->i2c->dev, |
| 539 | "Sony ASCOT2E attached on addr=%x at I2C adapter %p\n", |
| 540 | priv->i2c_address, priv->i2c); |
| 541 | return fe; |
| 542 | } |
| 543 | EXPORT_SYMBOL(ascot2e_attach); |
| 544 | |
| 545 | MODULE_DESCRIPTION("Sony ASCOT2E terr/cab tuner driver"); |
| 546 | MODULE_AUTHOR("info@netup.ru"); |
| 547 | MODULE_LICENSE("GPL"); |