Fabio Estevam | 014e420 | 2018-05-21 23:32:54 -0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | // |
| 3 | // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> |
| 4 | // Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
| 5 | // |
| 6 | // Based on code from Freescale Semiconductor, |
| 7 | // Authors: Daniel Mack, Juergen Beisert. |
| 8 | // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 9 | |
Anson Huang | 2808801 | 2018-05-22 11:05:40 +0800 | [diff] [blame] | 10 | #include <linux/clk.h> |
Fabio Estevam | 18f92b1 | 2013-07-22 18:17:52 -0300 | [diff] [blame] | 11 | #include <linux/err.h> |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 12 | #include <linux/init.h> |
Dinh Nguyen | a3484ff | 2010-10-23 09:12:48 -0500 | [diff] [blame] | 13 | #include <linux/interrupt.h> |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 14 | #include <linux/io.h> |
| 15 | #include <linux/irq.h> |
Shawn Guo | 1ab7ef1 | 2012-06-13 09:04:03 +0800 | [diff] [blame] | 16 | #include <linux/irqdomain.h> |
Catalin Marinas | de88cbb | 2013-01-18 15:31:37 +0000 | [diff] [blame] | 17 | #include <linux/irqchip/chained_irq.h> |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/slab.h> |
Anson Huang | 1a5287a | 2018-11-09 04:56:56 +0000 | [diff] [blame] | 20 | #include <linux/syscore_ops.h> |
Linus Walleij | 0f4630f | 2015-12-04 14:02:58 +0100 | [diff] [blame] | 21 | #include <linux/gpio/driver.h> |
Shawn Guo | 8937cb6 | 2011-07-07 00:37:43 +0800 | [diff] [blame] | 22 | #include <linux/of.h> |
| 23 | #include <linux/of_device.h> |
Christoph Hellwig | 16c3bd3 | 2015-08-28 09:27:22 +0200 | [diff] [blame] | 24 | #include <linux/bug.h> |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 25 | |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 26 | enum mxc_gpio_hwtype { |
| 27 | IMX1_GPIO, /* runs on i.mx1 */ |
| 28 | IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 29 | IMX31_GPIO, /* runs on i.mx31 */ |
| 30 | IMX35_GPIO, /* runs on all other i.mx */ |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 31 | }; |
| 32 | |
| 33 | /* device type dependent stuff */ |
| 34 | struct mxc_gpio_hwdata { |
| 35 | unsigned dr_reg; |
| 36 | unsigned gdir_reg; |
| 37 | unsigned psr_reg; |
| 38 | unsigned icr1_reg; |
| 39 | unsigned icr2_reg; |
| 40 | unsigned imr_reg; |
| 41 | unsigned isr_reg; |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 42 | int edge_sel_reg; |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 43 | unsigned low_level; |
| 44 | unsigned high_level; |
| 45 | unsigned rise_edge; |
| 46 | unsigned fall_edge; |
| 47 | }; |
| 48 | |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 49 | struct mxc_gpio_reg_saved { |
| 50 | u32 icr1; |
| 51 | u32 icr2; |
| 52 | u32 imr; |
| 53 | u32 gdir; |
| 54 | u32 edge_sel; |
| 55 | u32 dr; |
| 56 | }; |
| 57 | |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 58 | struct mxc_gpio_port { |
| 59 | struct list_head node; |
| 60 | void __iomem *base; |
Anson Huang | 2808801 | 2018-05-22 11:05:40 +0800 | [diff] [blame] | 61 | struct clk *clk; |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 62 | int irq; |
| 63 | int irq_high; |
Shawn Guo | 1ab7ef1 | 2012-06-13 09:04:03 +0800 | [diff] [blame] | 64 | struct irq_domain *domain; |
Linus Walleij | 0f4630f | 2015-12-04 14:02:58 +0100 | [diff] [blame] | 65 | struct gpio_chip gc; |
Bartosz Golaszewski | db5270a | 2017-08-09 14:25:06 +0200 | [diff] [blame] | 66 | struct device *dev; |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 67 | u32 both_edges; |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 68 | struct mxc_gpio_reg_saved gpio_saved_reg; |
| 69 | bool power_off; |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 70 | }; |
| 71 | |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 72 | static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { |
| 73 | .dr_reg = 0x1c, |
| 74 | .gdir_reg = 0x00, |
| 75 | .psr_reg = 0x24, |
| 76 | .icr1_reg = 0x28, |
| 77 | .icr2_reg = 0x2c, |
| 78 | .imr_reg = 0x30, |
| 79 | .isr_reg = 0x34, |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 80 | .edge_sel_reg = -EINVAL, |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 81 | .low_level = 0x03, |
| 82 | .high_level = 0x02, |
| 83 | .rise_edge = 0x00, |
| 84 | .fall_edge = 0x01, |
| 85 | }; |
| 86 | |
| 87 | static struct mxc_gpio_hwdata imx31_gpio_hwdata = { |
| 88 | .dr_reg = 0x00, |
| 89 | .gdir_reg = 0x04, |
| 90 | .psr_reg = 0x08, |
| 91 | .icr1_reg = 0x0c, |
| 92 | .icr2_reg = 0x10, |
| 93 | .imr_reg = 0x14, |
| 94 | .isr_reg = 0x18, |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 95 | .edge_sel_reg = -EINVAL, |
| 96 | .low_level = 0x00, |
| 97 | .high_level = 0x01, |
| 98 | .rise_edge = 0x02, |
| 99 | .fall_edge = 0x03, |
| 100 | }; |
| 101 | |
| 102 | static struct mxc_gpio_hwdata imx35_gpio_hwdata = { |
| 103 | .dr_reg = 0x00, |
| 104 | .gdir_reg = 0x04, |
| 105 | .psr_reg = 0x08, |
| 106 | .icr1_reg = 0x0c, |
| 107 | .icr2_reg = 0x10, |
| 108 | .imr_reg = 0x14, |
| 109 | .isr_reg = 0x18, |
| 110 | .edge_sel_reg = 0x1c, |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 111 | .low_level = 0x00, |
| 112 | .high_level = 0x01, |
| 113 | .rise_edge = 0x02, |
| 114 | .fall_edge = 0x03, |
| 115 | }; |
| 116 | |
| 117 | static enum mxc_gpio_hwtype mxc_gpio_hwtype; |
| 118 | static struct mxc_gpio_hwdata *mxc_gpio_hwdata; |
| 119 | |
| 120 | #define GPIO_DR (mxc_gpio_hwdata->dr_reg) |
| 121 | #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg) |
| 122 | #define GPIO_PSR (mxc_gpio_hwdata->psr_reg) |
| 123 | #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg) |
| 124 | #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg) |
| 125 | #define GPIO_IMR (mxc_gpio_hwdata->imr_reg) |
| 126 | #define GPIO_ISR (mxc_gpio_hwdata->isr_reg) |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 127 | #define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg) |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 128 | |
| 129 | #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level) |
| 130 | #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level) |
| 131 | #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge) |
| 132 | #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge) |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 133 | #define GPIO_INT_BOTH_EDGES 0x4 |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 134 | |
Krzysztof Kozlowski | f4f79d4 | 2015-05-02 00:56:47 +0900 | [diff] [blame] | 135 | static const struct platform_device_id mxc_gpio_devtype[] = { |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 136 | { |
| 137 | .name = "imx1-gpio", |
| 138 | .driver_data = IMX1_GPIO, |
| 139 | }, { |
| 140 | .name = "imx21-gpio", |
| 141 | .driver_data = IMX21_GPIO, |
| 142 | }, { |
| 143 | .name = "imx31-gpio", |
| 144 | .driver_data = IMX31_GPIO, |
| 145 | }, { |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 146 | .name = "imx35-gpio", |
| 147 | .driver_data = IMX35_GPIO, |
| 148 | }, { |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 149 | /* sentinel */ |
| 150 | } |
| 151 | }; |
| 152 | |
Shawn Guo | 8937cb6 | 2011-07-07 00:37:43 +0800 | [diff] [blame] | 153 | static const struct of_device_id mxc_gpio_dt_ids[] = { |
| 154 | { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], }, |
| 155 | { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], }, |
| 156 | { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], }, |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 157 | { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 158 | { .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], }, |
Shawn Guo | 8937cb6 | 2011-07-07 00:37:43 +0800 | [diff] [blame] | 159 | { /* sentinel */ } |
| 160 | }; |
| 161 | |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 162 | /* |
| 163 | * MX2 has one interrupt *for all* gpio ports. The list is used |
| 164 | * to save the references to all ports, so that mx2_gpio_irq_handler |
| 165 | * can walk through all interrupt status registers. |
| 166 | */ |
| 167 | static LIST_HEAD(mxc_gpio_ports); |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 168 | |
| 169 | /* Note: This driver assumes 32 GPIOs are handled in one register */ |
| 170 | |
Lennert Buytenhek | 4d93579 | 2010-11-29 11:16:23 +0100 | [diff] [blame] | 171 | static int gpio_set_irq_type(struct irq_data *d, u32 type) |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 172 | { |
Shawn Guo | e4ea933 | 2011-06-07 16:25:37 +0800 | [diff] [blame] | 173 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 174 | struct mxc_gpio_port *port = gc->private; |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 175 | u32 bit, val; |
Shawn Guo | 1ab7ef1 | 2012-06-13 09:04:03 +0800 | [diff] [blame] | 176 | u32 gpio_idx = d->hwirq; |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 177 | int edge; |
| 178 | void __iomem *reg = port->base; |
| 179 | |
Shawn Guo | 1ab7ef1 | 2012-06-13 09:04:03 +0800 | [diff] [blame] | 180 | port->both_edges &= ~(1 << gpio_idx); |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 181 | switch (type) { |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 182 | case IRQ_TYPE_EDGE_RISING: |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 183 | edge = GPIO_INT_RISE_EDGE; |
| 184 | break; |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 185 | case IRQ_TYPE_EDGE_FALLING: |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 186 | edge = GPIO_INT_FALL_EDGE; |
| 187 | break; |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 188 | case IRQ_TYPE_EDGE_BOTH: |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 189 | if (GPIO_EDGE_SEL >= 0) { |
| 190 | edge = GPIO_INT_BOTH_EDGES; |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 191 | } else { |
Linus Walleij | 8d0bd9a | 2018-04-15 22:25:00 +0200 | [diff] [blame] | 192 | val = port->gc.get(&port->gc, gpio_idx); |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 193 | if (val) { |
| 194 | edge = GPIO_INT_LOW_LEV; |
Linus Walleij | 8d0bd9a | 2018-04-15 22:25:00 +0200 | [diff] [blame] | 195 | pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 196 | } else { |
| 197 | edge = GPIO_INT_HIGH_LEV; |
Linus Walleij | 8d0bd9a | 2018-04-15 22:25:00 +0200 | [diff] [blame] | 198 | pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 199 | } |
Linus Torvalds | f948ad0 | 2012-07-26 13:56:38 -0700 | [diff] [blame] | 200 | port->both_edges |= 1 << gpio_idx; |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 201 | } |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 202 | break; |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 203 | case IRQ_TYPE_LEVEL_LOW: |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 204 | edge = GPIO_INT_LOW_LEV; |
| 205 | break; |
Dmitry Baryshkov | 6cab486 | 2008-07-27 04:23:31 +0100 | [diff] [blame] | 206 | case IRQ_TYPE_LEVEL_HIGH: |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 207 | edge = GPIO_INT_HIGH_LEV; |
| 208 | break; |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 209 | default: |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 210 | return -EINVAL; |
| 211 | } |
| 212 | |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 213 | if (GPIO_EDGE_SEL >= 0) { |
| 214 | val = readl(port->base + GPIO_EDGE_SEL); |
| 215 | if (edge == GPIO_INT_BOTH_EDGES) |
Linus Torvalds | f948ad0 | 2012-07-26 13:56:38 -0700 | [diff] [blame] | 216 | writel(val | (1 << gpio_idx), |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 217 | port->base + GPIO_EDGE_SEL); |
| 218 | else |
Linus Torvalds | f948ad0 | 2012-07-26 13:56:38 -0700 | [diff] [blame] | 219 | writel(val & ~(1 << gpio_idx), |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 220 | port->base + GPIO_EDGE_SEL); |
| 221 | } |
| 222 | |
| 223 | if (edge != GPIO_INT_BOTH_EDGES) { |
Linus Torvalds | f948ad0 | 2012-07-26 13:56:38 -0700 | [diff] [blame] | 224 | reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ |
| 225 | bit = gpio_idx & 0xf; |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 226 | val = readl(reg) & ~(0x3 << (bit << 1)); |
| 227 | writel(val | (edge << (bit << 1)), reg); |
| 228 | } |
| 229 | |
Shawn Guo | 1ab7ef1 | 2012-06-13 09:04:03 +0800 | [diff] [blame] | 230 | writel(1 << gpio_idx, port->base + GPIO_ISR); |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 231 | |
| 232 | return 0; |
| 233 | } |
| 234 | |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 235 | static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) |
| 236 | { |
| 237 | void __iomem *reg = port->base; |
| 238 | u32 bit, val; |
| 239 | int edge; |
| 240 | |
| 241 | reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ |
| 242 | bit = gpio & 0xf; |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 243 | val = readl(reg); |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 244 | edge = (val >> (bit << 1)) & 3; |
| 245 | val &= ~(0x3 << (bit << 1)); |
Uwe Kleine-König | 3d40f7f | 2010-02-05 22:14:37 +0100 | [diff] [blame] | 246 | if (edge == GPIO_INT_HIGH_LEV) { |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 247 | edge = GPIO_INT_LOW_LEV; |
| 248 | pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); |
Uwe Kleine-König | 3d40f7f | 2010-02-05 22:14:37 +0100 | [diff] [blame] | 249 | } else if (edge == GPIO_INT_LOW_LEV) { |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 250 | edge = GPIO_INT_HIGH_LEV; |
| 251 | pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); |
Uwe Kleine-König | 3d40f7f | 2010-02-05 22:14:37 +0100 | [diff] [blame] | 252 | } else { |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 253 | pr_err("mxc: invalid configuration for GPIO %d: %x\n", |
| 254 | gpio, edge); |
| 255 | return; |
| 256 | } |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 257 | writel(val | (edge << (bit << 1)), reg); |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 258 | } |
| 259 | |
Uwe Kleine-König | 3621f18 | 2010-02-08 21:02:30 +0100 | [diff] [blame] | 260 | /* handle 32 interrupts in one status register */ |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 261 | static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) |
| 262 | { |
Uwe Kleine-König | 3621f18 | 2010-02-08 21:02:30 +0100 | [diff] [blame] | 263 | while (irq_stat != 0) { |
| 264 | int irqoffset = fls(irq_stat) - 1; |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 265 | |
Uwe Kleine-König | 3621f18 | 2010-02-08 21:02:30 +0100 | [diff] [blame] | 266 | if (port->both_edges & (1 << irqoffset)) |
| 267 | mxc_flip_edge(port, irqoffset); |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 268 | |
Shawn Guo | 1ab7ef1 | 2012-06-13 09:04:03 +0800 | [diff] [blame] | 269 | generic_handle_irq(irq_find_mapping(port->domain, irqoffset)); |
Guennadi Liakhovetski | 910862e | 2009-03-12 12:46:41 +0100 | [diff] [blame] | 270 | |
Uwe Kleine-König | 3621f18 | 2010-02-08 21:02:30 +0100 | [diff] [blame] | 271 | irq_stat &= ~(1 << irqoffset); |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 272 | } |
| 273 | } |
| 274 | |
Paulius Zaleckas | cfca8b5 | 2008-11-14 11:01:38 +0100 | [diff] [blame] | 275 | /* MX1 and MX3 has one interrupt *per* gpio port */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 276 | static void mx3_gpio_irq_handler(struct irq_desc *desc) |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 277 | { |
| 278 | u32 irq_stat; |
Jiang Liu | 476f8b4 | 2015-06-04 12:13:15 +0800 | [diff] [blame] | 279 | struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); |
| 280 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Shawn Guo | 0e44b6e | 2011-09-21 21:24:04 +0800 | [diff] [blame] | 281 | |
| 282 | chained_irq_enter(chip, desc); |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 283 | |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 284 | irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); |
Sascha Hauer | e2c97e7 | 2009-04-21 12:39:59 +0200 | [diff] [blame] | 285 | |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 286 | mxc_gpio_irq_handler(port, irq_stat); |
Shawn Guo | 0e44b6e | 2011-09-21 21:24:04 +0800 | [diff] [blame] | 287 | |
| 288 | chained_irq_exit(chip, desc); |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 289 | } |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 290 | |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 291 | /* MX2 has one interrupt *for all* gpio ports */ |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 292 | static void mx2_gpio_irq_handler(struct irq_desc *desc) |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 293 | { |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 294 | u32 irq_msk, irq_stat; |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 295 | struct mxc_gpio_port *port; |
Jiang Liu | 476f8b4 | 2015-06-04 12:13:15 +0800 | [diff] [blame] | 296 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Uwe Kleine-König | c0e811d | 2013-07-18 14:58:06 +0200 | [diff] [blame] | 297 | |
| 298 | chained_irq_enter(chip, desc); |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 299 | |
| 300 | /* walk through all interrupt status registers */ |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 301 | list_for_each_entry(port, &mxc_gpio_ports, node) { |
| 302 | irq_msk = readl(port->base + GPIO_IMR); |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 303 | if (!irq_msk) |
| 304 | continue; |
| 305 | |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 306 | irq_stat = readl(port->base + GPIO_ISR) & irq_msk; |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 307 | if (irq_stat) |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 308 | mxc_gpio_irq_handler(port, irq_stat); |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 309 | } |
Uwe Kleine-König | c0e811d | 2013-07-18 14:58:06 +0200 | [diff] [blame] | 310 | chained_irq_exit(chip, desc); |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 311 | } |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 312 | |
Dinh Nguyen | a3484ff | 2010-10-23 09:12:48 -0500 | [diff] [blame] | 313 | /* |
| 314 | * Set interrupt number "irq" in the GPIO as a wake-up source. |
| 315 | * While system is running, all registered GPIO interrupts need to have |
| 316 | * wake-up enabled. When system is suspended, only selected GPIO interrupts |
| 317 | * need to have wake-up enabled. |
| 318 | * @param irq interrupt source number |
| 319 | * @param enable enable as wake-up if equal to non-zero |
| 320 | * @return This function returns 0 on success. |
| 321 | */ |
Lennert Buytenhek | 4d93579 | 2010-11-29 11:16:23 +0100 | [diff] [blame] | 322 | static int gpio_set_wake_irq(struct irq_data *d, u32 enable) |
Dinh Nguyen | a3484ff | 2010-10-23 09:12:48 -0500 | [diff] [blame] | 323 | { |
Shawn Guo | e4ea933 | 2011-06-07 16:25:37 +0800 | [diff] [blame] | 324 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 325 | struct mxc_gpio_port *port = gc->private; |
Shawn Guo | 1ab7ef1 | 2012-06-13 09:04:03 +0800 | [diff] [blame] | 326 | u32 gpio_idx = d->hwirq; |
Philipp Rosenberger | 77a4d75 | 2017-07-12 10:36:40 +0200 | [diff] [blame] | 327 | int ret; |
Dinh Nguyen | a3484ff | 2010-10-23 09:12:48 -0500 | [diff] [blame] | 328 | |
| 329 | if (enable) { |
| 330 | if (port->irq_high && (gpio_idx >= 16)) |
Philipp Rosenberger | 77a4d75 | 2017-07-12 10:36:40 +0200 | [diff] [blame] | 331 | ret = enable_irq_wake(port->irq_high); |
Dinh Nguyen | a3484ff | 2010-10-23 09:12:48 -0500 | [diff] [blame] | 332 | else |
Philipp Rosenberger | 77a4d75 | 2017-07-12 10:36:40 +0200 | [diff] [blame] | 333 | ret = enable_irq_wake(port->irq); |
Dinh Nguyen | a3484ff | 2010-10-23 09:12:48 -0500 | [diff] [blame] | 334 | } else { |
| 335 | if (port->irq_high && (gpio_idx >= 16)) |
Philipp Rosenberger | 77a4d75 | 2017-07-12 10:36:40 +0200 | [diff] [blame] | 336 | ret = disable_irq_wake(port->irq_high); |
Dinh Nguyen | a3484ff | 2010-10-23 09:12:48 -0500 | [diff] [blame] | 337 | else |
Philipp Rosenberger | 77a4d75 | 2017-07-12 10:36:40 +0200 | [diff] [blame] | 338 | ret = disable_irq_wake(port->irq); |
Dinh Nguyen | a3484ff | 2010-10-23 09:12:48 -0500 | [diff] [blame] | 339 | } |
| 340 | |
Philipp Rosenberger | 77a4d75 | 2017-07-12 10:36:40 +0200 | [diff] [blame] | 341 | return ret; |
Dinh Nguyen | a3484ff | 2010-10-23 09:12:48 -0500 | [diff] [blame] | 342 | } |
| 343 | |
Peng Fan | 9e26b0b | 2015-08-23 21:11:52 +0800 | [diff] [blame] | 344 | static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) |
Shawn Guo | e4ea933 | 2011-06-07 16:25:37 +0800 | [diff] [blame] | 345 | { |
| 346 | struct irq_chip_generic *gc; |
| 347 | struct irq_chip_type *ct; |
Bartosz Golaszewski | db5270a | 2017-08-09 14:25:06 +0200 | [diff] [blame] | 348 | int rv; |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 349 | |
Bartosz Golaszewski | db5270a | 2017-08-09 14:25:06 +0200 | [diff] [blame] | 350 | gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, |
| 351 | port->base, handle_level_irq); |
Peng Fan | 9e26b0b | 2015-08-23 21:11:52 +0800 | [diff] [blame] | 352 | if (!gc) |
| 353 | return -ENOMEM; |
Shawn Guo | e4ea933 | 2011-06-07 16:25:37 +0800 | [diff] [blame] | 354 | gc->private = port; |
| 355 | |
| 356 | ct = gc->chip_types; |
Shawn Guo | 591567a | 2011-07-19 21:16:56 +0800 | [diff] [blame] | 357 | ct->chip.irq_ack = irq_gc_ack_set_bit; |
Shawn Guo | e4ea933 | 2011-06-07 16:25:37 +0800 | [diff] [blame] | 358 | ct->chip.irq_mask = irq_gc_mask_clr_bit; |
| 359 | ct->chip.irq_unmask = irq_gc_mask_set_bit; |
| 360 | ct->chip.irq_set_type = gpio_set_irq_type; |
Shawn Guo | 591567a | 2011-07-19 21:16:56 +0800 | [diff] [blame] | 361 | ct->chip.irq_set_wake = gpio_set_wake_irq; |
Ulises Brindis | 952cfbd | 2015-08-05 10:23:07 -0700 | [diff] [blame] | 362 | ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; |
Shawn Guo | e4ea933 | 2011-06-07 16:25:37 +0800 | [diff] [blame] | 363 | ct->regs.ack = GPIO_ISR; |
| 364 | ct->regs.mask = GPIO_IMR; |
| 365 | |
Bartosz Golaszewski | db5270a | 2017-08-09 14:25:06 +0200 | [diff] [blame] | 366 | rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), |
| 367 | IRQ_GC_INIT_NESTED_LOCK, |
| 368 | IRQ_NOREQUEST, 0); |
Peng Fan | 9e26b0b | 2015-08-23 21:11:52 +0800 | [diff] [blame] | 369 | |
Bartosz Golaszewski | db5270a | 2017-08-09 14:25:06 +0200 | [diff] [blame] | 370 | return rv; |
Shawn Guo | e4ea933 | 2011-06-07 16:25:37 +0800 | [diff] [blame] | 371 | } |
Thomas Gleixner | b5eee2f | 2011-04-04 14:29:58 +0200 | [diff] [blame] | 372 | |
Bill Pemberton | 3836309 | 2012-11-19 13:22:34 -0500 | [diff] [blame] | 373 | static void mxc_gpio_get_hw(struct platform_device *pdev) |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 374 | { |
Shawn Guo | 8937cb6 | 2011-07-07 00:37:43 +0800 | [diff] [blame] | 375 | const struct of_device_id *of_id = |
| 376 | of_match_device(mxc_gpio_dt_ids, &pdev->dev); |
| 377 | enum mxc_gpio_hwtype hwtype; |
| 378 | |
| 379 | if (of_id) |
| 380 | pdev->id_entry = of_id->data; |
| 381 | hwtype = pdev->id_entry->driver_data; |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 382 | |
| 383 | if (mxc_gpio_hwtype) { |
| 384 | /* |
| 385 | * The driver works with a reasonable presupposition, |
| 386 | * that is all gpio ports must be the same type when |
| 387 | * running on one soc. |
| 388 | */ |
| 389 | BUG_ON(mxc_gpio_hwtype != hwtype); |
| 390 | return; |
| 391 | } |
| 392 | |
Benoît Thébaudeau | aeb2774 | 2012-06-22 21:04:06 +0200 | [diff] [blame] | 393 | if (hwtype == IMX35_GPIO) |
| 394 | mxc_gpio_hwdata = &imx35_gpio_hwdata; |
| 395 | else if (hwtype == IMX31_GPIO) |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 396 | mxc_gpio_hwdata = &imx31_gpio_hwdata; |
| 397 | else |
| 398 | mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata; |
| 399 | |
| 400 | mxc_gpio_hwtype = hwtype; |
| 401 | } |
| 402 | |
Shawn Guo | 09ad803 | 2011-08-14 00:14:02 +0800 | [diff] [blame] | 403 | static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
| 404 | { |
Linus Walleij | 0f4630f | 2015-12-04 14:02:58 +0100 | [diff] [blame] | 405 | struct mxc_gpio_port *port = gpiochip_get_data(gc); |
Shawn Guo | 09ad803 | 2011-08-14 00:14:02 +0800 | [diff] [blame] | 406 | |
Shawn Guo | 1ab7ef1 | 2012-06-13 09:04:03 +0800 | [diff] [blame] | 407 | return irq_find_mapping(port->domain, offset); |
Shawn Guo | 09ad803 | 2011-08-14 00:14:02 +0800 | [diff] [blame] | 408 | } |
| 409 | |
Bill Pemberton | 3836309 | 2012-11-19 13:22:34 -0500 | [diff] [blame] | 410 | static int mxc_gpio_probe(struct platform_device *pdev) |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 411 | { |
Shawn Guo | 8937cb6 | 2011-07-07 00:37:43 +0800 | [diff] [blame] | 412 | struct device_node *np = pdev->dev.of_node; |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 413 | struct mxc_gpio_port *port; |
Anson Huang | c8f3d14 | 2019-09-19 17:39:17 +0800 | [diff] [blame] | 414 | int irq_count; |
Shawn Guo | 1ab7ef1 | 2012-06-13 09:04:03 +0800 | [diff] [blame] | 415 | int irq_base; |
Shawn Guo | e4ea933 | 2011-06-07 16:25:37 +0800 | [diff] [blame] | 416 | int err; |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 417 | |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 418 | mxc_gpio_get_hw(pdev); |
| 419 | |
Fabio Estevam | 8cd73e4 | 2013-07-08 17:14:39 -0300 | [diff] [blame] | 420 | port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 421 | if (!port) |
| 422 | return -ENOMEM; |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 423 | |
Bartosz Golaszewski | db5270a | 2017-08-09 14:25:06 +0200 | [diff] [blame] | 424 | port->dev = &pdev->dev; |
| 425 | |
Enrico Weigelt, metux IT consult | 123ac0e | 2019-03-11 19:55:01 +0100 | [diff] [blame] | 426 | port->base = devm_platform_ioremap_resource(pdev, 0); |
Fabio Estevam | 8cd73e4 | 2013-07-08 17:14:39 -0300 | [diff] [blame] | 427 | if (IS_ERR(port->base)) |
| 428 | return PTR_ERR(port->base); |
Baruch Siach | 14cb0de | 2010-07-06 14:03:22 +0300 | [diff] [blame] | 429 | |
Anson Huang | c8f3d14 | 2019-09-19 17:39:17 +0800 | [diff] [blame] | 430 | irq_count = platform_irq_count(pdev); |
| 431 | if (irq_count < 0) |
| 432 | return irq_count; |
| 433 | |
| 434 | if (irq_count > 1) { |
| 435 | port->irq_high = platform_get_irq(pdev, 1); |
| 436 | if (port->irq_high < 0) |
| 437 | port->irq_high = 0; |
| 438 | } |
Philipp Rosenberger | cc9269f | 2017-07-12 10:36:39 +0200 | [diff] [blame] | 439 | |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 440 | port->irq = platform_get_irq(pdev, 0); |
Fabio Estevam | 8cd73e4 | 2013-07-08 17:14:39 -0300 | [diff] [blame] | 441 | if (port->irq < 0) |
Sachin Kamat | 5ea80e4 | 2013-12-21 13:05:57 +0530 | [diff] [blame] | 442 | return port->irq; |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 443 | |
Anson Huang | 2808801 | 2018-05-22 11:05:40 +0800 | [diff] [blame] | 444 | /* the controller clock is optional */ |
Anson Huang | 7beb620 | 2019-08-01 16:44:39 +0800 | [diff] [blame] | 445 | port->clk = devm_clk_get_optional(&pdev->dev, NULL); |
| 446 | if (IS_ERR(port->clk)) |
| 447 | return PTR_ERR(port->clk); |
Anson Huang | 2808801 | 2018-05-22 11:05:40 +0800 | [diff] [blame] | 448 | |
| 449 | err = clk_prepare_enable(port->clk); |
| 450 | if (err) { |
| 451 | dev_err(&pdev->dev, "Unable to enable clock.\n"); |
| 452 | return err; |
| 453 | } |
| 454 | |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 455 | if (of_device_is_compatible(np, "fsl,imx7d-gpio")) |
| 456 | port->power_off = true; |
| 457 | |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 458 | /* disable the interrupt and clear the status */ |
| 459 | writel(0, port->base + GPIO_IMR); |
| 460 | writel(~0, port->base + GPIO_ISR); |
| 461 | |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 462 | if (mxc_gpio_hwtype == IMX21_GPIO) { |
Uwe Kleine-König | 33a4e98 | 2012-06-06 11:49:23 +0200 | [diff] [blame] | 463 | /* |
| 464 | * Setup one handler for all GPIO interrupts. Actually setting |
| 465 | * the handler is needed only once, but doing it for every port |
| 466 | * is more robust and easier. |
| 467 | */ |
| 468 | irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 469 | } else { |
| 470 | /* setup one handler for each entry */ |
Russell King | e65eea5 | 2015-06-16 23:06:40 +0100 | [diff] [blame] | 471 | irq_set_chained_handler_and_data(port->irq, |
| 472 | mx3_gpio_irq_handler, port); |
| 473 | if (port->irq_high > 0) |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 474 | /* setup handler for GPIO 16 to 31 */ |
Russell King | e65eea5 | 2015-06-16 23:06:40 +0100 | [diff] [blame] | 475 | irq_set_chained_handler_and_data(port->irq_high, |
| 476 | mx3_gpio_irq_handler, |
| 477 | port); |
Sascha Hauer | 8afaada | 2009-06-15 12:36:25 +0200 | [diff] [blame] | 478 | } |
| 479 | |
Linus Walleij | 0f4630f | 2015-12-04 14:02:58 +0100 | [diff] [blame] | 480 | err = bgpio_init(&port->gc, &pdev->dev, 4, |
Shawn Guo | 2ce420d | 2011-06-06 13:22:41 +0800 | [diff] [blame] | 481 | port->base + GPIO_PSR, |
| 482 | port->base + GPIO_DR, NULL, |
Vladimir Zapolskiy | 442b249 | 2015-04-29 18:35:01 +0300 | [diff] [blame] | 483 | port->base + GPIO_GDIR, NULL, |
| 484 | BGPIOF_READ_OUTPUT_REG_SET); |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 485 | if (err) |
Fabio Estevam | 8cd73e4 | 2013-07-08 17:14:39 -0300 | [diff] [blame] | 486 | goto out_bgio; |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 487 | |
Vladimir Zapolskiy | 4c806c9 | 2016-09-08 04:48:16 +0300 | [diff] [blame] | 488 | if (of_property_read_bool(np, "gpio-ranges")) { |
| 489 | port->gc.request = gpiochip_generic_request; |
| 490 | port->gc.free = gpiochip_generic_free; |
| 491 | } |
| 492 | |
Linus Walleij | 0f4630f | 2015-12-04 14:02:58 +0100 | [diff] [blame] | 493 | port->gc.to_irq = mxc_gpio_to_irq; |
| 494 | port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : |
Shawn Guo | 7e6086d | 2012-08-05 14:01:26 +0800 | [diff] [blame] | 495 | pdev->id * 32; |
Shawn Guo | 2ce420d | 2011-06-06 13:22:41 +0800 | [diff] [blame] | 496 | |
Laxman Dewangan | ffc5663 | 2016-02-22 17:43:28 +0530 | [diff] [blame] | 497 | err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); |
Shawn Guo | 2ce420d | 2011-06-06 13:22:41 +0800 | [diff] [blame] | 498 | if (err) |
Linus Walleij | 0f4630f | 2015-12-04 14:02:58 +0100 | [diff] [blame] | 499 | goto out_bgio; |
Shawn Guo | 2ce420d | 2011-06-06 13:22:41 +0800 | [diff] [blame] | 500 | |
Bartosz Golaszewski | c553c3c | 2017-03-04 17:23:38 +0100 | [diff] [blame] | 501 | irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); |
Shawn Guo | 1ab7ef1 | 2012-06-13 09:04:03 +0800 | [diff] [blame] | 502 | if (irq_base < 0) { |
| 503 | err = irq_base; |
Laxman Dewangan | ffc5663 | 2016-02-22 17:43:28 +0530 | [diff] [blame] | 504 | goto out_bgio; |
Shawn Guo | 1ab7ef1 | 2012-06-13 09:04:03 +0800 | [diff] [blame] | 505 | } |
| 506 | |
| 507 | port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, |
| 508 | &irq_domain_simple_ops, NULL); |
| 509 | if (!port->domain) { |
| 510 | err = -ENODEV; |
Bartosz Golaszewski | c553c3c | 2017-03-04 17:23:38 +0100 | [diff] [blame] | 511 | goto out_bgio; |
Shawn Guo | 1ab7ef1 | 2012-06-13 09:04:03 +0800 | [diff] [blame] | 512 | } |
Shawn Guo | 8937cb6 | 2011-07-07 00:37:43 +0800 | [diff] [blame] | 513 | |
| 514 | /* gpio-mxc can be a generic irq chip */ |
Peng Fan | 9e26b0b | 2015-08-23 21:11:52 +0800 | [diff] [blame] | 515 | err = mxc_gpio_init_gc(port, irq_base); |
| 516 | if (err < 0) |
| 517 | goto out_irqdomain_remove; |
Shawn Guo | 8937cb6 | 2011-07-07 00:37:43 +0800 | [diff] [blame] | 518 | |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 519 | list_add_tail(&port->node, &mxc_gpio_ports); |
| 520 | |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 521 | platform_set_drvdata(pdev, port); |
| 522 | |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 523 | return 0; |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 524 | |
Peng Fan | 9e26b0b | 2015-08-23 21:11:52 +0800 | [diff] [blame] | 525 | out_irqdomain_remove: |
| 526 | irq_domain_remove(port->domain); |
Fabio Estevam | 8cd73e4 | 2013-07-08 17:14:39 -0300 | [diff] [blame] | 527 | out_bgio: |
Anson Huang | 2808801 | 2018-05-22 11:05:40 +0800 | [diff] [blame] | 528 | clk_disable_unprepare(port->clk); |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 529 | dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); |
| 530 | return err; |
Juergen Beisert | 07bd1a6 | 2008-07-05 10:02:49 +0200 | [diff] [blame] | 531 | } |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 532 | |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 533 | static void mxc_gpio_save_regs(struct mxc_gpio_port *port) |
| 534 | { |
| 535 | if (!port->power_off) |
| 536 | return; |
| 537 | |
| 538 | port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1); |
| 539 | port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2); |
| 540 | port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR); |
| 541 | port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR); |
| 542 | port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL); |
| 543 | port->gpio_saved_reg.dr = readl(port->base + GPIO_DR); |
| 544 | } |
| 545 | |
| 546 | static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) |
| 547 | { |
| 548 | if (!port->power_off) |
| 549 | return; |
| 550 | |
| 551 | writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1); |
| 552 | writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2); |
| 553 | writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR); |
| 554 | writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR); |
| 555 | writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL); |
| 556 | writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); |
| 557 | } |
| 558 | |
Anson Huang | 1a5287a | 2018-11-09 04:56:56 +0000 | [diff] [blame] | 559 | static int mxc_gpio_syscore_suspend(void) |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 560 | { |
Anson Huang | 1a5287a | 2018-11-09 04:56:56 +0000 | [diff] [blame] | 561 | struct mxc_gpio_port *port; |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 562 | |
Anson Huang | 1a5287a | 2018-11-09 04:56:56 +0000 | [diff] [blame] | 563 | /* walk through all ports */ |
| 564 | list_for_each_entry(port, &mxc_gpio_ports, node) { |
| 565 | mxc_gpio_save_regs(port); |
| 566 | clk_disable_unprepare(port->clk); |
| 567 | } |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 568 | |
| 569 | return 0; |
| 570 | } |
| 571 | |
Anson Huang | 1a5287a | 2018-11-09 04:56:56 +0000 | [diff] [blame] | 572 | static void mxc_gpio_syscore_resume(void) |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 573 | { |
Anson Huang | 1a5287a | 2018-11-09 04:56:56 +0000 | [diff] [blame] | 574 | struct mxc_gpio_port *port; |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 575 | int ret; |
| 576 | |
Anson Huang | 1a5287a | 2018-11-09 04:56:56 +0000 | [diff] [blame] | 577 | /* walk through all ports */ |
| 578 | list_for_each_entry(port, &mxc_gpio_ports, node) { |
| 579 | ret = clk_prepare_enable(port->clk); |
| 580 | if (ret) { |
| 581 | pr_err("mxc: failed to enable gpio clock %d\n", ret); |
| 582 | return; |
| 583 | } |
| 584 | mxc_gpio_restore_regs(port); |
| 585 | } |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 586 | } |
| 587 | |
Anson Huang | 1a5287a | 2018-11-09 04:56:56 +0000 | [diff] [blame] | 588 | static struct syscore_ops mxc_gpio_syscore_ops = { |
| 589 | .suspend = mxc_gpio_syscore_suspend, |
| 590 | .resume = mxc_gpio_syscore_resume, |
Anson Huang | c19fdae | 2018-07-18 09:25:32 +0800 | [diff] [blame] | 591 | }; |
| 592 | |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 593 | static struct platform_driver mxc_gpio_driver = { |
| 594 | .driver = { |
| 595 | .name = "gpio-mxc", |
Shawn Guo | 8937cb6 | 2011-07-07 00:37:43 +0800 | [diff] [blame] | 596 | .of_match_table = mxc_gpio_dt_ids, |
Bartosz Golaszewski | 90e1fc4 | 2017-08-09 14:25:00 +0200 | [diff] [blame] | 597 | .suppress_bind_attrs = true, |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 598 | }, |
| 599 | .probe = mxc_gpio_probe, |
Shawn Guo | e7fc6ae | 2011-07-07 00:37:41 +0800 | [diff] [blame] | 600 | .id_table = mxc_gpio_devtype, |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 601 | }; |
| 602 | |
| 603 | static int __init gpio_mxc_init(void) |
| 604 | { |
Anson Huang | 1a5287a | 2018-11-09 04:56:56 +0000 | [diff] [blame] | 605 | register_syscore_ops(&mxc_gpio_syscore_ops); |
| 606 | |
Shawn Guo | b78d8e5 | 2011-06-06 00:07:55 +0800 | [diff] [blame] | 607 | return platform_driver_register(&mxc_gpio_driver); |
| 608 | } |
Vladimir Zapolskiy | e188cbf | 2016-09-08 04:48:15 +0300 | [diff] [blame] | 609 | subsys_initcall(gpio_mxc_init); |