blob: c77d474185f315e1afb352c12d5aa23761d538d4 [file] [log] [blame]
Fabio Estevam014e4202018-05-21 23:32:54 -03001// SPDX-License-Identifier: GPL-2.0+
2//
3// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5//
6// Based on code from Freescale Semiconductor,
7// Authors: Daniel Mack, Juergen Beisert.
8// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
Juergen Beisert07bd1a62008-07-05 10:02:49 +02009
Anson Huang28088012018-05-22 11:05:40 +080010#include <linux/clk.h>
Fabio Estevam18f92b12013-07-22 18:17:52 -030011#include <linux/err.h>
Juergen Beisert07bd1a62008-07-05 10:02:49 +020012#include <linux/init.h>
Dinh Nguyena3484ff2010-10-23 09:12:48 -050013#include <linux/interrupt.h>
Juergen Beisert07bd1a62008-07-05 10:02:49 +020014#include <linux/io.h>
15#include <linux/irq.h>
Shawn Guo1ab7ef12012-06-13 09:04:03 +080016#include <linux/irqdomain.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000017#include <linux/irqchip/chained_irq.h>
Shawn Guob78d8e52011-06-06 00:07:55 +080018#include <linux/platform_device.h>
19#include <linux/slab.h>
Anson Huang1a5287a2018-11-09 04:56:56 +000020#include <linux/syscore_ops.h>
Linus Walleij0f4630f2015-12-04 14:02:58 +010021#include <linux/gpio/driver.h>
Shawn Guo8937cb62011-07-07 00:37:43 +080022#include <linux/of.h>
23#include <linux/of_device.h>
Christoph Hellwig16c3bd32015-08-28 09:27:22 +020024#include <linux/bug.h>
Juergen Beisert07bd1a62008-07-05 10:02:49 +020025
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080026enum mxc_gpio_hwtype {
27 IMX1_GPIO, /* runs on i.mx1 */
28 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +020029 IMX31_GPIO, /* runs on i.mx31 */
30 IMX35_GPIO, /* runs on all other i.mx */
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080031};
32
33/* device type dependent stuff */
34struct mxc_gpio_hwdata {
35 unsigned dr_reg;
36 unsigned gdir_reg;
37 unsigned psr_reg;
38 unsigned icr1_reg;
39 unsigned icr2_reg;
40 unsigned imr_reg;
41 unsigned isr_reg;
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +020042 int edge_sel_reg;
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080043 unsigned low_level;
44 unsigned high_level;
45 unsigned rise_edge;
46 unsigned fall_edge;
47};
48
Anson Huangc19fdae2018-07-18 09:25:32 +080049struct mxc_gpio_reg_saved {
50 u32 icr1;
51 u32 icr2;
52 u32 imr;
53 u32 gdir;
54 u32 edge_sel;
55 u32 dr;
56};
57
Shawn Guob78d8e52011-06-06 00:07:55 +080058struct mxc_gpio_port {
59 struct list_head node;
60 void __iomem *base;
Anson Huang28088012018-05-22 11:05:40 +080061 struct clk *clk;
Shawn Guob78d8e52011-06-06 00:07:55 +080062 int irq;
63 int irq_high;
Shawn Guo1ab7ef12012-06-13 09:04:03 +080064 struct irq_domain *domain;
Linus Walleij0f4630f2015-12-04 14:02:58 +010065 struct gpio_chip gc;
Bartosz Golaszewskidb5270a2017-08-09 14:25:06 +020066 struct device *dev;
Shawn Guob78d8e52011-06-06 00:07:55 +080067 u32 both_edges;
Anson Huangc19fdae2018-07-18 09:25:32 +080068 struct mxc_gpio_reg_saved gpio_saved_reg;
69 bool power_off;
Shawn Guob78d8e52011-06-06 00:07:55 +080070};
71
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080072static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
73 .dr_reg = 0x1c,
74 .gdir_reg = 0x00,
75 .psr_reg = 0x24,
76 .icr1_reg = 0x28,
77 .icr2_reg = 0x2c,
78 .imr_reg = 0x30,
79 .isr_reg = 0x34,
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +020080 .edge_sel_reg = -EINVAL,
Shawn Guoe7fc6ae2011-07-07 00:37:41 +080081 .low_level = 0x03,
82 .high_level = 0x02,
83 .rise_edge = 0x00,
84 .fall_edge = 0x01,
85};
86
87static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
88 .dr_reg = 0x00,
89 .gdir_reg = 0x04,
90 .psr_reg = 0x08,
91 .icr1_reg = 0x0c,
92 .icr2_reg = 0x10,
93 .imr_reg = 0x14,
94 .isr_reg = 0x18,
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +020095 .edge_sel_reg = -EINVAL,
96 .low_level = 0x00,
97 .high_level = 0x01,
98 .rise_edge = 0x02,
99 .fall_edge = 0x03,
100};
101
102static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
103 .dr_reg = 0x00,
104 .gdir_reg = 0x04,
105 .psr_reg = 0x08,
106 .icr1_reg = 0x0c,
107 .icr2_reg = 0x10,
108 .imr_reg = 0x14,
109 .isr_reg = 0x18,
110 .edge_sel_reg = 0x1c,
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800111 .low_level = 0x00,
112 .high_level = 0x01,
113 .rise_edge = 0x02,
114 .fall_edge = 0x03,
115};
116
117static enum mxc_gpio_hwtype mxc_gpio_hwtype;
118static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
119
120#define GPIO_DR (mxc_gpio_hwdata->dr_reg)
121#define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
122#define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
123#define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
124#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
125#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
126#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200127#define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg)
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800128
129#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
130#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
131#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
132#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200133#define GPIO_INT_BOTH_EDGES 0x4
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800134
Krzysztof Kozlowskif4f79d42015-05-02 00:56:47 +0900135static const struct platform_device_id mxc_gpio_devtype[] = {
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800136 {
137 .name = "imx1-gpio",
138 .driver_data = IMX1_GPIO,
139 }, {
140 .name = "imx21-gpio",
141 .driver_data = IMX21_GPIO,
142 }, {
143 .name = "imx31-gpio",
144 .driver_data = IMX31_GPIO,
145 }, {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200146 .name = "imx35-gpio",
147 .driver_data = IMX35_GPIO,
148 }, {
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800149 /* sentinel */
150 }
151};
152
Shawn Guo8937cb62011-07-07 00:37:43 +0800153static const struct of_device_id mxc_gpio_dt_ids[] = {
154 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
155 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
156 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200157 { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
Anson Huangc19fdae2018-07-18 09:25:32 +0800158 { .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
Shawn Guo8937cb62011-07-07 00:37:43 +0800159 { /* sentinel */ }
160};
161
Shawn Guob78d8e52011-06-06 00:07:55 +0800162/*
163 * MX2 has one interrupt *for all* gpio ports. The list is used
164 * to save the references to all ports, so that mx2_gpio_irq_handler
165 * can walk through all interrupt status registers.
166 */
167static LIST_HEAD(mxc_gpio_ports);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200168
169/* Note: This driver assumes 32 GPIOs are handled in one register */
170
Lennert Buytenhek4d935792010-11-29 11:16:23 +0100171static int gpio_set_irq_type(struct irq_data *d, u32 type)
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200172{
Shawn Guoe4ea9332011-06-07 16:25:37 +0800173 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
174 struct mxc_gpio_port *port = gc->private;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200175 u32 bit, val;
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800176 u32 gpio_idx = d->hwirq;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200177 int edge;
178 void __iomem *reg = port->base;
179
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800180 port->both_edges &= ~(1 << gpio_idx);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200181 switch (type) {
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100182 case IRQ_TYPE_EDGE_RISING:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200183 edge = GPIO_INT_RISE_EDGE;
184 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100185 case IRQ_TYPE_EDGE_FALLING:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200186 edge = GPIO_INT_FALL_EDGE;
187 break;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100188 case IRQ_TYPE_EDGE_BOTH:
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200189 if (GPIO_EDGE_SEL >= 0) {
190 edge = GPIO_INT_BOTH_EDGES;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100191 } else {
Linus Walleij8d0bd9a2018-04-15 22:25:00 +0200192 val = port->gc.get(&port->gc, gpio_idx);
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200193 if (val) {
194 edge = GPIO_INT_LOW_LEV;
Linus Walleij8d0bd9a2018-04-15 22:25:00 +0200195 pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200196 } else {
197 edge = GPIO_INT_HIGH_LEV;
Linus Walleij8d0bd9a2018-04-15 22:25:00 +0200198 pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200199 }
Linus Torvaldsf948ad02012-07-26 13:56:38 -0700200 port->both_edges |= 1 << gpio_idx;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100201 }
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100202 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100203 case IRQ_TYPE_LEVEL_LOW:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200204 edge = GPIO_INT_LOW_LEV;
205 break;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100206 case IRQ_TYPE_LEVEL_HIGH:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200207 edge = GPIO_INT_HIGH_LEV;
208 break;
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100209 default:
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200210 return -EINVAL;
211 }
212
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200213 if (GPIO_EDGE_SEL >= 0) {
214 val = readl(port->base + GPIO_EDGE_SEL);
215 if (edge == GPIO_INT_BOTH_EDGES)
Linus Torvaldsf948ad02012-07-26 13:56:38 -0700216 writel(val | (1 << gpio_idx),
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200217 port->base + GPIO_EDGE_SEL);
218 else
Linus Torvaldsf948ad02012-07-26 13:56:38 -0700219 writel(val & ~(1 << gpio_idx),
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200220 port->base + GPIO_EDGE_SEL);
221 }
222
223 if (edge != GPIO_INT_BOTH_EDGES) {
Linus Torvaldsf948ad02012-07-26 13:56:38 -0700224 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
225 bit = gpio_idx & 0xf;
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200226 val = readl(reg) & ~(0x3 << (bit << 1));
227 writel(val | (edge << (bit << 1)), reg);
228 }
229
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800230 writel(1 << gpio_idx, port->base + GPIO_ISR);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200231
232 return 0;
233}
234
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100235static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
236{
237 void __iomem *reg = port->base;
238 u32 bit, val;
239 int edge;
240
241 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
242 bit = gpio & 0xf;
Shawn Guob78d8e52011-06-06 00:07:55 +0800243 val = readl(reg);
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100244 edge = (val >> (bit << 1)) & 3;
245 val &= ~(0x3 << (bit << 1));
Uwe Kleine-König3d40f7f2010-02-05 22:14:37 +0100246 if (edge == GPIO_INT_HIGH_LEV) {
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100247 edge = GPIO_INT_LOW_LEV;
248 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
Uwe Kleine-König3d40f7f2010-02-05 22:14:37 +0100249 } else if (edge == GPIO_INT_LOW_LEV) {
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100250 edge = GPIO_INT_HIGH_LEV;
251 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
Uwe Kleine-König3d40f7f2010-02-05 22:14:37 +0100252 } else {
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100253 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
254 gpio, edge);
255 return;
256 }
Shawn Guob78d8e52011-06-06 00:07:55 +0800257 writel(val | (edge << (bit << 1)), reg);
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100258}
259
Uwe Kleine-König3621f182010-02-08 21:02:30 +0100260/* handle 32 interrupts in one status register */
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200261static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
262{
Uwe Kleine-König3621f182010-02-08 21:02:30 +0100263 while (irq_stat != 0) {
264 int irqoffset = fls(irq_stat) - 1;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200265
Uwe Kleine-König3621f182010-02-08 21:02:30 +0100266 if (port->both_edges & (1 << irqoffset))
267 mxc_flip_edge(port, irqoffset);
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100268
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800269 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
Guennadi Liakhovetski910862e2009-03-12 12:46:41 +0100270
Uwe Kleine-König3621f182010-02-08 21:02:30 +0100271 irq_stat &= ~(1 << irqoffset);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200272 }
273}
274
Paulius Zaleckascfca8b52008-11-14 11:01:38 +0100275/* MX1 and MX3 has one interrupt *per* gpio port */
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200276static void mx3_gpio_irq_handler(struct irq_desc *desc)
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200277{
278 u32 irq_stat;
Jiang Liu476f8b42015-06-04 12:13:15 +0800279 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
280 struct irq_chip *chip = irq_desc_get_chip(desc);
Shawn Guo0e44b6e2011-09-21 21:24:04 +0800281
282 chained_irq_enter(chip, desc);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200283
Shawn Guob78d8e52011-06-06 00:07:55 +0800284 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
Sascha Hauere2c97e72009-04-21 12:39:59 +0200285
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200286 mxc_gpio_irq_handler(port, irq_stat);
Shawn Guo0e44b6e2011-09-21 21:24:04 +0800287
288 chained_irq_exit(chip, desc);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200289}
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200290
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200291/* MX2 has one interrupt *for all* gpio ports */
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200292static void mx2_gpio_irq_handler(struct irq_desc *desc)
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200293{
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200294 u32 irq_msk, irq_stat;
Shawn Guob78d8e52011-06-06 00:07:55 +0800295 struct mxc_gpio_port *port;
Jiang Liu476f8b42015-06-04 12:13:15 +0800296 struct irq_chip *chip = irq_desc_get_chip(desc);
Uwe Kleine-Königc0e811d2013-07-18 14:58:06 +0200297
298 chained_irq_enter(chip, desc);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200299
300 /* walk through all interrupt status registers */
Shawn Guob78d8e52011-06-06 00:07:55 +0800301 list_for_each_entry(port, &mxc_gpio_ports, node) {
302 irq_msk = readl(port->base + GPIO_IMR);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200303 if (!irq_msk)
304 continue;
305
Shawn Guob78d8e52011-06-06 00:07:55 +0800306 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200307 if (irq_stat)
Shawn Guob78d8e52011-06-06 00:07:55 +0800308 mxc_gpio_irq_handler(port, irq_stat);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200309 }
Uwe Kleine-Königc0e811d2013-07-18 14:58:06 +0200310 chained_irq_exit(chip, desc);
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200311}
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200312
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500313/*
314 * Set interrupt number "irq" in the GPIO as a wake-up source.
315 * While system is running, all registered GPIO interrupts need to have
316 * wake-up enabled. When system is suspended, only selected GPIO interrupts
317 * need to have wake-up enabled.
318 * @param irq interrupt source number
319 * @param enable enable as wake-up if equal to non-zero
320 * @return This function returns 0 on success.
321 */
Lennert Buytenhek4d935792010-11-29 11:16:23 +0100322static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500323{
Shawn Guoe4ea9332011-06-07 16:25:37 +0800324 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
325 struct mxc_gpio_port *port = gc->private;
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800326 u32 gpio_idx = d->hwirq;
Philipp Rosenberger77a4d752017-07-12 10:36:40 +0200327 int ret;
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500328
329 if (enable) {
330 if (port->irq_high && (gpio_idx >= 16))
Philipp Rosenberger77a4d752017-07-12 10:36:40 +0200331 ret = enable_irq_wake(port->irq_high);
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500332 else
Philipp Rosenberger77a4d752017-07-12 10:36:40 +0200333 ret = enable_irq_wake(port->irq);
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500334 } else {
335 if (port->irq_high && (gpio_idx >= 16))
Philipp Rosenberger77a4d752017-07-12 10:36:40 +0200336 ret = disable_irq_wake(port->irq_high);
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500337 else
Philipp Rosenberger77a4d752017-07-12 10:36:40 +0200338 ret = disable_irq_wake(port->irq);
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500339 }
340
Philipp Rosenberger77a4d752017-07-12 10:36:40 +0200341 return ret;
Dinh Nguyena3484ff2010-10-23 09:12:48 -0500342}
343
Peng Fan9e26b0b2015-08-23 21:11:52 +0800344static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
Shawn Guoe4ea9332011-06-07 16:25:37 +0800345{
346 struct irq_chip_generic *gc;
347 struct irq_chip_type *ct;
Bartosz Golaszewskidb5270a2017-08-09 14:25:06 +0200348 int rv;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200349
Bartosz Golaszewskidb5270a2017-08-09 14:25:06 +0200350 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
351 port->base, handle_level_irq);
Peng Fan9e26b0b2015-08-23 21:11:52 +0800352 if (!gc)
353 return -ENOMEM;
Shawn Guoe4ea9332011-06-07 16:25:37 +0800354 gc->private = port;
355
356 ct = gc->chip_types;
Shawn Guo591567a2011-07-19 21:16:56 +0800357 ct->chip.irq_ack = irq_gc_ack_set_bit;
Shawn Guoe4ea9332011-06-07 16:25:37 +0800358 ct->chip.irq_mask = irq_gc_mask_clr_bit;
359 ct->chip.irq_unmask = irq_gc_mask_set_bit;
360 ct->chip.irq_set_type = gpio_set_irq_type;
Shawn Guo591567a2011-07-19 21:16:56 +0800361 ct->chip.irq_set_wake = gpio_set_wake_irq;
Ulises Brindis952cfbd2015-08-05 10:23:07 -0700362 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
Shawn Guoe4ea9332011-06-07 16:25:37 +0800363 ct->regs.ack = GPIO_ISR;
364 ct->regs.mask = GPIO_IMR;
365
Bartosz Golaszewskidb5270a2017-08-09 14:25:06 +0200366 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
367 IRQ_GC_INIT_NESTED_LOCK,
368 IRQ_NOREQUEST, 0);
Peng Fan9e26b0b2015-08-23 21:11:52 +0800369
Bartosz Golaszewskidb5270a2017-08-09 14:25:06 +0200370 return rv;
Shawn Guoe4ea9332011-06-07 16:25:37 +0800371}
Thomas Gleixnerb5eee2f2011-04-04 14:29:58 +0200372
Bill Pemberton38363092012-11-19 13:22:34 -0500373static void mxc_gpio_get_hw(struct platform_device *pdev)
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800374{
Shawn Guo8937cb62011-07-07 00:37:43 +0800375 const struct of_device_id *of_id =
376 of_match_device(mxc_gpio_dt_ids, &pdev->dev);
377 enum mxc_gpio_hwtype hwtype;
378
379 if (of_id)
380 pdev->id_entry = of_id->data;
381 hwtype = pdev->id_entry->driver_data;
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800382
383 if (mxc_gpio_hwtype) {
384 /*
385 * The driver works with a reasonable presupposition,
386 * that is all gpio ports must be the same type when
387 * running on one soc.
388 */
389 BUG_ON(mxc_gpio_hwtype != hwtype);
390 return;
391 }
392
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200393 if (hwtype == IMX35_GPIO)
394 mxc_gpio_hwdata = &imx35_gpio_hwdata;
395 else if (hwtype == IMX31_GPIO)
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800396 mxc_gpio_hwdata = &imx31_gpio_hwdata;
397 else
398 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
399
400 mxc_gpio_hwtype = hwtype;
401}
402
Shawn Guo09ad8032011-08-14 00:14:02 +0800403static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
404{
Linus Walleij0f4630f2015-12-04 14:02:58 +0100405 struct mxc_gpio_port *port = gpiochip_get_data(gc);
Shawn Guo09ad8032011-08-14 00:14:02 +0800406
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800407 return irq_find_mapping(port->domain, offset);
Shawn Guo09ad8032011-08-14 00:14:02 +0800408}
409
Bill Pemberton38363092012-11-19 13:22:34 -0500410static int mxc_gpio_probe(struct platform_device *pdev)
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200411{
Shawn Guo8937cb62011-07-07 00:37:43 +0800412 struct device_node *np = pdev->dev.of_node;
Shawn Guob78d8e52011-06-06 00:07:55 +0800413 struct mxc_gpio_port *port;
Anson Huangc8f3d142019-09-19 17:39:17 +0800414 int irq_count;
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800415 int irq_base;
Shawn Guoe4ea9332011-06-07 16:25:37 +0800416 int err;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200417
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800418 mxc_gpio_get_hw(pdev);
419
Fabio Estevam8cd73e42013-07-08 17:14:39 -0300420 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
Shawn Guob78d8e52011-06-06 00:07:55 +0800421 if (!port)
422 return -ENOMEM;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200423
Bartosz Golaszewskidb5270a2017-08-09 14:25:06 +0200424 port->dev = &pdev->dev;
425
Enrico Weigelt, metux IT consult123ac0e2019-03-11 19:55:01 +0100426 port->base = devm_platform_ioremap_resource(pdev, 0);
Fabio Estevam8cd73e42013-07-08 17:14:39 -0300427 if (IS_ERR(port->base))
428 return PTR_ERR(port->base);
Baruch Siach14cb0de2010-07-06 14:03:22 +0300429
Anson Huangc8f3d142019-09-19 17:39:17 +0800430 irq_count = platform_irq_count(pdev);
431 if (irq_count < 0)
432 return irq_count;
433
434 if (irq_count > 1) {
435 port->irq_high = platform_get_irq(pdev, 1);
436 if (port->irq_high < 0)
437 port->irq_high = 0;
438 }
Philipp Rosenbergercc9269f2017-07-12 10:36:39 +0200439
Shawn Guob78d8e52011-06-06 00:07:55 +0800440 port->irq = platform_get_irq(pdev, 0);
Fabio Estevam8cd73e42013-07-08 17:14:39 -0300441 if (port->irq < 0)
Sachin Kamat5ea80e42013-12-21 13:05:57 +0530442 return port->irq;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200443
Anson Huang28088012018-05-22 11:05:40 +0800444 /* the controller clock is optional */
Anson Huang7beb6202019-08-01 16:44:39 +0800445 port->clk = devm_clk_get_optional(&pdev->dev, NULL);
446 if (IS_ERR(port->clk))
447 return PTR_ERR(port->clk);
Anson Huang28088012018-05-22 11:05:40 +0800448
449 err = clk_prepare_enable(port->clk);
450 if (err) {
451 dev_err(&pdev->dev, "Unable to enable clock.\n");
452 return err;
453 }
454
Anson Huangc19fdae2018-07-18 09:25:32 +0800455 if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
456 port->power_off = true;
457
Shawn Guob78d8e52011-06-06 00:07:55 +0800458 /* disable the interrupt and clear the status */
459 writel(0, port->base + GPIO_IMR);
460 writel(~0, port->base + GPIO_ISR);
461
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800462 if (mxc_gpio_hwtype == IMX21_GPIO) {
Uwe Kleine-König33a4e982012-06-06 11:49:23 +0200463 /*
464 * Setup one handler for all GPIO interrupts. Actually setting
465 * the handler is needed only once, but doing it for every port
466 * is more robust and easier.
467 */
468 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
Shawn Guob78d8e52011-06-06 00:07:55 +0800469 } else {
470 /* setup one handler for each entry */
Russell Kinge65eea52015-06-16 23:06:40 +0100471 irq_set_chained_handler_and_data(port->irq,
472 mx3_gpio_irq_handler, port);
473 if (port->irq_high > 0)
Shawn Guob78d8e52011-06-06 00:07:55 +0800474 /* setup handler for GPIO 16 to 31 */
Russell Kinge65eea52015-06-16 23:06:40 +0100475 irq_set_chained_handler_and_data(port->irq_high,
476 mx3_gpio_irq_handler,
477 port);
Sascha Hauer8afaada2009-06-15 12:36:25 +0200478 }
479
Linus Walleij0f4630f2015-12-04 14:02:58 +0100480 err = bgpio_init(&port->gc, &pdev->dev, 4,
Shawn Guo2ce420d2011-06-06 13:22:41 +0800481 port->base + GPIO_PSR,
482 port->base + GPIO_DR, NULL,
Vladimir Zapolskiy442b2492015-04-29 18:35:01 +0300483 port->base + GPIO_GDIR, NULL,
484 BGPIOF_READ_OUTPUT_REG_SET);
Shawn Guob78d8e52011-06-06 00:07:55 +0800485 if (err)
Fabio Estevam8cd73e42013-07-08 17:14:39 -0300486 goto out_bgio;
Shawn Guob78d8e52011-06-06 00:07:55 +0800487
Vladimir Zapolskiy4c806c92016-09-08 04:48:16 +0300488 if (of_property_read_bool(np, "gpio-ranges")) {
489 port->gc.request = gpiochip_generic_request;
490 port->gc.free = gpiochip_generic_free;
491 }
492
Linus Walleij0f4630f2015-12-04 14:02:58 +0100493 port->gc.to_irq = mxc_gpio_to_irq;
494 port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
Shawn Guo7e6086d2012-08-05 14:01:26 +0800495 pdev->id * 32;
Shawn Guo2ce420d2011-06-06 13:22:41 +0800496
Laxman Dewanganffc56632016-02-22 17:43:28 +0530497 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
Shawn Guo2ce420d2011-06-06 13:22:41 +0800498 if (err)
Linus Walleij0f4630f2015-12-04 14:02:58 +0100499 goto out_bgio;
Shawn Guo2ce420d2011-06-06 13:22:41 +0800500
Bartosz Golaszewskic553c3c2017-03-04 17:23:38 +0100501 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800502 if (irq_base < 0) {
503 err = irq_base;
Laxman Dewanganffc56632016-02-22 17:43:28 +0530504 goto out_bgio;
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800505 }
506
507 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
508 &irq_domain_simple_ops, NULL);
509 if (!port->domain) {
510 err = -ENODEV;
Bartosz Golaszewskic553c3c2017-03-04 17:23:38 +0100511 goto out_bgio;
Shawn Guo1ab7ef12012-06-13 09:04:03 +0800512 }
Shawn Guo8937cb62011-07-07 00:37:43 +0800513
514 /* gpio-mxc can be a generic irq chip */
Peng Fan9e26b0b2015-08-23 21:11:52 +0800515 err = mxc_gpio_init_gc(port, irq_base);
516 if (err < 0)
517 goto out_irqdomain_remove;
Shawn Guo8937cb62011-07-07 00:37:43 +0800518
Shawn Guob78d8e52011-06-06 00:07:55 +0800519 list_add_tail(&port->node, &mxc_gpio_ports);
520
Anson Huangc19fdae2018-07-18 09:25:32 +0800521 platform_set_drvdata(pdev, port);
522
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200523 return 0;
Shawn Guob78d8e52011-06-06 00:07:55 +0800524
Peng Fan9e26b0b2015-08-23 21:11:52 +0800525out_irqdomain_remove:
526 irq_domain_remove(port->domain);
Fabio Estevam8cd73e42013-07-08 17:14:39 -0300527out_bgio:
Anson Huang28088012018-05-22 11:05:40 +0800528 clk_disable_unprepare(port->clk);
Shawn Guob78d8e52011-06-06 00:07:55 +0800529 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
530 return err;
Juergen Beisert07bd1a62008-07-05 10:02:49 +0200531}
Shawn Guob78d8e52011-06-06 00:07:55 +0800532
Anson Huangc19fdae2018-07-18 09:25:32 +0800533static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
534{
535 if (!port->power_off)
536 return;
537
538 port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
539 port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
540 port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
541 port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
542 port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
543 port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
544}
545
546static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
547{
548 if (!port->power_off)
549 return;
550
551 writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
552 writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
553 writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
554 writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
555 writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
556 writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
557}
558
Anson Huang1a5287a2018-11-09 04:56:56 +0000559static int mxc_gpio_syscore_suspend(void)
Anson Huangc19fdae2018-07-18 09:25:32 +0800560{
Anson Huang1a5287a2018-11-09 04:56:56 +0000561 struct mxc_gpio_port *port;
Anson Huangc19fdae2018-07-18 09:25:32 +0800562
Anson Huang1a5287a2018-11-09 04:56:56 +0000563 /* walk through all ports */
564 list_for_each_entry(port, &mxc_gpio_ports, node) {
565 mxc_gpio_save_regs(port);
566 clk_disable_unprepare(port->clk);
567 }
Anson Huangc19fdae2018-07-18 09:25:32 +0800568
569 return 0;
570}
571
Anson Huang1a5287a2018-11-09 04:56:56 +0000572static void mxc_gpio_syscore_resume(void)
Anson Huangc19fdae2018-07-18 09:25:32 +0800573{
Anson Huang1a5287a2018-11-09 04:56:56 +0000574 struct mxc_gpio_port *port;
Anson Huangc19fdae2018-07-18 09:25:32 +0800575 int ret;
576
Anson Huang1a5287a2018-11-09 04:56:56 +0000577 /* walk through all ports */
578 list_for_each_entry(port, &mxc_gpio_ports, node) {
579 ret = clk_prepare_enable(port->clk);
580 if (ret) {
581 pr_err("mxc: failed to enable gpio clock %d\n", ret);
582 return;
583 }
584 mxc_gpio_restore_regs(port);
585 }
Anson Huangc19fdae2018-07-18 09:25:32 +0800586}
587
Anson Huang1a5287a2018-11-09 04:56:56 +0000588static struct syscore_ops mxc_gpio_syscore_ops = {
589 .suspend = mxc_gpio_syscore_suspend,
590 .resume = mxc_gpio_syscore_resume,
Anson Huangc19fdae2018-07-18 09:25:32 +0800591};
592
Shawn Guob78d8e52011-06-06 00:07:55 +0800593static struct platform_driver mxc_gpio_driver = {
594 .driver = {
595 .name = "gpio-mxc",
Shawn Guo8937cb62011-07-07 00:37:43 +0800596 .of_match_table = mxc_gpio_dt_ids,
Bartosz Golaszewski90e1fc42017-08-09 14:25:00 +0200597 .suppress_bind_attrs = true,
Shawn Guob78d8e52011-06-06 00:07:55 +0800598 },
599 .probe = mxc_gpio_probe,
Shawn Guoe7fc6ae2011-07-07 00:37:41 +0800600 .id_table = mxc_gpio_devtype,
Shawn Guob78d8e52011-06-06 00:07:55 +0800601};
602
603static int __init gpio_mxc_init(void)
604{
Anson Huang1a5287a2018-11-09 04:56:56 +0000605 register_syscore_ops(&mxc_gpio_syscore_ops);
606
Shawn Guob78d8e52011-06-06 00:07:55 +0800607 return platform_driver_register(&mxc_gpio_driver);
608}
Vladimir Zapolskiye188cbf2016-09-08 04:48:15 +0300609subsys_initcall(gpio_mxc_init);