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Bean Huo67351112020-06-05 22:05:19 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +05302/*
3 * Universal Flash Storage Host controller driver
Vinayak Holikatti3b1d0582013-02-25 21:44:32 +05304 * Copyright (C) 2011-2013 Samsung India Software Operations
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +05305 *
Vinayak Holikatti3b1d0582013-02-25 21:44:32 +05306 * Authors:
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +05309 */
10
11#ifndef _UFSHCI_H
12#define _UFSHCI_H
13
14enum {
15 TASK_REQ_UPIU_SIZE_DWORDS = 8,
16 TASK_RSP_UPIU_SIZE_DWORDS = 8,
Dolev Raviv68078d52013-07-30 00:35:58 +053017 ALIGNED_UPIU_SIZE = 512,
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +053018};
19
20/* UFSHCI Registers */
21enum {
22 REG_CONTROLLER_CAPABILITIES = 0x00,
23 REG_UFS_VERSION = 0x08,
24 REG_CONTROLLER_DEV_ID = 0x10,
25 REG_CONTROLLER_PROD_ID = 0x14,
Tomohiro Kusumif6b25452017-03-28 16:49:27 +030026 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +053027 REG_INTERRUPT_STATUS = 0x20,
28 REG_INTERRUPT_ENABLE = 0x24,
29 REG_CONTROLLER_STATUS = 0x30,
30 REG_CONTROLLER_ENABLE = 0x34,
31 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
32 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
33 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
34 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
35 REG_UIC_ERROR_CODE_DME = 0x48,
36 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
37 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
38 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
39 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
40 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
41 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
42 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
43 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
44 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
45 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
46 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
47 REG_UIC_COMMAND = 0x90,
48 REG_UIC_COMMAND_ARG_1 = 0x94,
49 REG_UIC_COMMAND_ARG_2 = 0x98,
50 REG_UIC_COMMAND_ARG_3 = 0x9C,
Dolev Raviv66cc8202016-12-22 18:39:42 -080051
52 UFSHCI_REG_SPACE_SIZE = 0xA0,
53
Yaniv Gardic01848c2016-12-05 19:25:02 -080054 REG_UFS_CCAP = 0x100,
55 REG_UFS_CRYPTOCAP = 0x104,
56
57 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +053058};
59
60/* Controller capability masks */
61enum {
62 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
63 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
Adrian Hunterad448372018-03-20 15:07:38 +020064 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +053065 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
66 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
67 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
Satya Tangirala5e7341e2020-07-06 20:04:12 +000068 MASK_CRYPTO_SUPPORT = 0x10000000,
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +053069};
70
Santosh Y679882a2016-11-24 12:58:51 +080071#define UFS_MASK(mask, offset) ((mask) << (offset))
72
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +053073/* UFS Version 08h */
74#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
75#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
76
Caleb Connolly51428812021-03-10 15:33:42 +000077/*
78 * Controller UFSHCI version
79 * - 2.x and newer use the following scheme:
80 * major << 8 + minor << 4
81 * - 1.x has been converted to match this in
82 * ufshcd_get_ufs_version()
83 */
84static inline u32 ufshci_version(u32 major, u32 minor)
85{
86 return (major << 8) + (minor << 4);
87}
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +053088
89/*
90 * HCDDID - Host Controller Identification Descriptor
91 * - Device ID and Device Class 10h
92 */
93#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
94#define DEVICE_ID UFS_MASK(0xFF, 24)
95
96/*
97 * HCPMID - Host Controller Identification Descriptor
98 * - Product/Manufacturer ID 14h
99 */
100#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
101#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
102
Adrian Hunterad448372018-03-20 15:07:38 +0200103/* AHIT - Auto-Hibernate Idle Timer */
104#define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
105#define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
106#define UFSHCI_AHIBERN8_SCALE_FACTOR 10
107#define UFSHCI_AHIBERN8_MAX (1023 * 100000)
108
Alim Akhtarcc816412017-10-03 20:51:22 +0530109/*
110 * IS - Interrupt Status - 20h
111 */
112#define UTP_TRANSFER_REQ_COMPL 0x1
113#define UIC_DME_END_PT_RESET 0x2
114#define UIC_ERROR 0x4
115#define UIC_TEST_MODE 0x8
116#define UIC_POWER_MODE 0x10
117#define UIC_HIBERNATE_EXIT 0x20
118#define UIC_HIBERNATE_ENTER 0x40
119#define UIC_LINK_LOST 0x80
120#define UIC_LINK_STARTUP 0x100
121#define UTP_TASK_REQ_COMPL 0x200
122#define UIC_COMMAND_COMPL 0x400
123#define DEVICE_FATAL_ERROR 0x800
124#define CONTROLLER_FATAL_ERROR 0x10000
125#define SYSTEM_BUS_FATAL_ERROR 0x20000
Satya Tangirala5e7341e2020-07-06 20:04:12 +0000126#define CRYPTO_ENGINE_FATAL_ERROR 0x40000
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530127
Stanley Chu82174442019-05-21 14:44:54 +0800128#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
129 UIC_HIBERNATE_EXIT)
130
131#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
Subhash Jadavani57d104c2014-09-25 15:32:30 +0300132 UIC_POWER_MODE)
133
134#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
Seungwon Jeon53b3d9c2013-08-31 21:40:22 +0530135
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530136#define UFSHCD_ERROR_MASK (UIC_ERROR |\
137 DEVICE_FATAL_ERROR |\
138 CONTROLLER_FATAL_ERROR |\
Satya Tangirala5e7341e2020-07-06 20:04:12 +0000139 SYSTEM_BUS_FATAL_ERROR |\
140 CRYPTO_ENGINE_FATAL_ERROR)
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530141
142#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
143 CONTROLLER_FATAL_ERROR |\
Satya Tangirala5e7341e2020-07-06 20:04:12 +0000144 SYSTEM_BUS_FATAL_ERROR |\
Kiwoong Kimc99b9b22022-01-21 14:37:55 +0900145 CRYPTO_ENGINE_FATAL_ERROR |\
146 UIC_LINK_LOST)
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530147
148/* HCS - Host Controller Status 30h */
Alim Akhtarcc816412017-10-03 20:51:22 +0530149#define DEVICE_PRESENT 0x1
150#define UTP_TRANSFER_REQ_LIST_READY 0x2
151#define UTP_TASK_REQ_LIST_READY 0x4
152#define UIC_COMMAND_READY 0x8
kwmad.kim@samsung.comcffe3ff2017-11-28 14:35:29 +0900153#define HOST_ERROR_INDICATOR 0x10
154#define DEVICE_ERROR_INDICATOR 0x20
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530155#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
156
Tomohiro Kusumi6cf16112017-04-26 20:28:58 +0300157#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
158 UTP_TASK_REQ_LIST_READY |\
159 UIC_COMMAND_READY)
160
Seungwon Jeon53b3d9c2013-08-31 21:40:22 +0530161enum {
162 PWR_OK = 0x0,
163 PWR_LOCAL = 0x01,
164 PWR_REMOTE = 0x02,
165 PWR_BUSY = 0x03,
166 PWR_ERROR_CAP = 0x04,
167 PWR_FATAL_ERROR = 0x05,
168};
169
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530170/* HCE - Host Controller Enable 34h */
Alim Akhtarcc816412017-10-03 20:51:22 +0530171#define CONTROLLER_ENABLE 0x1
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530172#define CONTROLLER_DISABLE 0x0
Alim Akhtarcc816412017-10-03 20:51:22 +0530173#define CRYPTO_GENERAL_ENABLE 0x2
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530174
175/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
Alim Akhtarcc816412017-10-03 20:51:22 +0530176#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530177#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
Dolev Ravivfb7b45f2016-11-23 16:32:32 -0800178#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
Can Guo2355b662020-08-24 19:07:06 -0700179#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530180
181/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
Alim Akhtarcc816412017-10-03 20:51:22 +0530182#define UIC_DATA_LINK_LAYER_ERROR 0x80000000
Venkat Gopalakrishnan9333d772019-11-14 22:09:28 -0800183#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
kwmad.kim@samsung.comcffe3ff2017-11-28 14:35:29 +0900184#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
185#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
186#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
187#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530188#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
Yaniv Gardi583fa622016-03-10 17:37:13 +0200189#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
190#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530191
192/* UECN - Host UIC Error Code Network Layer 40h */
Alim Akhtarcc816412017-10-03 20:51:22 +0530193#define UIC_NETWORK_LAYER_ERROR 0x80000000
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530194#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
kwmad.kim@samsung.comcffe3ff2017-11-28 14:35:29 +0900195#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
196#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
197#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530198
199/* UECT - Host UIC Error Code Transport Layer 44h */
Alim Akhtarcc816412017-10-03 20:51:22 +0530200#define UIC_TRANSPORT_LAYER_ERROR 0x80000000
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530201#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
kwmad.kim@samsung.comcffe3ff2017-11-28 14:35:29 +0900202#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
203#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
204#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
205#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
206#define UIC_TRANSPORT_BAD_TC 0x10
207#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
208#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530209
210/* UECDME - Host UIC Error Code DME 48h */
Alim Akhtarcc816412017-10-03 20:51:22 +0530211#define UIC_DME_ERROR 0x80000000
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530212#define UIC_DME_ERROR_CODE_MASK 0x1
213
Alim Akhtarcc816412017-10-03 20:51:22 +0530214/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530215#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
216#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
Alim Akhtarcc816412017-10-03 20:51:22 +0530217#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
218#define INT_AGGR_STATUS_BIT 0x100000
219#define INT_AGGR_PARAM_WRITE 0x1000000
220#define INT_AGGR_ENABLE 0x80000000
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530221
222/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
Alim Akhtarcc816412017-10-03 20:51:22 +0530223#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530224
225/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
Alim Akhtarcc816412017-10-03 20:51:22 +0530226#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530227
228/* UICCMD - UIC Command */
229#define COMMAND_OPCODE_MASK 0xFF
230#define GEN_SELECTOR_INDEX_MASK 0xFFFF
231
232#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
233#define RESET_LEVEL 0xFF
234
235#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
236#define CONFIG_RESULT_CODE_MASK 0xFF
237#define GENERIC_ERROR_CODE_MASK 0xFF
238
Yaniv Gardi7ca38cf2015-05-17 18:54:59 +0300239/* GenSelectorIndex calculation macros for M-PHY attributes */
240#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
Yaniv Gardi37113102016-03-10 17:37:16 +0200241#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
Yaniv Gardi7ca38cf2015-05-17 18:54:59 +0300242
Seungwon Jeon12b4fdb2013-08-31 21:40:21 +0530243#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
244 ((sel) & 0xFFFF))
245#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
246#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
247#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
248
Joao Pinto79fcc032016-05-11 12:21:29 +0100249/* Link Status*/
250enum link_status {
251 UFSHCD_LINK_IS_DOWN = 1,
252 UFSHCD_LINK_IS_UP = 2,
253};
254
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530255/* UIC Commands */
Subhash Jadavani57d104c2014-09-25 15:32:30 +0300256enum uic_cmd_dme {
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530257 UIC_CMD_DME_GET = 0x01,
258 UIC_CMD_DME_SET = 0x02,
259 UIC_CMD_DME_PEER_GET = 0x03,
260 UIC_CMD_DME_PEER_SET = 0x04,
261 UIC_CMD_DME_POWERON = 0x10,
262 UIC_CMD_DME_POWEROFF = 0x11,
263 UIC_CMD_DME_ENABLE = 0x12,
264 UIC_CMD_DME_RESET = 0x14,
265 UIC_CMD_DME_END_PT_RST = 0x15,
266 UIC_CMD_DME_LINK_STARTUP = 0x16,
267 UIC_CMD_DME_HIBER_ENTER = 0x17,
268 UIC_CMD_DME_HIBER_EXIT = 0x18,
269 UIC_CMD_DME_TEST_MODE = 0x1A,
270};
271
272/* UIC Config result code / Generic error code */
273enum {
274 UIC_CMD_RESULT_SUCCESS = 0x00,
275 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
276 UIC_CMD_RESULT_FAILURE = 0x01,
277 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
278 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
279 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
280 UIC_CMD_RESULT_BAD_INDEX = 0x05,
281 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
282 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
283 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
284 UIC_CMD_RESULT_BUSY = 0x09,
285 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
286};
287
288#define MASK_UIC_COMMAND_RESULT 0xFF
289
Seungwon Jeon7d568652013-08-31 21:40:20 +0530290#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
291#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530292
293/* Interrupt disable masks */
294enum {
295 /* Interrupt disable mask for UFSHCI v1.0 */
Seungwon Jeon2fbd0092013-06-26 22:39:27 +0530296 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
297 INTERRUPT_MASK_RW_VER_10 = 0x30000,
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530298
299 /* Interrupt disable mask for UFSHCI v1.1 */
Seungwon Jeon2fbd0092013-06-26 22:39:27 +0530300 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
Yaniv Gardic01848c2016-12-05 19:25:02 -0800301
302 /* Interrupt disable mask for UFSHCI v2.1 */
303 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530304};
305
Satya Tangirala5e7341e2020-07-06 20:04:12 +0000306/* CCAP - Crypto Capability 100h */
307union ufs_crypto_capabilities {
308 __le32 reg_val;
309 struct {
310 u8 num_crypto_cap;
311 u8 config_count;
312 u8 reserved;
313 u8 config_array_ptr;
314 };
315};
316
317enum ufs_crypto_key_size {
318 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
319 UFS_CRYPTO_KEY_SIZE_128 = 0x1,
320 UFS_CRYPTO_KEY_SIZE_192 = 0x2,
321 UFS_CRYPTO_KEY_SIZE_256 = 0x3,
322 UFS_CRYPTO_KEY_SIZE_512 = 0x4,
323};
324
325enum ufs_crypto_alg {
326 UFS_CRYPTO_ALG_AES_XTS = 0x0,
327 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
328 UFS_CRYPTO_ALG_AES_ECB = 0x2,
329 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
330};
331
332/* x-CRYPTOCAP - Crypto Capability X */
333union ufs_crypto_cap_entry {
334 __le32 reg_val;
335 struct {
336 u8 algorithm_id;
337 u8 sdus_mask; /* Supported data unit size mask */
338 u8 key_size;
339 u8 reserved;
340 };
341};
342
343#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
344#define UFS_CRYPTO_KEY_MAX_SIZE 64
345/* x-CRYPTOCFG - Crypto Configuration X */
346union ufs_crypto_cfg_entry {
347 __le32 reg_val[32];
348 struct {
349 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
350 u8 data_unit_size;
351 u8 crypto_cap_idx;
352 u8 reserved_1;
353 u8 config_enable;
354 u8 reserved_multi_host;
355 u8 reserved_2;
356 u8 vsb[2];
357 u8 reserved_3[56];
358 };
359};
360
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530361/*
362 * Request Descriptor Definitions
363 */
364
365/* Transfer request command type */
366enum {
367 UTP_CMD_TYPE_SCSI = 0x0,
368 UTP_CMD_TYPE_UFS = 0x1,
369 UTP_CMD_TYPE_DEV_MANAGE = 0x2,
370};
371
Joao Pinto300bb132016-05-11 12:21:27 +0100372/* To accommodate UFS2.0 required Command type */
373enum {
374 UTP_CMD_TYPE_UFS_STORAGE = 0x1,
375};
376
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530377enum {
378 UTP_SCSI_COMMAND = 0x00000000,
379 UTP_NATIVE_UFS_COMMAND = 0x10000000,
380 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
381 UTP_REQ_DESC_INT_CMD = 0x01000000,
Satya Tangirala5e7341e2020-07-06 20:04:12 +0000382 UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000,
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530383};
384
385/* UTP Transfer Request Data Direction (DD) */
386enum {
387 UTP_NO_DATA_TRANSFER = 0x00000000,
388 UTP_HOST_TO_DEVICE = 0x02000000,
389 UTP_DEVICE_TO_HOST = 0x04000000,
390};
391
392/* Overall command status values */
Bart Van Assche957d63e2021-10-20 14:40:17 -0700393enum utp_ocs {
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530394 OCS_SUCCESS = 0x0,
395 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
396 OCS_INVALID_PRDT_ATTR = 0x2,
397 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
398 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
399 OCS_PEER_COMM_FAILURE = 0x5,
400 OCS_ABORTED = 0x6,
401 OCS_FATAL_ERROR = 0x7,
Satya Tangirala5e7341e2020-07-06 20:04:12 +0000402 OCS_DEVICE_FATAL_ERROR = 0x8,
403 OCS_INVALID_CRYPTO_CONFIG = 0x9,
404 OCS_GENERAL_CRYPTO_ERROR = 0xA,
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530405 OCS_INVALID_COMMAND_STATUS = 0x0F,
Bart Van Assche957d63e2021-10-20 14:40:17 -0700406};
407
408enum {
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530409 MASK_OCS = 0x0F,
410};
411
Akinobu Mitaeeda4742014-07-01 23:00:32 +0900412/* The maximum length of the data byte count field in the PRDT is 256KB */
413#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
414/* The granularity of the data byte count field in the PRDT is 32-bit */
415#define PRDT_DATA_BYTE_COUNT_PAD 4
416
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530417/**
418 * struct ufshcd_sg_entry - UFSHCI PRD Entry
Bart Van Assche1ea7d802021-10-20 14:40:24 -0700419 * @addr: Physical address; DW-0 and DW-1.
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530420 * @reserved: Reserved for future use DW-2
421 * @size: size of physical segment DW-3
422 */
423struct ufshcd_sg_entry {
Bart Van Assche1ea7d802021-10-20 14:40:24 -0700424 __le64 addr;
Sujit Reddy Thummae8c8e822014-05-26 10:59:10 +0530425 __le32 reserved;
426 __le32 size;
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530427};
428
429/**
Bart Van Assche91bb7652021-10-20 14:40:16 -0700430 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530431 * @command_upiu: Command UPIU Frame address
432 * @response_upiu: Response UPIU Frame address
433 * @prd_table: Physical Region Descriptor
434 */
435struct utp_transfer_cmd_desc {
436 u8 command_upiu[ALIGNED_UPIU_SIZE];
437 u8 response_upiu[ALIGNED_UPIU_SIZE];
438 struct ufshcd_sg_entry prd_table[SG_ALL];
439};
440
441/**
442 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
443 * @dword0: Descriptor Header DW0
444 * @dword1: Descriptor Header DW1
445 * @dword2: Descriptor Header DW2
446 * @dword3: Descriptor Header DW3
447 */
448struct request_desc_header {
Sujit Reddy Thummae8c8e822014-05-26 10:59:10 +0530449 __le32 dword_0;
450 __le32 dword_1;
451 __le32 dword_2;
452 __le32 dword_3;
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530453};
454
455/**
Bart Van Assche91bb7652021-10-20 14:40:16 -0700456 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530457 * @header: UTRD header DW-0 to DW-3
458 * @command_desc_base_addr_lo: UCD base address low DW-4
459 * @command_desc_base_addr_hi: UCD base address high DW-5
460 * @response_upiu_length: response UPIU length DW-6
461 * @response_upiu_offset: response UPIU offset DW-6
462 * @prd_table_length: Physical region descriptor length DW-7
463 * @prd_table_offset: Physical region descriptor offset DW-7
464 */
465struct utp_transfer_req_desc {
466
467 /* DW 0-3 */
468 struct request_desc_header header;
469
470 /* DW 4-5*/
Sujit Reddy Thummae8c8e822014-05-26 10:59:10 +0530471 __le32 command_desc_base_addr_lo;
472 __le32 command_desc_base_addr_hi;
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530473
474 /* DW 6 */
Sujit Reddy Thummae8c8e822014-05-26 10:59:10 +0530475 __le16 response_upiu_length;
476 __le16 response_upiu_offset;
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530477
478 /* DW 7 */
Sujit Reddy Thummae8c8e822014-05-26 10:59:10 +0530479 __le16 prd_table_length;
480 __le16 prd_table_offset;
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530481};
482
Christoph Hellwig391e3882018-10-07 17:30:32 +0300483/*
484 * UTMRD structure.
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530485 */
486struct utp_task_req_desc {
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530487 /* DW 0-3 */
488 struct request_desc_header header;
489
Christoph Hellwig391e3882018-10-07 17:30:32 +0300490 /* DW 4-11 - Task request UPIU structure */
Gustavo A. R. Silva1352eec2021-03-31 17:43:38 -0500491 struct {
492 struct utp_upiu_header req_header;
493 __be32 input_param1;
494 __be32 input_param2;
495 __be32 input_param3;
496 __be32 __reserved1[2];
497 } upiu_req;
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530498
Christoph Hellwig391e3882018-10-07 17:30:32 +0300499 /* DW 12-19 - Task Management Response UPIU structure */
Gustavo A. R. Silva1352eec2021-03-31 17:43:38 -0500500 struct {
501 struct utp_upiu_header rsp_header;
502 __be32 output_param1;
503 __be32 output_param2;
504 __be32 __reserved2[3];
505 } upiu_rsp;
Santosh Yaraganavi7a3e97b2012-02-29 12:11:50 +0530506};
507
508#endif /* End of Header */