Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers. |
| 3 | * |
| 4 | * This driver is heavily based upon: |
| 5 | * |
| 6 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 |
| 7 | * |
| 8 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> |
| 9 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. |
| 10 | * Portions Copyright (C) 2003 Red Hat Inc |
Sergei Shtylyov | 256ace9 | 2009-12-17 01:11:27 -0500 | [diff] [blame] | 11 | * Portions Copyright (C) 2005-2009 MontaVista Software, Inc. |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 12 | * |
| 13 | * |
| 14 | * TODO |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 15 | * Work out best PLL policy |
| 16 | */ |
| 17 | |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/blkdev.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <scsi/scsi_host.h> |
| 25 | #include <linux/libata.h> |
| 26 | |
| 27 | #define DRV_NAME "pata_hpt3x2n" |
Sergei Shtylyov | 1a1b172 | 2009-12-07 23:30:06 +0400 | [diff] [blame] | 28 | #define DRV_VERSION "0.3.10" |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 29 | |
| 30 | enum { |
| 31 | HPT_PCI_FAST = (1 << 31), |
| 32 | PCI66 = (1 << 1), |
| 33 | USE_DPLL = (1 << 0) |
| 34 | }; |
| 35 | |
| 36 | struct hpt_clock { |
| 37 | u8 xfer_speed; |
| 38 | u32 timing; |
| 39 | }; |
| 40 | |
| 41 | struct hpt_chip { |
| 42 | const char *name; |
| 43 | struct hpt_clock *clocks[3]; |
| 44 | }; |
| 45 | |
| 46 | /* key for bus clock timings |
| 47 | * bit |
Sergei Shtylyov | fd5e62e | 2009-12-07 23:38:11 +0400 | [diff] [blame] | 48 | * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. |
| 49 | * cycles = value + 1 |
| 50 | * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. |
| 51 | * cycles = value + 1 |
| 52 | * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 53 | * register access. |
Sergei Shtylyov | fd5e62e | 2009-12-07 23:38:11 +0400 | [diff] [blame] | 54 | * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 55 | * register access. |
Sergei Shtylyov | fd5e62e | 2009-12-07 23:38:11 +0400 | [diff] [blame] | 56 | * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. |
| 57 | * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. |
| 58 | * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. |
| 59 | * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 60 | * register access. |
Sergei Shtylyov | fd5e62e | 2009-12-07 23:38:11 +0400 | [diff] [blame] | 61 | * 28 UDMA enable. |
| 62 | * 29 DMA enable. |
| 63 | * 30 PIO_MST enable. If set, the chip is in bus master mode during |
| 64 | * PIO xfer. |
| 65 | * 31 FIFO enable. Only for PIO. |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 66 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 67 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 68 | /* 66MHz DPLL clocks */ |
| 69 | |
| 70 | static struct hpt_clock hpt3x2n_clocks[] = { |
| 71 | { XFER_UDMA_7, 0x1c869c62 }, |
| 72 | { XFER_UDMA_6, 0x1c869c62 }, |
| 73 | { XFER_UDMA_5, 0x1c8a9c62 }, |
| 74 | { XFER_UDMA_4, 0x1c8a9c62 }, |
| 75 | { XFER_UDMA_3, 0x1c8e9c62 }, |
| 76 | { XFER_UDMA_2, 0x1c929c62 }, |
| 77 | { XFER_UDMA_1, 0x1c9a9c62 }, |
| 78 | { XFER_UDMA_0, 0x1c829c62 }, |
| 79 | |
| 80 | { XFER_MW_DMA_2, 0x2c829c62 }, |
| 81 | { XFER_MW_DMA_1, 0x2c829c66 }, |
Bartlomiej Zolnierkiewicz | d413ff3 | 2009-12-03 20:32:09 +0100 | [diff] [blame] | 82 | { XFER_MW_DMA_0, 0x2c829d2e }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 83 | |
| 84 | { XFER_PIO_4, 0x0c829c62 }, |
| 85 | { XFER_PIO_3, 0x0c829c84 }, |
| 86 | { XFER_PIO_2, 0x0c829ca6 }, |
| 87 | { XFER_PIO_1, 0x0d029d26 }, |
| 88 | { XFER_PIO_0, 0x0d029d5e }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 89 | }; |
| 90 | |
| 91 | /** |
| 92 | * hpt3x2n_find_mode - reset the hpt3x2n bus |
| 93 | * @ap: ATA port |
| 94 | * @speed: transfer mode |
| 95 | * |
| 96 | * Return the 32bit register programming information for this channel |
| 97 | * that matches the speed provided. For the moment the clocks table |
| 98 | * is hard coded but easy to change. This will be needed if we use |
| 99 | * different DPLLs |
| 100 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 101 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 102 | static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed) |
| 103 | { |
| 104 | struct hpt_clock *clocks = hpt3x2n_clocks; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 105 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 106 | while(clocks->xfer_speed) { |
| 107 | if (clocks->xfer_speed == speed) |
| 108 | return clocks->timing; |
| 109 | clocks++; |
| 110 | } |
| 111 | BUG(); |
| 112 | return 0xffffffffU; /* silence compiler warning */ |
| 113 | } |
| 114 | |
| 115 | /** |
Jeff Garzik | a0fcdc0 | 2007-03-09 07:24:15 -0500 | [diff] [blame] | 116 | * hpt3x2n_cable_detect - Detect the cable type |
| 117 | * @ap: ATA port to detect on |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 118 | * |
Jeff Garzik | a0fcdc0 | 2007-03-09 07:24:15 -0500 | [diff] [blame] | 119 | * Return the cable type attached to this port |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 120 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 121 | |
Jeff Garzik | a0fcdc0 | 2007-03-09 07:24:15 -0500 | [diff] [blame] | 122 | static int hpt3x2n_cable_detect(struct ata_port *ap) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 123 | { |
| 124 | u8 scr2, ata66; |
| 125 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 126 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 127 | pci_read_config_byte(pdev, 0x5B, &scr2); |
| 128 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); |
Bartlomiej Zolnierkiewicz | 10a9c969 | 2009-11-19 20:31:31 +0100 | [diff] [blame] | 129 | |
| 130 | udelay(10); /* debounce */ |
| 131 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 132 | /* Cable register now active */ |
| 133 | pci_read_config_byte(pdev, 0x5A, &ata66); |
| 134 | /* Restore state */ |
| 135 | pci_write_config_byte(pdev, 0x5B, scr2); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 136 | |
Bartlomiej Zolnierkiewicz | f3b1cf4 | 2009-11-19 18:38:11 +0100 | [diff] [blame] | 137 | if (ata66 & (2 >> ap->port_no)) |
Jeff Garzik | a0fcdc0 | 2007-03-09 07:24:15 -0500 | [diff] [blame] | 138 | return ATA_CBL_PATA40; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 139 | else |
Jeff Garzik | a0fcdc0 | 2007-03-09 07:24:15 -0500 | [diff] [blame] | 140 | return ATA_CBL_PATA80; |
| 141 | } |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 142 | |
Jeff Garzik | a0fcdc0 | 2007-03-09 07:24:15 -0500 | [diff] [blame] | 143 | /** |
| 144 | * hpt3x2n_pre_reset - reset the hpt3x2n bus |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 145 | * @link: ATA link to reset |
Alan Cox | 28e21c8 | 2007-04-26 00:19:25 -0700 | [diff] [blame] | 146 | * @deadline: deadline jiffies for the operation |
Jeff Garzik | a0fcdc0 | 2007-03-09 07:24:15 -0500 | [diff] [blame] | 147 | * |
| 148 | * Perform the initial reset handling for the 3x2n series controllers. |
| 149 | * Reset the hardware and state machine, |
| 150 | */ |
| 151 | |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 152 | static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline) |
Jeff Garzik | a0fcdc0 | 2007-03-09 07:24:15 -0500 | [diff] [blame] | 153 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 154 | struct ata_port *ap = link->ap; |
Jeff Garzik | a0fcdc0 | 2007-03-09 07:24:15 -0500 | [diff] [blame] | 155 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 156 | /* Reset the state machine */ |
Alan Cox | 28e21c8 | 2007-04-26 00:19:25 -0700 | [diff] [blame] | 157 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 158 | udelay(100); |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 159 | |
Tejun Heo | 9363c38 | 2008-04-07 22:47:16 +0900 | [diff] [blame] | 160 | return ata_sff_prereset(link, deadline); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 161 | } |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 162 | |
Sergei Shtylyov | 1a1b172 | 2009-12-07 23:30:06 +0400 | [diff] [blame] | 163 | static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev, |
| 164 | u8 mode) |
| 165 | { |
| 166 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 167 | u32 addr1, addr2; |
| 168 | u32 reg, timing, mask; |
| 169 | u8 fast; |
| 170 | |
| 171 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); |
| 172 | addr2 = 0x51 + 4 * ap->port_no; |
| 173 | |
| 174 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
| 175 | pci_read_config_byte(pdev, addr2, &fast); |
| 176 | fast &= ~0x07; |
| 177 | pci_write_config_byte(pdev, addr2, fast); |
| 178 | |
| 179 | /* Determine timing mask and find matching mode entry */ |
| 180 | if (mode < XFER_MW_DMA_0) |
| 181 | mask = 0xcfc3ffff; |
| 182 | else if (mode < XFER_UDMA_0) |
| 183 | mask = 0x31c001ff; |
| 184 | else |
| 185 | mask = 0x303c0000; |
| 186 | |
| 187 | timing = hpt3x2n_find_mode(ap, mode); |
| 188 | |
| 189 | pci_read_config_dword(pdev, addr1, ®); |
| 190 | reg = (reg & ~mask) | (timing & mask); |
| 191 | pci_write_config_dword(pdev, addr1, reg); |
| 192 | } |
| 193 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 194 | /** |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 195 | * hpt3x2n_set_piomode - PIO setup |
| 196 | * @ap: ATA interface |
| 197 | * @adev: device on the interface |
| 198 | * |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 199 | * Perform PIO mode setup. |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 200 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 201 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 202 | static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev) |
| 203 | { |
Sergei Shtylyov | 1a1b172 | 2009-12-07 23:30:06 +0400 | [diff] [blame] | 204 | hpt3x2n_set_mode(ap, adev, adev->pio_mode); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 205 | } |
| 206 | |
| 207 | /** |
| 208 | * hpt3x2n_set_dmamode - DMA timing setup |
| 209 | * @ap: ATA interface |
| 210 | * @adev: Device being configured |
| 211 | * |
Sergei Shtylyov | 1a1b172 | 2009-12-07 23:30:06 +0400 | [diff] [blame] | 212 | * Set up the channel for MWDMA or UDMA modes. |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 213 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 214 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 215 | static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
| 216 | { |
Sergei Shtylyov | 1a1b172 | 2009-12-07 23:30:06 +0400 | [diff] [blame] | 217 | hpt3x2n_set_mode(ap, adev, adev->dma_mode); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | /** |
| 221 | * hpt3x2n_bmdma_end - DMA engine stop |
| 222 | * @qc: ATA command |
| 223 | * |
| 224 | * Clean up after the HPT3x2n and later DMA engine |
| 225 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 226 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 227 | static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc) |
| 228 | { |
| 229 | struct ata_port *ap = qc->ap; |
| 230 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 231 | int mscreg = 0x50 + 2 * ap->port_no; |
| 232 | u8 bwsr_stat, msc_stat; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 233 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 234 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
| 235 | pci_read_config_byte(pdev, mscreg, &msc_stat); |
| 236 | if (bwsr_stat & (1 << ap->port_no)) |
| 237 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); |
| 238 | ata_bmdma_stop(qc); |
| 239 | } |
| 240 | |
| 241 | /** |
| 242 | * hpt3x2n_set_clock - clock control |
| 243 | * @ap: ATA port |
| 244 | * @source: 0x21 or 0x23 for PLL or PCI sourced clock |
| 245 | * |
| 246 | * Switch the ATA bus clock between the PLL and PCI clock sources |
| 247 | * while correctly isolating the bus and resetting internal logic |
| 248 | * |
| 249 | * We must use the DPLL for |
| 250 | * - writing |
| 251 | * - second channel UDMA7 (SATA ports) or higher |
| 252 | * - 66MHz PCI |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 253 | * |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 254 | * or we will underclock the device and get reduced performance. |
| 255 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 256 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 257 | static void hpt3x2n_set_clock(struct ata_port *ap, int source) |
| 258 | { |
Sergei Shtylyov | 256ace9 | 2009-12-17 01:11:27 -0500 | [diff] [blame] | 259 | void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 260 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 261 | /* Tristate the bus */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 262 | iowrite8(0x80, bmdma+0x73); |
| 263 | iowrite8(0x80, bmdma+0x77); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 264 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 265 | /* Switch clock and reset channels */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 266 | iowrite8(source, bmdma+0x7B); |
| 267 | iowrite8(0xC0, bmdma+0x79); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 268 | |
Sergei Shtylyov | 256ace9 | 2009-12-17 01:11:27 -0500 | [diff] [blame] | 269 | /* Reset state machines, avoid enabling the disabled channels */ |
| 270 | iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70); |
| 271 | iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 272 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 273 | /* Complete reset */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 274 | iowrite8(0x00, bmdma+0x79); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 275 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 276 | /* Reconnect channels to bus */ |
Tejun Heo | 0d5ff56 | 2007-02-01 15:06:36 +0900 | [diff] [blame] | 277 | iowrite8(0x00, bmdma+0x73); |
| 278 | iowrite8(0x00, bmdma+0x77); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 279 | } |
| 280 | |
Alan | a52865c | 2007-01-24 11:51:38 +0000 | [diff] [blame] | 281 | static int hpt3x2n_use_dpll(struct ata_port *ap, int writing) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 282 | { |
| 283 | long flags = (long)ap->host->private_data; |
Sergei Shtylyov | 256ace9 | 2009-12-17 01:11:27 -0500 | [diff] [blame] | 284 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 285 | /* See if we should use the DPLL */ |
Alan | a52865c | 2007-01-24 11:51:38 +0000 | [diff] [blame] | 286 | if (writing) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 287 | return USE_DPLL; /* Needed for write */ |
| 288 | if (flags & PCI66) |
| 289 | return USE_DPLL; /* Needed at 66Mhz */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 290 | return 0; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 291 | } |
| 292 | |
Sergei Shtylyov | 256ace9 | 2009-12-17 01:11:27 -0500 | [diff] [blame] | 293 | static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc) |
| 294 | { |
| 295 | struct ata_port *ap = qc->ap; |
| 296 | struct ata_port *alt = ap->host->ports[ap->port_no ^ 1]; |
| 297 | int rc, flags = (long)ap->host->private_data; |
| 298 | int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); |
| 299 | |
| 300 | /* First apply the usual rules */ |
| 301 | rc = ata_std_qc_defer(qc); |
| 302 | if (rc != 0) |
| 303 | return rc; |
| 304 | |
| 305 | if ((flags & USE_DPLL) != dpll && alt->qc_active) |
| 306 | return ATA_DEFER_PORT; |
| 307 | return 0; |
| 308 | } |
| 309 | |
Tejun Heo | 9363c38 | 2008-04-07 22:47:16 +0900 | [diff] [blame] | 310 | static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 311 | { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 312 | struct ata_port *ap = qc->ap; |
| 313 | int flags = (long)ap->host->private_data; |
Sergei Shtylyov | 256ace9 | 2009-12-17 01:11:27 -0500 | [diff] [blame] | 314 | int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 315 | |
Sergei Shtylyov | 256ace9 | 2009-12-17 01:11:27 -0500 | [diff] [blame] | 316 | if ((flags & USE_DPLL) != dpll) { |
| 317 | flags &= ~USE_DPLL; |
| 318 | flags |= dpll; |
| 319 | ap->host->private_data = (void *)(long)flags; |
| 320 | |
| 321 | hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 322 | } |
Tejun Heo | 9363c38 | 2008-04-07 22:47:16 +0900 | [diff] [blame] | 323 | return ata_sff_qc_issue(qc); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | static struct scsi_host_template hpt3x2n_sht = { |
Tejun Heo | 68d1d07 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 327 | ATA_BMDMA_SHT(DRV_NAME), |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 328 | }; |
| 329 | |
| 330 | /* |
| 331 | * Configuration for HPT3x2n. |
| 332 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 333 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 334 | static struct ata_port_operations hpt3x2n_port_ops = { |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 335 | .inherits = &ata_bmdma_port_ops, |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 336 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 337 | .bmdma_stop = hpt3x2n_bmdma_stop, |
Sergei Shtylyov | 256ace9 | 2009-12-17 01:11:27 -0500 | [diff] [blame] | 338 | |
| 339 | .qc_defer = hpt3x2n_qc_defer, |
Tejun Heo | 9363c38 | 2008-04-07 22:47:16 +0900 | [diff] [blame] | 340 | .qc_issue = hpt3x2n_qc_issue, |
Jeff Garzik | bda3028 | 2006-09-27 05:41:13 -0400 | [diff] [blame] | 341 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 342 | .cable_detect = hpt3x2n_cable_detect, |
| 343 | .set_piomode = hpt3x2n_set_piomode, |
| 344 | .set_dmamode = hpt3x2n_set_dmamode, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 345 | .prereset = hpt3x2n_pre_reset, |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 346 | }; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 347 | |
| 348 | /** |
| 349 | * hpt3xn_calibrate_dpll - Calibrate the DPLL loop |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 350 | * @dev: PCI device |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 351 | * |
| 352 | * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this |
| 353 | * succeeds |
| 354 | */ |
| 355 | |
| 356 | static int hpt3xn_calibrate_dpll(struct pci_dev *dev) |
| 357 | { |
| 358 | u8 reg5b; |
| 359 | u32 reg5c; |
| 360 | int tries; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 361 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 362 | for(tries = 0; tries < 0x5000; tries++) { |
| 363 | udelay(50); |
| 364 | pci_read_config_byte(dev, 0x5b, ®5b); |
| 365 | if (reg5b & 0x80) { |
| 366 | /* See if it stays set */ |
| 367 | for(tries = 0; tries < 0x1000; tries ++) { |
| 368 | pci_read_config_byte(dev, 0x5b, ®5b); |
| 369 | /* Failed ? */ |
| 370 | if ((reg5b & 0x80) == 0) |
| 371 | return 0; |
| 372 | } |
| 373 | /* Turn off tuning, we have the DPLL set */ |
| 374 | pci_read_config_dword(dev, 0x5c, ®5c); |
| 375 | pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100); |
| 376 | return 1; |
| 377 | } |
| 378 | } |
| 379 | /* Never went stable */ |
| 380 | return 0; |
| 381 | } |
| 382 | |
| 383 | static int hpt3x2n_pci_clock(struct pci_dev *pdev) |
| 384 | { |
| 385 | unsigned long freq; |
| 386 | u32 fcnt; |
Alan Cox | 28e21c8 | 2007-04-26 00:19:25 -0700 | [diff] [blame] | 387 | unsigned long iobase = pci_resource_start(pdev, 4); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 388 | |
Alan Cox | 28e21c8 | 2007-04-26 00:19:25 -0700 | [diff] [blame] | 389 | fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 390 | if ((fcnt >> 12) != 0xABCDE) { |
| 391 | printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n"); |
| 392 | return 33; /* Not BIOS set */ |
| 393 | } |
| 394 | fcnt &= 0x1FF; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 395 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 396 | freq = (fcnt * 77) / 192; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 397 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 398 | /* Clamp to bands */ |
| 399 | if (freq < 40) |
| 400 | return 33; |
| 401 | if (freq < 45) |
| 402 | return 40; |
| 403 | if (freq < 55) |
| 404 | return 50; |
| 405 | return 66; |
| 406 | } |
| 407 | |
| 408 | /** |
| 409 | * hpt3x2n_init_one - Initialise an HPT37X/302 |
| 410 | * @dev: PCI device |
| 411 | * @id: Entry in match table |
| 412 | * |
| 413 | * Initialise an HPT3x2n device. There are some interesting complications |
| 414 | * here. Firstly the chip may report 366 and be one of several variants. |
| 415 | * Secondly all the timings depend on the clock for the chip which we must |
| 416 | * detect and look up |
| 417 | * |
| 418 | * This is the known chip mappings. It may be missing a couple of later |
| 419 | * releases. |
| 420 | * |
| 421 | * Chip version PCI Rev Notes |
| 422 | * HPT372 4 (HPT366) 5 Other driver |
| 423 | * HPT372N 4 (HPT366) 6 UDMA133 |
| 424 | * HPT372 5 (HPT372) 1 Other driver |
| 425 | * HPT372N 5 (HPT372) 2 UDMA133 |
| 426 | * HPT302 6 (HPT302) * Other driver |
| 427 | * HPT302N 6 (HPT302) > 1 UDMA133 |
| 428 | * HPT371 7 (HPT371) * Other driver |
| 429 | * HPT371N 7 (HPT371) > 1 UDMA133 |
| 430 | * HPT374 8 (HPT374) * Other driver |
| 431 | * HPT372N 9 (HPT372N) * UDMA133 |
| 432 | * |
| 433 | * (1) UDMA133 support depends on the bus clock |
| 434 | * |
| 435 | * To pin down HPT371N |
| 436 | */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 437 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 438 | static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
| 439 | { |
| 440 | /* HPT372N and friends - UDMA133 */ |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 441 | static const struct ata_port_info info = { |
Jeff Garzik | 1d2808f | 2007-05-28 06:59:48 -0400 | [diff] [blame] | 442 | .flags = ATA_FLAG_SLAVE_POSS, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 443 | .pio_mask = ATA_PIO4, |
| 444 | .mwdma_mask = ATA_MWDMA2, |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 445 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 446 | .port_ops = &hpt3x2n_port_ops |
| 447 | }; |
Tejun Heo | 887125e | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 448 | const struct ata_port_info *ppi[] = { &info, NULL }; |
Sergei Shtylyov | 89d3b36 | 2009-11-24 22:54:49 +0400 | [diff] [blame] | 449 | u8 rev = dev->revision; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 450 | u8 irqmask; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 451 | unsigned int pci_mhz; |
| 452 | unsigned int f_low, f_high; |
| 453 | int adjust; |
Alan Cox | 28e21c8 | 2007-04-26 00:19:25 -0700 | [diff] [blame] | 454 | unsigned long iobase = pci_resource_start(dev, 4); |
Sergei Shtylyov | 256ace9 | 2009-12-17 01:11:27 -0500 | [diff] [blame] | 455 | void *hpriv = (void *)USE_DPLL; |
Tejun Heo | f08048e | 2008-03-25 12:22:47 +0900 | [diff] [blame] | 456 | int rc; |
| 457 | |
| 458 | rc = pcim_enable_device(dev); |
| 459 | if (rc) |
| 460 | return rc; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 461 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 462 | switch(dev->device) { |
| 463 | case PCI_DEVICE_ID_TTI_HPT366: |
Sergei Shtylyov | 89d3b36 | 2009-11-24 22:54:49 +0400 | [diff] [blame] | 464 | if (rev < 6) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 465 | return -ENODEV; |
| 466 | break; |
Alan Cox | 28e21c8 | 2007-04-26 00:19:25 -0700 | [diff] [blame] | 467 | case PCI_DEVICE_ID_TTI_HPT371: |
Sergei Shtylyov | 89d3b36 | 2009-11-24 22:54:49 +0400 | [diff] [blame] | 468 | if (rev < 2) |
Alan Cox | 28e21c8 | 2007-04-26 00:19:25 -0700 | [diff] [blame] | 469 | return -ENODEV; |
| 470 | /* 371N if rev > 1 */ |
| 471 | break; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 472 | case PCI_DEVICE_ID_TTI_HPT372: |
Alan Cox | 824cf33 | 2007-05-21 14:57:01 +0100 | [diff] [blame] | 473 | /* 372N if rev >= 2*/ |
Sergei Shtylyov | 89d3b36 | 2009-11-24 22:54:49 +0400 | [diff] [blame] | 474 | if (rev < 2) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 475 | return -ENODEV; |
| 476 | break; |
| 477 | case PCI_DEVICE_ID_TTI_HPT302: |
Sergei Shtylyov | 89d3b36 | 2009-11-24 22:54:49 +0400 | [diff] [blame] | 478 | if (rev < 2) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 479 | return -ENODEV; |
| 480 | break; |
| 481 | case PCI_DEVICE_ID_TTI_HPT372N: |
| 482 | break; |
| 483 | default: |
| 484 | printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device); |
| 485 | return -ENODEV; |
| 486 | } |
| 487 | |
| 488 | /* Ok so this is a chip we support */ |
| 489 | |
| 490 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); |
| 491 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); |
| 492 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); |
| 493 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); |
| 494 | |
| 495 | pci_read_config_byte(dev, 0x5A, &irqmask); |
| 496 | irqmask &= ~0x10; |
| 497 | pci_write_config_byte(dev, 0x5a, irqmask); |
| 498 | |
Alan Cox | 28e21c8 | 2007-04-26 00:19:25 -0700 | [diff] [blame] | 499 | /* |
| 500 | * HPT371 chips physically have only one channel, the secondary one, |
| 501 | * but the primary channel registers do exist! Go figure... |
| 502 | * So, we manually disable the non-existing channel here |
| 503 | * (if the BIOS hasn't done this already). |
| 504 | */ |
| 505 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { |
| 506 | u8 mcr1; |
| 507 | pci_read_config_byte(dev, 0x50, &mcr1); |
| 508 | mcr1 &= ~0x04; |
| 509 | pci_write_config_byte(dev, 0x50, mcr1); |
| 510 | } |
| 511 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 512 | /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or |
| 513 | 50 for UDMA100. Right now we always use 66 */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 514 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 515 | pci_mhz = hpt3x2n_pci_clock(dev); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 516 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 517 | f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */ |
| 518 | f_high = f_low + 2; /* Tolerance */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 519 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 520 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); |
| 521 | /* PLL clock */ |
| 522 | pci_write_config_byte(dev, 0x5B, 0x21); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 523 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 524 | /* Unlike the 37x we don't try jiggling the frequency */ |
| 525 | for(adjust = 0; adjust < 8; adjust++) { |
| 526 | if (hpt3xn_calibrate_dpll(dev)) |
| 527 | break; |
| 528 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); |
| 529 | } |
Alan Cox | 28e21c8 | 2007-04-26 00:19:25 -0700 | [diff] [blame] | 530 | if (adjust == 8) { |
Sergei Shtylyov | 80b8987 | 2007-08-10 21:02:15 +0400 | [diff] [blame] | 531 | printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n"); |
Alan Cox | 28e21c8 | 2007-04-26 00:19:25 -0700 | [diff] [blame] | 532 | return -ENODEV; |
| 533 | } |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 534 | |
Sergei Shtylyov | 80b8987 | 2007-08-10 21:02:15 +0400 | [diff] [blame] | 535 | printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n", |
| 536 | pci_mhz); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 537 | /* Set our private data up. We only need a few flags so we use |
| 538 | it directly */ |
Sergei Shtylyov | 6066193 | 2009-12-07 23:25:52 +0400 | [diff] [blame] | 539 | if (pci_mhz > 60) |
Sergei Shtylyov | 256ace9 | 2009-12-17 01:11:27 -0500 | [diff] [blame] | 540 | hpriv = (void *)(PCI66 | USE_DPLL); |
Sergei Shtylyov | 6066193 | 2009-12-07 23:25:52 +0400 | [diff] [blame] | 541 | |
| 542 | /* |
| 543 | * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in |
| 544 | * the MISC. register to stretch the UltraDMA Tss timing. |
| 545 | * NOTE: This register is only writeable via I/O space. |
| 546 | */ |
| 547 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) |
| 548 | outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 549 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 550 | /* Now kick off ATA set up */ |
Alan Cox | 16ea0fc | 2010-02-23 02:26:06 -0500 | [diff] [blame] | 551 | return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 552 | } |
| 553 | |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 554 | static const struct pci_device_id hpt3x2n[] = { |
| 555 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, |
Alan Cox | 28e21c8 | 2007-04-26 00:19:25 -0700 | [diff] [blame] | 556 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 557 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, |
| 558 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, |
| 559 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), }, |
| 560 | |
| 561 | { }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 562 | }; |
| 563 | |
| 564 | static struct pci_driver hpt3x2n_pci_driver = { |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 565 | .name = DRV_NAME, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 566 | .id_table = hpt3x2n, |
| 567 | .probe = hpt3x2n_init_one, |
| 568 | .remove = ata_pci_remove_one |
| 569 | }; |
| 570 | |
| 571 | static int __init hpt3x2n_init(void) |
| 572 | { |
| 573 | return pci_register_driver(&hpt3x2n_pci_driver); |
| 574 | } |
| 575 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 576 | static void __exit hpt3x2n_exit(void) |
| 577 | { |
| 578 | pci_unregister_driver(&hpt3x2n_pci_driver); |
| 579 | } |
| 580 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 581 | MODULE_AUTHOR("Alan Cox"); |
| 582 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x"); |
| 583 | MODULE_LICENSE("GPL"); |
| 584 | MODULE_DEVICE_TABLE(pci, hpt3x2n); |
| 585 | MODULE_VERSION(DRV_VERSION); |
| 586 | |
| 587 | module_init(hpt3x2n_init); |
| 588 | module_exit(hpt3x2n_exit); |