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Andrei Konovalovae918c02007-07-17 04:04:11 -07001/*
Andrei Konovalovae918c02007-07-17 04:04:11 -07002 * Xilinx SPI controller driver (master mode only)
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
Grant Likely8fd88212010-10-14 09:04:29 -06007 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
8 * Copyright (c) 2009 Intel Corporation
9 * 2002-2007 (c) MontaVista Software, Inc.
10
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
Andrei Konovalovae918c02007-07-17 04:04:11 -070014 */
15
16#include <linux/module.h>
Andrei Konovalovae918c02007-07-17 04:04:11 -070017#include <linux/interrupt.h>
Grant Likelyeae6cb32010-10-14 09:32:53 -060018#include <linux/of.h>
Grant Likely8fd88212010-10-14 09:04:29 -060019#include <linux/platform_device.h>
Andrei Konovalovae918c02007-07-17 04:04:11 -070020#include <linux/spi/spi.h>
21#include <linux/spi/spi_bitbang.h>
Richard Röjforsd5af91a2009-11-13 12:28:39 +010022#include <linux/spi/xilinx_spi.h>
Grant Likelyeae6cb32010-10-14 09:32:53 -060023#include <linux/io.h>
Richard Röjforsd5af91a2009-11-13 12:28:39 +010024
Ricardo Ribaldaeb25f162015-01-28 20:53:39 +010025#define XILINX_SPI_MAX_CS 32
26
David Brownellfc3ba952007-08-30 23:56:24 -070027#define XILINX_SPI_NAME "xilinx_spi"
Andrei Konovalovae918c02007-07-17 04:04:11 -070028
29/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
30 * Product Specification", DS464
31 */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010032#define XSPI_CR_OFFSET 0x60 /* Control Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070033
Michal Simek082339b2013-06-04 16:02:36 +020034#define XSPI_CR_LOOP 0x01
Andrei Konovalovae918c02007-07-17 04:04:11 -070035#define XSPI_CR_ENABLE 0x02
36#define XSPI_CR_MASTER_MODE 0x04
37#define XSPI_CR_CPOL 0x08
38#define XSPI_CR_CPHA 0x10
Ricardo Ribalda Delgadobca690d2015-01-23 17:08:33 +010039#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \
Ricardo Ribalda Delgado0240f942015-01-23 17:08:34 +010040 XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
Andrei Konovalovae918c02007-07-17 04:04:11 -070041#define XSPI_CR_TXFIFO_RESET 0x20
42#define XSPI_CR_RXFIFO_RESET 0x40
43#define XSPI_CR_MANUAL_SSELECT 0x80
44#define XSPI_CR_TRANS_INHIBIT 0x100
Richard Röjforsc9da2e12009-11-13 12:28:55 +010045#define XSPI_CR_LSB_FIRST 0x200
Andrei Konovalovae918c02007-07-17 04:04:11 -070046
Richard Röjforsc9da2e12009-11-13 12:28:55 +010047#define XSPI_SR_OFFSET 0x64 /* Status Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070048
49#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
50#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
51#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
52#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
53#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
54
Richard Röjforsc9da2e12009-11-13 12:28:55 +010055#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
56#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
Andrei Konovalovae918c02007-07-17 04:04:11 -070057
58#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
59
60/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
61 * IPIF registers are 32 bit
62 */
63#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
64#define XIPIF_V123B_GINTR_ENABLE 0x80000000
65
66#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
67#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
68
69#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
70#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
71 * disabled */
72#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
73#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
74#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
75#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
Richard Röjforsc9da2e12009-11-13 12:28:55 +010076#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
Andrei Konovalovae918c02007-07-17 04:04:11 -070077
78#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
79#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
80
81struct xilinx_spi {
82 /* bitbang has to be first */
83 struct spi_bitbang bitbang;
84 struct completion done;
Andrei Konovalovae918c02007-07-17 04:04:11 -070085 void __iomem *regs; /* virt. address of the control registers */
86
Dan Carpenter9ca12732013-07-17 18:34:48 +030087 int irq;
Andrei Konovalovae918c02007-07-17 04:04:11 -070088
Andrei Konovalovae918c02007-07-17 04:04:11 -070089 u8 *rx_ptr; /* pointer in the Tx buffer */
90 const u8 *tx_ptr; /* pointer in the Rx buffer */
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +010091 u8 bytes_per_word;
Ricardo Ribalda Delgado4c9a7612015-01-28 13:23:40 +010092 int buffer_size; /* buffer size in words */
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +010093 u32 cs_inactive; /* Level of the CS pins when inactive*/
Jingoo Han6ff86722014-02-26 10:24:47 +090094 unsigned int (*read_fn)(void __iomem *);
95 void (*write_fn)(u32, void __iomem *);
Andrei Konovalovae918c02007-07-17 04:04:11 -070096};
97
Mark Brown06352872015-01-30 13:42:00 +010098static void xspi_write32(u32 val, void __iomem *addr)
99{
100 iowrite32(val, addr);
101}
102
103static unsigned int xspi_read32(void __iomem *addr)
104{
105 return ioread32(addr);
106}
107
108static void xspi_write32_be(u32 val, void __iomem *addr)
109{
110 iowrite32be(val, addr);
111}
112
113static unsigned int xspi_read32_be(void __iomem *addr)
114{
115 return ioread32be(addr);
116}
117
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100118static void xilinx_spi_tx(struct xilinx_spi *xspi)
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100119{
Ricardo Ribalda Delgado34093cb2015-02-02 11:06:56 +0100120 u32 data = 0;
121
Ricardo Ribalda Delgadoc3092942015-01-28 13:23:48 +0100122 if (!xspi->tx_ptr) {
123 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
124 return;
125 }
Ricardo Ribalda Delgado34093cb2015-02-02 11:06:56 +0100126
127 switch (xspi->bytes_per_word) {
128 case 1:
129 data = *(u8 *)(xspi->tx_ptr);
130 break;
131 case 2:
132 data = *(u16 *)(xspi->tx_ptr);
133 break;
134 case 4:
135 data = *(u32 *)(xspi->tx_ptr);
136 break;
137 }
138
139 xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET);
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +0100140 xspi->tx_ptr += xspi->bytes_per_word;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100141}
142
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100143static void xilinx_spi_rx(struct xilinx_spi *xspi)
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100144{
145 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100146
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100147 if (!xspi->rx_ptr)
148 return;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100149
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +0100150 switch (xspi->bytes_per_word) {
151 case 1:
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100152 *(u8 *)(xspi->rx_ptr) = data;
153 break;
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +0100154 case 2:
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100155 *(u16 *)(xspi->rx_ptr) = data;
156 break;
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +0100157 case 4:
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100158 *(u32 *)(xspi->rx_ptr) = data;
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100159 break;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100160 }
Ricardo Ribalda Delgado24ba5e52015-01-28 13:23:47 +0100161
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +0100162 xspi->rx_ptr += xspi->bytes_per_word;
Richard Röjforsc9da2e12009-11-13 12:28:55 +0100163}
164
Richard Röjfors86fc5932009-11-13 12:28:49 +0100165static void xspi_init_hw(struct xilinx_spi *xspi)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700166{
Richard Röjfors86fc5932009-11-13 12:28:49 +0100167 void __iomem *regs_base = xspi->regs;
168
Andrei Konovalovae918c02007-07-17 04:04:11 -0700169 /* Reset the SPI device */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100170 xspi->write_fn(XIPIF_V123B_RESET_MASK,
171 regs_base + XIPIF_V123B_RESETR_OFFSET);
Ricardo Ribalda Delgado899929ba2015-01-28 13:23:41 +0100172 /* Enable the transmit empty interrupt, which we use to determine
173 * progress on the transmission.
174 */
175 xspi->write_fn(XSPI_INTR_TX_EMPTY,
176 regs_base + XIPIF_V123B_IIER_OFFSET);
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100177 /* Disable the global IPIF interrupt */
178 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700179 /* Deselect the slave on the SPI bus */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100180 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700181 /* Disable the transmitter, enable Manual Slave Select Assertion,
182 * put SPI controller into master mode, and enable it */
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100183 xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE |
184 XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET,
185 regs_base + XSPI_CR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700186}
187
188static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
189{
190 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +0100191 u16 cr;
192 u32 cs;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700193
194 if (is_on == BITBANG_CS_INACTIVE) {
195 /* Deselect the slave on the SPI bus */
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +0100196 xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
197 return;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700198 }
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +0100199
200 /* Set the SPI clock phase and polarity */
201 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK;
202 if (spi->mode & SPI_CPHA)
203 cr |= XSPI_CR_CPHA;
204 if (spi->mode & SPI_CPOL)
205 cr |= XSPI_CR_CPOL;
206 if (spi->mode & SPI_LSB_FIRST)
207 cr |= XSPI_CR_LSB_FIRST;
208 if (spi->mode & SPI_LOOP)
209 cr |= XSPI_CR_LOOP;
210 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
211
212 /* We do not check spi->max_speed_hz here as the SPI clock
213 * frequency is not software programmable (the IP block design
214 * parameter)
215 */
216
217 cs = xspi->cs_inactive;
218 cs ^= BIT(spi->chip_select);
219
220 /* Activate the chip select */
221 xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700222}
223
224/* spi_bitbang requires custom setup_transfer() to be defined if there is a
Axel Lin9bf46f62014-02-14 21:06:43 +0800225 * custom txrx_bufs().
Andrei Konovalovae918c02007-07-17 04:04:11 -0700226 */
227static int xilinx_spi_setup_transfer(struct spi_device *spi,
228 struct spi_transfer *t)
229{
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +0100230 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
231
232 if (spi->mode & SPI_CS_HIGH)
233 xspi->cs_inactive &= ~BIT(spi->chip_select);
234 else
235 xspi->cs_inactive |= BIT(spi->chip_select);
236
Andrei Konovalovae918c02007-07-17 04:04:11 -0700237 return 0;
238}
239
Andrei Konovalovae918c02007-07-17 04:04:11 -0700240static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
241{
242 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100243 int remaining_words; /* the number of words left to transfer */
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100244 bool use_irq = false;
245 u16 cr = 0;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700246
247 /* We get here with transmitter inhibited */
248
249 xspi->tx_ptr = t->tx_buf;
250 xspi->rx_ptr = t->rx_buf;
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100251 remaining_words = t->len / xspi->bytes_per_word;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700252
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100253 if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) {
Ricardo Ribalda Delgado74346842015-08-13 16:09:28 +0200254 u32 isr;
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100255 use_irq = true;
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100256 /* Inhibit irq to avoid spurious irqs on tx_empty*/
257 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
258 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
259 xspi->regs + XSPI_CR_OFFSET);
Ricardo Ribalda Delgado74346842015-08-13 16:09:28 +0200260 /* ACK old irqs (if any) */
261 isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
262 if (isr)
263 xspi->write_fn(isr,
264 xspi->regs + XIPIF_V123B_IISR_OFFSET);
265 /* Enable the global IPIF interrupt */
266 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
267 xspi->regs + XIPIF_V123B_DGIER_OFFSET);
268 reinit_completion(&xspi->done);
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100269 }
270
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100271 while (remaining_words) {
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100272 int n_words, tx_words, rx_words;
Ricardo Ribalda Delgadoeca37c72015-10-28 16:16:02 +0100273 u32 sr;
Ricardo Ribalda5a1314f2017-11-21 10:09:02 +0100274 int stalled;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700275
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100276 n_words = min(remaining_words, xspi->buffer_size);
Ricardo Ribalda Delgado4c9a7612015-01-28 13:23:40 +0100277
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100278 tx_words = n_words;
279 while (tx_words--)
280 xilinx_spi_tx(xspi);
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200281
282 /* Start the transfer by not inhibiting the transmitter any
283 * longer
284 */
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200285
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100286 if (use_irq) {
Ricardo Ribalda Delgadod9f58812015-01-28 13:23:45 +0100287 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
Ricardo Ribalda Delgado5fe11cc2015-01-28 13:23:44 +0100288 wait_for_completion(&xspi->done);
Ricardo Ribalda Delgadoeca37c72015-10-28 16:16:02 +0100289 /* A transmit has just completed. Process received data
290 * and check for more data to transmit. Always inhibit
291 * the transmitter while the Isr refills the transmit
292 * register/FIFO, or make sure it is stopped if we're
293 * done.
294 */
Ricardo Ribalda Delgadod9f58812015-01-28 13:23:45 +0100295 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
Ricardo Ribalda Delgadoeca37c72015-10-28 16:16:02 +0100296 xspi->regs + XSPI_CR_OFFSET);
297 sr = XSPI_SR_TX_EMPTY_MASK;
298 } else
299 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200300
301 /* Read out all the data from the Rx FIFO */
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100302 rx_words = n_words;
Ricardo Ribalda5a1314f2017-11-21 10:09:02 +0100303 stalled = 10;
Ricardo Ribalda Delgadoeca37c72015-10-28 16:16:02 +0100304 while (rx_words) {
Ricardo Ribalda5a1314f2017-11-21 10:09:02 +0100305 if (rx_words == n_words && !(stalled--) &&
306 !(sr & XSPI_SR_TX_EMPTY_MASK) &&
307 (sr & XSPI_SR_RX_EMPTY_MASK)) {
308 dev_err(&spi->dev,
309 "Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n");
310 xspi_init_hw(xspi);
311 return -EIO;
312 }
313
Ricardo Ribalda Delgadoeca37c72015-10-28 16:16:02 +0100314 if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) {
315 xilinx_spi_rx(xspi);
316 rx_words--;
317 continue;
318 }
319
320 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
321 if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
322 xilinx_spi_rx(xspi);
323 rx_words--;
324 }
325 }
Ricardo Ribalda Delgadob563bfb2015-01-28 13:23:52 +0100326
327 remaining_words -= n_words;
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200328 }
Andrei Konovalovae918c02007-07-17 04:04:11 -0700329
Ricardo Ribalda Delgado16ea9b82015-08-12 18:04:04 +0200330 if (use_irq) {
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100331 xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
Ricardo Ribalda Delgado16ea9b82015-08-12 18:04:04 +0200332 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
333 }
Ricardo Ribalda Delgado22417352015-01-28 13:23:54 +0100334
Ricardo Ribalda Delgadod79b2d02015-01-28 13:23:49 +0100335 return t->len;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700336}
337
338
339/* This driver supports single master mode only. Hence Tx FIFO Empty
340 * is the only interrupt we care about.
341 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
342 * Fault are not to happen.
343 */
344static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
345{
346 struct xilinx_spi *xspi = dev_id;
347 u32 ipif_isr;
348
349 /* Get the IPIF interrupts, and clear them immediately */
Richard Röjfors86fc5932009-11-13 12:28:49 +0100350 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
351 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700352
353 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
Peter Crosthwaite68c315b2013-06-04 16:02:34 +0200354 complete(&xspi->done);
Lars-Peter Clausend3364842016-07-15 11:04:19 +0200355 return IRQ_HANDLED;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700356 }
357
Lars-Peter Clausend3364842016-07-15 11:04:19 +0200358 return IRQ_NONE;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700359}
360
Ricardo Ribalda Delgado4c9a7612015-01-28 13:23:40 +0100361static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
362{
363 u8 sr;
364 int n_words = 0;
365
366 /*
367 * Before the buffer_size detection we reset the core
368 * to make sure we start with a clean state.
369 */
370 xspi->write_fn(XIPIF_V123B_RESET_MASK,
371 xspi->regs + XIPIF_V123B_RESETR_OFFSET);
372
373 /* Fill the Tx FIFO with as many words as possible */
374 do {
375 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
376 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
377 n_words++;
378 } while (!(sr & XSPI_SR_TX_FULL_MASK));
379
380 return n_words;
381}
382
Grant Likelyeae6cb32010-10-14 09:32:53 -0600383static const struct of_device_id xilinx_spi_of_match[] = {
Ricardo Ribaldaa094c2f2017-11-21 10:09:03 +0100384 { .compatible = "xlnx,axi-quad-spi-1.00.a", },
Grant Likelyeae6cb32010-10-14 09:32:53 -0600385 { .compatible = "xlnx,xps-spi-2.00.a", },
386 { .compatible = "xlnx,xps-spi-2.00.b", },
387 {}
388};
389MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
Grant Likelyeae6cb32010-10-14 09:32:53 -0600390
Mark Brown7cb2abd2013-07-05 11:24:26 +0100391static int xilinx_spi_probe(struct platform_device *pdev)
Andrei Konovalovae918c02007-07-17 04:04:11 -0700392{
Andrei Konovalovae918c02007-07-17 04:04:11 -0700393 struct xilinx_spi *xspi;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100394 struct xspi_platform_data *pdata;
Michal Simekad3fdbc2013-07-08 15:29:15 +0200395 struct resource *res;
Michal Simek7b3b7432013-07-09 18:05:16 +0200396 int ret, num_cs = 0, bits_per_word = 8;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100397 struct spi_master *master;
Michal Simek082339b2013-06-04 16:02:36 +0200398 u32 tmp;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100399 u8 i;
John Linnff82c582009-01-09 16:01:53 -0700400
Jingoo Han8074cf02013-07-30 16:58:59 +0900401 pdata = dev_get_platdata(&pdev->dev);
Mark Brownd81c0bb2013-07-03 12:05:42 +0100402 if (pdata) {
403 num_cs = pdata->num_chipselect;
404 bits_per_word = pdata->bits_per_word;
Michal Simekbe3acdf2013-07-08 15:29:17 +0200405 } else {
406 of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
407 &num_cs);
Mark Brownd81c0bb2013-07-03 12:05:42 +0100408 }
Mark Brownd81c0bb2013-07-03 12:05:42 +0100409
410 if (!num_cs) {
Mark Brown7cb2abd2013-07-05 11:24:26 +0100411 dev_err(&pdev->dev,
412 "Missing slave select configuration data\n");
Mark Brownd81c0bb2013-07-03 12:05:42 +0100413 return -EINVAL;
414 }
415
Ricardo Ribaldaeb25f162015-01-28 20:53:39 +0100416 if (num_cs > XILINX_SPI_MAX_CS) {
417 dev_err(&pdev->dev, "Invalid number of spi slaves\n");
418 return -EINVAL;
419 }
420
Mark Brown7cb2abd2013-07-05 11:24:26 +0100421 master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100422 if (!master)
Mark Brownd81c0bb2013-07-03 12:05:42 +0100423 return -ENODEV;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700424
David Brownelle7db06b2009-06-17 16:26:04 -0700425 /* the spi->mode bits understood by this driver: */
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +0100426 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
427 SPI_CS_HIGH;
David Brownelle7db06b2009-06-17 16:26:04 -0700428
Andrei Konovalovae918c02007-07-17 04:04:11 -0700429 xspi = spi_master_get_devdata(master);
Ricardo Ribalda Delgadof9c6ef62015-01-28 13:23:46 +0100430 xspi->cs_inactive = 0xffffffff;
Axel Lin94c69f72013-09-10 15:43:41 +0800431 xspi->bitbang.master = master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700432 xspi->bitbang.chipselect = xilinx_spi_chipselect;
433 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
434 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700435 init_completion(&xspi->done);
436
Michal Simekad3fdbc2013-07-08 15:29:15 +0200437 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
438 xspi->regs = devm_ioremap_resource(&pdev->dev, res);
Mark Brownc40537d2013-07-01 20:33:01 +0100439 if (IS_ERR(xspi->regs)) {
440 ret = PTR_ERR(xspi->regs);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700441 goto put_master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700442 }
443
Lars-Peter Clausen4b153a22014-07-10 10:30:20 +0200444 master->bus_num = pdev->id;
Grant Likely91565c42010-10-14 08:54:55 -0600445 master->num_chipselect = num_cs;
Mark Brown7cb2abd2013-07-05 11:24:26 +0100446 master->dev.of_node = pdev->dev.of_node;
Michal Simek082339b2013-06-04 16:02:36 +0200447
448 /*
449 * Detect endianess on the IP via loop bit in CR. Detection
450 * must be done before reset is sent because incorrect reset
451 * value generates error interrupt.
452 * Setup little endian helper functions first and try to use them
453 * and check if bit was correctly setup or not.
454 */
Mark Brown06352872015-01-30 13:42:00 +0100455 xspi->read_fn = xspi_read32;
456 xspi->write_fn = xspi_write32;
Michal Simek082339b2013-06-04 16:02:36 +0200457
458 xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
459 tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
460 tmp &= XSPI_CR_LOOP;
461 if (tmp != XSPI_CR_LOOP) {
Mark Brown06352872015-01-30 13:42:00 +0100462 xspi->read_fn = xspi_read32_be;
463 xspi->write_fn = xspi_write32_be;
Richard Röjfors86fc5932009-11-13 12:28:49 +0100464 }
Michal Simek082339b2013-06-04 16:02:36 +0200465
Axel Lin9bf46f62014-02-14 21:06:43 +0800466 master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
Ricardo Ribalda Delgado17aaaa82015-01-28 13:23:50 +0100467 xspi->bytes_per_word = bits_per_word / 8;
Ricardo Ribalda Delgado4c9a7612015-01-28 13:23:40 +0100468 xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
469
Michal Simek7b3b7432013-07-09 18:05:16 +0200470 xspi->irq = platform_get_irq(pdev, 0);
Lars-Peter Clausen4db9bf52016-07-15 11:04:18 +0200471 if (xspi->irq < 0 && xspi->irq != -ENXIO) {
472 ret = xspi->irq;
473 goto put_master;
474 } else if (xspi->irq >= 0) {
Ricardo Ribalda Delgado5fe11cc2015-01-28 13:23:44 +0100475 /* Register for SPI Interrupt */
476 ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
477 dev_name(&pdev->dev), xspi);
478 if (ret)
479 goto put_master;
Michal Simek7b3b7432013-07-09 18:05:16 +0200480 }
481
Ricardo Ribalda Delgado5fe11cc2015-01-28 13:23:44 +0100482 /* SPI controller initializations */
483 xspi_init_hw(xspi);
Andrei Konovalovae918c02007-07-17 04:04:11 -0700484
Richard Röjforsd5af91a2009-11-13 12:28:39 +0100485 ret = spi_bitbang_start(&xspi->bitbang);
486 if (ret) {
Mark Brown7cb2abd2013-07-05 11:24:26 +0100487 dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
Michal Simek7b3b7432013-07-09 18:05:16 +0200488 goto put_master;
Andrei Konovalovae918c02007-07-17 04:04:11 -0700489 }
490
Mark Brown7cb2abd2013-07-05 11:24:26 +0100491 dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
Michal Simekad3fdbc2013-07-08 15:29:15 +0200492 (unsigned long long)res->start, xspi->regs, xspi->irq);
Grant Likely8fd88212010-10-14 09:04:29 -0600493
Grant Likelyeae6cb32010-10-14 09:32:53 -0600494 if (pdata) {
495 for (i = 0; i < pdata->num_devices; i++)
496 spi_new_device(master, pdata->devices + i);
497 }
Grant Likely8fd88212010-10-14 09:04:29 -0600498
Mark Brown7cb2abd2013-07-05 11:24:26 +0100499 platform_set_drvdata(pdev, master);
Grant Likely8fd88212010-10-14 09:04:29 -0600500 return 0;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100501
Mark Brownd81c0bb2013-07-03 12:05:42 +0100502put_master:
503 spi_master_put(master);
504
505 return ret;
Grant Likely8fd88212010-10-14 09:04:29 -0600506}
507
Mark Brown7cb2abd2013-07-05 11:24:26 +0100508static int xilinx_spi_remove(struct platform_device *pdev)
Grant Likely8fd88212010-10-14 09:04:29 -0600509{
Mark Brown7cb2abd2013-07-05 11:24:26 +0100510 struct spi_master *master = platform_get_drvdata(pdev);
Mark Brownd81c0bb2013-07-03 12:05:42 +0100511 struct xilinx_spi *xspi = spi_master_get_devdata(master);
Michal Simek7b3b7432013-07-09 18:05:16 +0200512 void __iomem *regs_base = xspi->regs;
Mark Brownd81c0bb2013-07-03 12:05:42 +0100513
514 spi_bitbang_stop(&xspi->bitbang);
Michal Simek7b3b7432013-07-09 18:05:16 +0200515
516 /* Disable all the interrupts just in case */
517 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
518 /* Disable the global IPIF interrupt */
519 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
Mark Brownd81c0bb2013-07-03 12:05:42 +0100520
521 spi_master_put(xspi->bitbang.master);
Grant Likely8fd88212010-10-14 09:04:29 -0600522
523 return 0;
524}
525
526/* work with hotplug and coldplug */
527MODULE_ALIAS("platform:" XILINX_SPI_NAME);
528
529static struct platform_driver xilinx_spi_driver = {
530 .probe = xilinx_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000531 .remove = xilinx_spi_remove,
Grant Likely8fd88212010-10-14 09:04:29 -0600532 .driver = {
533 .name = XILINX_SPI_NAME,
Grant Likelyeae6cb32010-10-14 09:32:53 -0600534 .of_match_table = xilinx_spi_of_match,
Grant Likely8fd88212010-10-14 09:04:29 -0600535 },
536};
Grant Likely940ab882011-10-05 11:29:49 -0600537module_platform_driver(xilinx_spi_driver);
Grant Likely8fd88212010-10-14 09:04:29 -0600538
Andrei Konovalovae918c02007-07-17 04:04:11 -0700539MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
540MODULE_DESCRIPTION("Xilinx SPI driver");
541MODULE_LICENSE("GPL");