Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2019 MediaTek Inc. |
| 4 | * Author: jitao.shi <jitao.shi@mediatek.com> |
| 5 | */ |
| 6 | |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 7 | #include "phy-mtk-io.h" |
Chun-Kuang Hu | 90f80d9 | 2020-10-06 07:37:07 +0800 | [diff] [blame] | 8 | #include "phy-mtk-mipi-dsi.h" |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 9 | |
| 10 | #define MIPITX_LANE_CON 0x000c |
| 11 | #define RG_DSI_CPHY_T1DRV_EN BIT(0) |
| 12 | #define RG_DSI_ANA_CK_SEL BIT(1) |
| 13 | #define RG_DSI_PHY_CK_SEL BIT(2) |
| 14 | #define RG_DSI_CPHY_EN BIT(3) |
| 15 | #define RG_DSI_PHYCK_INV_EN BIT(4) |
| 16 | #define RG_DSI_PWR04_EN BIT(5) |
| 17 | #define RG_DSI_BG_LPF_EN BIT(6) |
| 18 | #define RG_DSI_BG_CORE_EN BIT(7) |
| 19 | #define RG_DSI_PAD_TIEL_SEL BIT(8) |
| 20 | |
Jitao Shi | 3d50b59 | 2020-04-11 15:44:07 +0800 | [diff] [blame] | 21 | #define MIPITX_VOLTAGE_SEL 0x0010 |
Chunfeng Yun | d36d69a | 2022-09-20 17:00:36 +0800 | [diff] [blame] | 22 | #define RG_DSI_HSTX_LDO_REF_SEL GENMASK(9, 6) |
Jitao Shi | 3d50b59 | 2020-04-11 15:44:07 +0800 | [diff] [blame] | 23 | |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 24 | #define MIPITX_PLL_PWR 0x0028 |
| 25 | #define MIPITX_PLL_CON0 0x002c |
| 26 | #define MIPITX_PLL_CON1 0x0030 |
| 27 | #define MIPITX_PLL_CON2 0x0034 |
| 28 | #define MIPITX_PLL_CON3 0x0038 |
| 29 | #define MIPITX_PLL_CON4 0x003c |
Chunfeng Yun | d36d69a | 2022-09-20 17:00:36 +0800 | [diff] [blame] | 30 | #define RG_DSI_PLL_IBIAS GENMASK(11, 10) |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 31 | |
Jitao Shi | 424a3a7 | 2020-04-11 15:44:08 +0800 | [diff] [blame] | 32 | #define MIPITX_D2P_RTCODE 0x0100 |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 33 | #define MIPITX_D2_SW_CTL_EN 0x0144 |
| 34 | #define MIPITX_D0_SW_CTL_EN 0x0244 |
| 35 | #define MIPITX_CK_CKMODE_EN 0x0328 |
| 36 | #define DSI_CK_CKMODE_EN BIT(0) |
| 37 | #define MIPITX_CK_SW_CTL_EN 0x0344 |
| 38 | #define MIPITX_D1_SW_CTL_EN 0x0444 |
| 39 | #define MIPITX_D3_SW_CTL_EN 0x0544 |
| 40 | #define DSI_SW_CTL_EN BIT(0) |
| 41 | #define AD_DSI_PLL_SDM_PWR_ON BIT(0) |
| 42 | #define AD_DSI_PLL_SDM_ISO_EN BIT(1) |
| 43 | |
| 44 | #define RG_DSI_PLL_EN BIT(4) |
Chunfeng Yun | d36d69a | 2022-09-20 17:00:36 +0800 | [diff] [blame] | 45 | #define RG_DSI_PLL_POSDIV GENMASK(10, 8) |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 46 | |
| 47 | static int mtk_mipi_tx_pll_enable(struct clk_hw *hw) |
| 48 | { |
| 49 | struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 50 | void __iomem *base = mipi_tx->regs; |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 51 | unsigned int txdiv, txdiv0; |
| 52 | u64 pcw; |
| 53 | |
| 54 | dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate); |
| 55 | |
| 56 | if (mipi_tx->data_rate >= 2000000000) { |
| 57 | txdiv = 1; |
| 58 | txdiv0 = 0; |
| 59 | } else if (mipi_tx->data_rate >= 1000000000) { |
| 60 | txdiv = 2; |
| 61 | txdiv0 = 1; |
| 62 | } else if (mipi_tx->data_rate >= 500000000) { |
| 63 | txdiv = 4; |
| 64 | txdiv0 = 2; |
| 65 | } else if (mipi_tx->data_rate > 250000000) { |
| 66 | txdiv = 8; |
| 67 | txdiv0 = 3; |
| 68 | } else if (mipi_tx->data_rate >= 125000000) { |
| 69 | txdiv = 16; |
| 70 | txdiv0 = 4; |
| 71 | } else { |
| 72 | return -EINVAL; |
| 73 | } |
| 74 | |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 75 | mtk_phy_clear_bits(base + MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 76 | |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 77 | mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); |
| 78 | mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 79 | udelay(1); |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 80 | mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 81 | pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000); |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 82 | writel(pcw, base + MIPITX_PLL_CON0); |
| 83 | mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0); |
| 84 | mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 85 | |
| 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | static void mtk_mipi_tx_pll_disable(struct clk_hw *hw) |
| 90 | { |
| 91 | struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw); |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 92 | void __iomem *base = mipi_tx->regs; |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 93 | |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 94 | mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 95 | |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 96 | mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); |
| 97 | mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
| 101 | unsigned long *prate) |
| 102 | { |
Michael Walle | 06f76e4 | 2023-11-23 12:02:02 +0100 | [diff] [blame] | 103 | return clamp_val(rate, 125000000, 1600000000); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | static const struct clk_ops mtk_mipi_tx_pll_ops = { |
| 107 | .enable = mtk_mipi_tx_pll_enable, |
| 108 | .disable = mtk_mipi_tx_pll_disable, |
| 109 | .round_rate = mtk_mipi_tx_pll_round_rate, |
| 110 | .set_rate = mtk_mipi_tx_pll_set_rate, |
| 111 | .recalc_rate = mtk_mipi_tx_pll_recalc_rate, |
| 112 | }; |
| 113 | |
Jitao Shi | 424a3a7 | 2020-04-11 15:44:08 +0800 | [diff] [blame] | 114 | static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) |
| 115 | { |
| 116 | int i, j; |
| 117 | |
| 118 | for (i = 0; i < 5; i++) { |
| 119 | if ((mipi_tx->rt_code[i] & 0x1f) == 0) |
| 120 | mipi_tx->rt_code[i] |= 0x10; |
| 121 | |
| 122 | if ((mipi_tx->rt_code[i] >> 5 & 0x1f) == 0) |
| 123 | mipi_tx->rt_code[i] |= 0x10 << 5; |
| 124 | |
| 125 | for (j = 0; j < 10; j++) |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 126 | mtk_phy_update_bits(mipi_tx->regs + |
Jitao Shi | 424a3a7 | 2020-04-11 15:44:08 +0800 | [diff] [blame] | 127 | MIPITX_D2P_RTCODE * (i + 1) + j * 4, |
| 128 | 1, mipi_tx->rt_code[i] >> j & 1); |
| 129 | } |
| 130 | } |
| 131 | |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 132 | static void mtk_mipi_tx_power_on_signal(struct phy *phy) |
| 133 | { |
| 134 | struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 135 | void __iomem *base = mipi_tx->regs; |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 136 | |
| 137 | /* BG_LPF_EN / BG_CORE_EN */ |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 138 | writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 139 | usleep_range(30, 100); |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 140 | writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN, base + MIPITX_LANE_CON); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 141 | |
| 142 | /* Switch OFF each Lane */ |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 143 | mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); |
| 144 | mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); |
| 145 | mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); |
| 146 | mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); |
| 147 | mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 148 | |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 149 | mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL, |
| 150 | (mipi_tx->mipitx_drive - 3000) / 200); |
Jitao Shi | 3d50b59 | 2020-04-11 15:44:07 +0800 | [diff] [blame] | 151 | |
Jitao Shi | 424a3a7 | 2020-04-11 15:44:08 +0800 | [diff] [blame] | 152 | mtk_mipi_tx_config_calibration_data(mipi_tx); |
| 153 | |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 154 | mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | static void mtk_mipi_tx_power_off_signal(struct phy *phy) |
| 158 | { |
| 159 | struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 160 | void __iomem *base = mipi_tx->regs; |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 161 | |
| 162 | /* Switch ON each Lane */ |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 163 | mtk_phy_set_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); |
| 164 | mtk_phy_set_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); |
| 165 | mtk_phy_set_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); |
| 166 | mtk_phy_set_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); |
| 167 | mtk_phy_set_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 168 | |
Chunfeng Yun | 5f88a93 | 2022-09-20 17:00:37 +0800 | [diff] [blame] | 169 | writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON); |
| 170 | writel(RG_DSI_PAD_TIEL_SEL, base + MIPITX_LANE_CON); |
Jitao Shi | efda51a | 2019-08-07 16:46:45 +0800 | [diff] [blame] | 171 | } |
| 172 | |
| 173 | const struct mtk_mipitx_data mt8183_mipitx_data = { |
| 174 | .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops, |
| 175 | .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal, |
| 176 | .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal, |
| 177 | }; |