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Jitao Shiefda51a2019-08-07 16:46:45 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: jitao.shi <jitao.shi@mediatek.com>
5 */
6
Chunfeng Yun5f88a932022-09-20 17:00:37 +08007#include "phy-mtk-io.h"
Chun-Kuang Hu90f80d92020-10-06 07:37:07 +08008#include "phy-mtk-mipi-dsi.h"
Jitao Shiefda51a2019-08-07 16:46:45 +08009
10#define MIPITX_LANE_CON 0x000c
11#define RG_DSI_CPHY_T1DRV_EN BIT(0)
12#define RG_DSI_ANA_CK_SEL BIT(1)
13#define RG_DSI_PHY_CK_SEL BIT(2)
14#define RG_DSI_CPHY_EN BIT(3)
15#define RG_DSI_PHYCK_INV_EN BIT(4)
16#define RG_DSI_PWR04_EN BIT(5)
17#define RG_DSI_BG_LPF_EN BIT(6)
18#define RG_DSI_BG_CORE_EN BIT(7)
19#define RG_DSI_PAD_TIEL_SEL BIT(8)
20
Jitao Shi3d50b592020-04-11 15:44:07 +080021#define MIPITX_VOLTAGE_SEL 0x0010
Chunfeng Yund36d69a2022-09-20 17:00:36 +080022#define RG_DSI_HSTX_LDO_REF_SEL GENMASK(9, 6)
Jitao Shi3d50b592020-04-11 15:44:07 +080023
Jitao Shiefda51a2019-08-07 16:46:45 +080024#define MIPITX_PLL_PWR 0x0028
25#define MIPITX_PLL_CON0 0x002c
26#define MIPITX_PLL_CON1 0x0030
27#define MIPITX_PLL_CON2 0x0034
28#define MIPITX_PLL_CON3 0x0038
29#define MIPITX_PLL_CON4 0x003c
Chunfeng Yund36d69a2022-09-20 17:00:36 +080030#define RG_DSI_PLL_IBIAS GENMASK(11, 10)
Jitao Shiefda51a2019-08-07 16:46:45 +080031
Jitao Shi424a3a72020-04-11 15:44:08 +080032#define MIPITX_D2P_RTCODE 0x0100
Jitao Shiefda51a2019-08-07 16:46:45 +080033#define MIPITX_D2_SW_CTL_EN 0x0144
34#define MIPITX_D0_SW_CTL_EN 0x0244
35#define MIPITX_CK_CKMODE_EN 0x0328
36#define DSI_CK_CKMODE_EN BIT(0)
37#define MIPITX_CK_SW_CTL_EN 0x0344
38#define MIPITX_D1_SW_CTL_EN 0x0444
39#define MIPITX_D3_SW_CTL_EN 0x0544
40#define DSI_SW_CTL_EN BIT(0)
41#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
42#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
43
44#define RG_DSI_PLL_EN BIT(4)
Chunfeng Yund36d69a2022-09-20 17:00:36 +080045#define RG_DSI_PLL_POSDIV GENMASK(10, 8)
Jitao Shiefda51a2019-08-07 16:46:45 +080046
47static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
48{
49 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
Chunfeng Yun5f88a932022-09-20 17:00:37 +080050 void __iomem *base = mipi_tx->regs;
Jitao Shiefda51a2019-08-07 16:46:45 +080051 unsigned int txdiv, txdiv0;
52 u64 pcw;
53
54 dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate);
55
56 if (mipi_tx->data_rate >= 2000000000) {
57 txdiv = 1;
58 txdiv0 = 0;
59 } else if (mipi_tx->data_rate >= 1000000000) {
60 txdiv = 2;
61 txdiv0 = 1;
62 } else if (mipi_tx->data_rate >= 500000000) {
63 txdiv = 4;
64 txdiv0 = 2;
65 } else if (mipi_tx->data_rate > 250000000) {
66 txdiv = 8;
67 txdiv0 = 3;
68 } else if (mipi_tx->data_rate >= 125000000) {
69 txdiv = 16;
70 txdiv0 = 4;
71 } else {
72 return -EINVAL;
73 }
74
Chunfeng Yun5f88a932022-09-20 17:00:37 +080075 mtk_phy_clear_bits(base + MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
Jitao Shiefda51a2019-08-07 16:46:45 +080076
Chunfeng Yun5f88a932022-09-20 17:00:37 +080077 mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
78 mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
Jitao Shiefda51a2019-08-07 16:46:45 +080079 udelay(1);
Chunfeng Yun5f88a932022-09-20 17:00:37 +080080 mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
Jitao Shiefda51a2019-08-07 16:46:45 +080081 pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000);
Chunfeng Yun5f88a932022-09-20 17:00:37 +080082 writel(pcw, base + MIPITX_PLL_CON0);
83 mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0);
84 mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
Jitao Shiefda51a2019-08-07 16:46:45 +080085
86 return 0;
87}
88
89static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
90{
91 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
Chunfeng Yun5f88a932022-09-20 17:00:37 +080092 void __iomem *base = mipi_tx->regs;
Jitao Shiefda51a2019-08-07 16:46:45 +080093
Chunfeng Yun5f88a932022-09-20 17:00:37 +080094 mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
Jitao Shiefda51a2019-08-07 16:46:45 +080095
Chunfeng Yun5f88a932022-09-20 17:00:37 +080096 mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
97 mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
Jitao Shiefda51a2019-08-07 16:46:45 +080098}
99
100static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
101 unsigned long *prate)
102{
Michael Walle06f76e42023-11-23 12:02:02 +0100103 return clamp_val(rate, 125000000, 1600000000);
Jitao Shiefda51a2019-08-07 16:46:45 +0800104}
105
106static const struct clk_ops mtk_mipi_tx_pll_ops = {
107 .enable = mtk_mipi_tx_pll_enable,
108 .disable = mtk_mipi_tx_pll_disable,
109 .round_rate = mtk_mipi_tx_pll_round_rate,
110 .set_rate = mtk_mipi_tx_pll_set_rate,
111 .recalc_rate = mtk_mipi_tx_pll_recalc_rate,
112};
113
Jitao Shi424a3a72020-04-11 15:44:08 +0800114static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
115{
116 int i, j;
117
118 for (i = 0; i < 5; i++) {
119 if ((mipi_tx->rt_code[i] & 0x1f) == 0)
120 mipi_tx->rt_code[i] |= 0x10;
121
122 if ((mipi_tx->rt_code[i] >> 5 & 0x1f) == 0)
123 mipi_tx->rt_code[i] |= 0x10 << 5;
124
125 for (j = 0; j < 10; j++)
Chunfeng Yun5f88a932022-09-20 17:00:37 +0800126 mtk_phy_update_bits(mipi_tx->regs +
Jitao Shi424a3a72020-04-11 15:44:08 +0800127 MIPITX_D2P_RTCODE * (i + 1) + j * 4,
128 1, mipi_tx->rt_code[i] >> j & 1);
129 }
130}
131
Jitao Shiefda51a2019-08-07 16:46:45 +0800132static void mtk_mipi_tx_power_on_signal(struct phy *phy)
133{
134 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
Chunfeng Yun5f88a932022-09-20 17:00:37 +0800135 void __iomem *base = mipi_tx->regs;
Jitao Shiefda51a2019-08-07 16:46:45 +0800136
137 /* BG_LPF_EN / BG_CORE_EN */
Chunfeng Yun5f88a932022-09-20 17:00:37 +0800138 writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
Jitao Shiefda51a2019-08-07 16:46:45 +0800139 usleep_range(30, 100);
Chunfeng Yun5f88a932022-09-20 17:00:37 +0800140 writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN, base + MIPITX_LANE_CON);
Jitao Shiefda51a2019-08-07 16:46:45 +0800141
142 /* Switch OFF each Lane */
Chunfeng Yun5f88a932022-09-20 17:00:37 +0800143 mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
144 mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
145 mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
146 mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
147 mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
Jitao Shiefda51a2019-08-07 16:46:45 +0800148
Chunfeng Yun5f88a932022-09-20 17:00:37 +0800149 mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL,
150 (mipi_tx->mipitx_drive - 3000) / 200);
Jitao Shi3d50b592020-04-11 15:44:07 +0800151
Jitao Shi424a3a72020-04-11 15:44:08 +0800152 mtk_mipi_tx_config_calibration_data(mipi_tx);
153
Chunfeng Yun5f88a932022-09-20 17:00:37 +0800154 mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
Jitao Shiefda51a2019-08-07 16:46:45 +0800155}
156
157static void mtk_mipi_tx_power_off_signal(struct phy *phy)
158{
159 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
Chunfeng Yun5f88a932022-09-20 17:00:37 +0800160 void __iomem *base = mipi_tx->regs;
Jitao Shiefda51a2019-08-07 16:46:45 +0800161
162 /* Switch ON each Lane */
Chunfeng Yun5f88a932022-09-20 17:00:37 +0800163 mtk_phy_set_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
164 mtk_phy_set_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
165 mtk_phy_set_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
166 mtk_phy_set_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
167 mtk_phy_set_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
Jitao Shiefda51a2019-08-07 16:46:45 +0800168
Chunfeng Yun5f88a932022-09-20 17:00:37 +0800169 writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
170 writel(RG_DSI_PAD_TIEL_SEL, base + MIPITX_LANE_CON);
Jitao Shiefda51a2019-08-07 16:46:45 +0800171}
172
173const struct mtk_mipitx_data mt8183_mipitx_data = {
174 .mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
175 .mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
176 .mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
177};