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Thomas Gleixnercaab2772019-06-03 07:44:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Marc Zyngier712c6ff2012-10-19 17:46:27 +01002/*
3 * Hypervisor stub
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Marc Zyngier <marc.zyngier@arm.com>
Marc Zyngier712c6ff2012-10-19 17:46:27 +01007 */
8
9#include <linux/init.h>
10#include <linux/linkage.h>
Marc Zyngier712c6ff2012-10-19 17:46:27 +010011
12#include <asm/assembler.h>
Marc Zyngierf3591822021-02-08 09:57:13 +000013#include <asm/el2_setup.h>
Geoff Levandad72e592016-04-27 17:47:03 +010014#include <asm/kvm_arm.h>
James Morsec94b0cf2016-04-27 17:47:04 +010015#include <asm/kvm_asm.h>
Marc Zyngier712c6ff2012-10-19 17:46:27 +010016#include <asm/ptrace.h>
17#include <asm/virt.h>
18
Marc Zyngierfa8aa592022-06-30 17:04:55 +010019// Warning, hardcoded register allocation
Marc Zyngier6ab76612022-06-30 17:04:57 +010020// This will clobber x1 and x2, and expect x1 to contain
21// the id register value as read from the HW
22.macro __check_override idreg, fld, width, pass, fail
23 ubfx x1, x1, #\fld, #\width
Marc Zyngierfa8aa592022-06-30 17:04:55 +010024 cbz x1, \fail
25
26 adr_l x1, \idreg\()_override
27 ldr x2, [x1, FTR_OVR_VAL_OFFSET]
28 ldr x1, [x1, FTR_OVR_MASK_OFFSET]
Marc Zyngier6ab76612022-06-30 17:04:57 +010029 ubfx x2, x2, #\fld, #\width
30 ubfx x1, x1, #\fld, #\width
Marc Zyngierfa8aa592022-06-30 17:04:55 +010031 cmp x1, xzr
32 and x2, x2, x1
33 csinv x2, x2, xzr, ne
34 cbnz x2, \pass
35 b \fail
36.endm
37
Marc Zyngier6ab76612022-06-30 17:04:57 +010038.macro check_override idreg, fld, pass, fail
39 mrs x1, \idreg\()_el1
40 __check_override \idreg \fld 4 \pass \fail
41.endm
42
Marc Zyngier712c6ff2012-10-19 17:46:27 +010043 .text
James Morse8fac5cb2019-01-24 16:32:56 +000044 .pushsection .hyp.text, "ax"
45
Marc Zyngier712c6ff2012-10-19 17:46:27 +010046 .align 11
47
Mark Brown0343a7e2020-05-01 12:54:29 +010048SYM_CODE_START(__hyp_stub_vectors)
Marc Zyngier712c6ff2012-10-19 17:46:27 +010049 ventry el2_sync_invalid // Synchronous EL2t
50 ventry el2_irq_invalid // IRQ EL2t
51 ventry el2_fiq_invalid // FIQ EL2t
52 ventry el2_error_invalid // Error EL2t
53
Marc Zyngier31a32b42021-04-08 14:10:09 +010054 ventry elx_sync // Synchronous EL2h
Marc Zyngier712c6ff2012-10-19 17:46:27 +010055 ventry el2_irq_invalid // IRQ EL2h
56 ventry el2_fiq_invalid // FIQ EL2h
57 ventry el2_error_invalid // Error EL2h
58
Marc Zyngier31a32b42021-04-08 14:10:09 +010059 ventry elx_sync // Synchronous 64-bit EL1
Marc Zyngier712c6ff2012-10-19 17:46:27 +010060 ventry el1_irq_invalid // IRQ 64-bit EL1
61 ventry el1_fiq_invalid // FIQ 64-bit EL1
62 ventry el1_error_invalid // Error 64-bit EL1
63
64 ventry el1_sync_invalid // Synchronous 32-bit EL1
65 ventry el1_irq_invalid // IRQ 32-bit EL1
66 ventry el1_fiq_invalid // FIQ 32-bit EL1
67 ventry el1_error_invalid // Error 32-bit EL1
Mark Brown0343a7e2020-05-01 12:54:29 +010068SYM_CODE_END(__hyp_stub_vectors)
Marc Zyngier712c6ff2012-10-19 17:46:27 +010069
70 .align 11
71
Marc Zyngier31a32b42021-04-08 14:10:09 +010072SYM_CODE_START_LOCAL(elx_sync)
Marc Zyngier0b51c542017-04-03 19:38:04 +010073 cmp x0, #HVC_SET_VECTORS
Marc Zyngierf3591822021-02-08 09:57:13 +000074 b.ne 1f
Geoff Levandad72e592016-04-27 17:47:03 +010075 msr vbar_el2, x1
76 b 9f
77
Marc Zyngier7ddb0c3d2022-06-30 17:04:52 +0100781: cmp x0, #HVC_FINALISE_EL2
79 b.eq __finalise_el2
Marc Zyngierf3591822021-02-08 09:57:13 +000080
Geoff Levandf9076ec2016-06-23 17:54:48 +0000812: cmp x0, #HVC_SOFT_RESTART
82 b.ne 3f
83 mov x0, x2
84 mov x2, x4
85 mov x4, x1
86 mov x1, x3
87 br x4 // no return
88
Marc Zyngierfd0e0c62017-04-03 19:37:39 +0100893: cmp x0, #HVC_RESET_VECTORS
90 beq 9f // Nothing to reset!
91
James Morsec94b0cf2016-04-27 17:47:04 +010092 /* Someone called kvm_call_hyp() against the hyp-stub... */
Remi Denis-Courmontdc374b42020-03-04 11:36:31 +020093 mov_q x0, HVC_STUB_ERR
Marc Zyngieraf42f202017-04-03 19:38:05 +010094 eret
Geoff Levandad72e592016-04-27 17:47:03 +010095
Marc Zyngieraf42f202017-04-03 19:38:05 +0100969: mov x0, xzr
97 eret
Marc Zyngier31a32b42021-04-08 14:10:09 +010098SYM_CODE_END(elx_sync)
Marc Zyngier712c6ff2012-10-19 17:46:27 +010099
Marc Zyngier7ddb0c3d2022-06-30 17:04:52 +0100100SYM_CODE_START_LOCAL(__finalise_el2)
Mark Brown55adc082022-09-05 23:54:03 +0100101 check_override id_aa64pfr0 ID_AA64PFR0_EL1_SVE_SHIFT .Linit_sve .Lskip_sve
Marc Zyngier504ee232022-06-30 17:04:59 +0100102
103.Linit_sve: /* SVE register access */
104 mrs x0, cptr_el2 // Disable SVE traps
105 bic x0, x0, #CPTR_EL2_TZ
106 msr cptr_el2, x0
107 isb
108 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
109 msr_s SYS_ZCR_EL2, x1 // length for EL1.
110
111.Lskip_sve:
Mark Brown6ca2b9c2022-09-05 23:54:04 +0100112 check_override id_aa64pfr1 ID_AA64PFR1_EL1_SME_SHIFT .Linit_sme .Lskip_sme
Marc Zyngierb3000e22022-06-30 17:04:58 +0100113
114.Linit_sme: /* SME register access and priority mapping */
115 mrs x0, cptr_el2 // Disable SME traps
116 bic x0, x0, #CPTR_EL2_TSM
117 msr cptr_el2, x0
118 isb
119
120 mrs x1, sctlr_el2
121 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
122 msr sctlr_el2, x1
123 isb
124
Marc Zyngier18c9aa42022-06-30 17:05:00 +0100125 mov x0, #0 // SMCR controls
Marc Zyngierb3000e22022-06-30 17:04:58 +0100126
Marc Zyngier18c9aa42022-06-30 17:05:00 +0100127 // Full FP in SM?
128 mrs_s x1, SYS_ID_AA64SMFR0_EL1
Will Deaconf96d67a2022-07-25 10:59:15 +0100129 __check_override id_aa64smfr0 ID_AA64SMFR0_EL1_FA64_SHIFT 1 .Linit_sme_fa64 .Lskip_sme_fa64
Marc Zyngierb3000e22022-06-30 17:04:58 +0100130
Marc Zyngier18c9aa42022-06-30 17:05:00 +0100131.Linit_sme_fa64:
132 orr x0, x0, SMCR_ELx_FA64_MASK
Marc Zyngierb3000e22022-06-30 17:04:58 +0100133.Lskip_sme_fa64:
134
Marc Zyngier18c9aa42022-06-30 17:05:00 +0100135 orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector
136 msr_s SYS_SMCR_EL2, x0 // length for EL1.
Marc Zyngierb3000e22022-06-30 17:04:58 +0100137
138 mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported?
139 ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1
140 cbz x1, .Lskip_sme
141
142 msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal
143
144 mrs x1, id_aa64mmfr1_el1 // HCRX_EL2 present?
Kristina Martsenko6fcd0192022-09-05 23:54:07 +0100145 ubfx x1, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4
Marc Zyngierb3000e22022-06-30 17:04:58 +0100146 cbz x1, .Lskip_sme
147
148 mrs_s x1, SYS_HCRX_EL2
149 orr x1, x1, #HCRX_EL2_SMPME_MASK // Enable priority mapping
150 msr_s SYS_HCRX_EL2, x1
151
152.Lskip_sme:
153
Marc Zyngier7ddb0c3d2022-06-30 17:04:52 +0100154 // nVHE? No way! Give me the real thing!
Marc Zyngierf3591822021-02-08 09:57:13 +0000155 // Sanity check: MMU *must* be off
156 mrs x1, sctlr_el2
157 tbnz x1, #0, 1f
158
159 // Needs to be VHE capable, obviously
Kristina Martsenko6fcd0192022-09-05 23:54:07 +0100160 check_override id_aa64mmfr1 ID_AA64MMFR1_EL1_VH_SHIFT 2f 1f
Marc Zyngier41fac422021-02-08 09:57:24 +0000161
Marc Zyngierf1b6cff2021-02-24 09:37:36 +00001621: mov_q x0, HVC_STUB_ERR
163 eret
1642:
Marc Zyngierf3591822021-02-08 09:57:13 +0000165 // Engage the VHE magic!
166 mov_q x0, HCR_HOST_VHE_FLAGS
167 msr hcr_el2, x0
168 isb
169
Marc Zyngierf3591822021-02-08 09:57:13 +0000170 // Use the EL1 allocated stack, per-cpu offset
171 mrs x0, sp_el1
172 mov sp, x0
173 mrs x0, tpidr_el1
174 msr tpidr_el2, x0
175
176 // FP configuration, vectors
177 mrs_s x0, SYS_CPACR_EL12
178 msr cpacr_el1, x0
179 mrs_s x0, SYS_VBAR_EL12
180 msr vbar_el1, x0
181
Suzuki K Poulosea1319262021-04-05 17:42:54 +0100182 // Use EL2 translations for SPE & TRBE and disable access from EL1
Marc Zyngier19e87e12021-02-08 09:57:16 +0000183 mrs x0, mdcr_el2
184 bic x0, x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
Suzuki K Poulosea1319262021-04-05 17:42:54 +0100185 bic x0, x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT)
Marc Zyngier19e87e12021-02-08 09:57:16 +0000186 msr mdcr_el2, x0
187
Marc Zyngierf3591822021-02-08 09:57:13 +0000188 // Transfer the MM state from EL1 to EL2
189 mrs_s x0, SYS_TCR_EL12
190 msr tcr_el1, x0
191 mrs_s x0, SYS_TTBR0_EL12
192 msr ttbr0_el1, x0
193 mrs_s x0, SYS_TTBR1_EL12
194 msr ttbr1_el1, x0
195 mrs_s x0, SYS_MAIR_EL12
196 msr mair_el1, x0
197 isb
198
Marc Zyngierf1b6cff2021-02-24 09:37:36 +0000199 // Hack the exception return to stay at EL2
200 mrs x0, spsr_el1
201 and x0, x0, #~PSR_MODE_MASK
202 mov x1, #PSR_MODE_EL2h
203 orr x0, x0, x1
204 msr spsr_el1, x0
205
206 b enter_vhe
Marc Zyngier7ddb0c3d2022-06-30 17:04:52 +0100207SYM_CODE_END(__finalise_el2)
Marc Zyngierf1b6cff2021-02-24 09:37:36 +0000208
209 // At the point where we reach enter_vhe(), we run with
Marc Zyngier7ddb0c3d2022-06-30 17:04:52 +0100210 // the MMU off (which is enforced by __finalise_el2()).
Marc Zyngierf1b6cff2021-02-24 09:37:36 +0000211 // We thus need to be in the idmap, or everything will
212 // explode when enabling the MMU.
213
214 .pushsection .idmap.text, "ax"
215
216SYM_CODE_START_LOCAL(enter_vhe)
Marc Zyngierf3591822021-02-08 09:57:13 +0000217 // Invalidate TLBs before enabling the MMU
218 tlbi vmalle1
219 dsb nsh
Marc Zyngier430251c2021-02-24 09:37:38 +0000220 isb
Marc Zyngierf3591822021-02-08 09:57:13 +0000221
222 // Enable the EL2 S1 MMU, as set up from EL1
223 mrs_s x0, SYS_SCTLR_EL12
224 set_sctlr_el1 x0
225
226 // Disable the EL1 S1 MMU for a good measure
227 mov_q x0, INIT_SCTLR_EL1_MMU_OFF
228 msr_s SYS_SCTLR_EL12, x0
229
Marc Zyngierf3591822021-02-08 09:57:13 +0000230 mov x0, xzr
231
Marc Zyngierf1b6cff2021-02-24 09:37:36 +0000232 eret
233SYM_CODE_END(enter_vhe)
234
235 .popsection
Marc Zyngierf3591822021-02-08 09:57:13 +0000236
Marc Zyngier712c6ff2012-10-19 17:46:27 +0100237.macro invalid_vector label
Mark Brown0343a7e2020-05-01 12:54:29 +0100238SYM_CODE_START_LOCAL(\label)
Marc Zyngier712c6ff2012-10-19 17:46:27 +0100239 b \label
Mark Brown0343a7e2020-05-01 12:54:29 +0100240SYM_CODE_END(\label)
Marc Zyngier712c6ff2012-10-19 17:46:27 +0100241.endm
242
243 invalid_vector el2_sync_invalid
244 invalid_vector el2_irq_invalid
245 invalid_vector el2_fiq_invalid
246 invalid_vector el2_error_invalid
247 invalid_vector el1_sync_invalid
248 invalid_vector el1_irq_invalid
249 invalid_vector el1_fiq_invalid
250 invalid_vector el1_error_invalid
251
Quentin Perrete30be142021-01-28 17:38:50 +0000252 .popsection
253
Marc Zyngier712c6ff2012-10-19 17:46:27 +0100254/*
255 * __hyp_set_vectors: Call this after boot to set the initial hypervisor
256 * vectors as part of hypervisor installation. On an SMP system, this should
257 * be called on each CPU.
258 *
259 * x0 must be the physical address of the new vector table, and must be
260 * 2KB aligned.
261 *
262 * Before calling this, you must check that the stub hypervisor is installed
263 * everywhere, by waiting for any secondary CPUs to be brought up and then
264 * checking that is_hyp_mode_available() is true.
265 *
266 * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
267 * something else went wrong... in such cases, trying to install a new
268 * hypervisor is unlikely to work as desired.
269 *
270 * When you call into your shiny new hypervisor, sp_el2 will contain junk,
271 * so you will need to set that to something sensible at the new hypervisor's
272 * initialisation entry point.
273 */
274
Mark Brown0343a7e2020-05-01 12:54:29 +0100275SYM_FUNC_START(__hyp_set_vectors)
Geoff Levandad72e592016-04-27 17:47:03 +0100276 mov x1, x0
277 mov x0, #HVC_SET_VECTORS
James Morse00a44cd2016-04-27 17:47:02 +0100278 hvc #0
James Morse00a44cd2016-04-27 17:47:02 +0100279 ret
Mark Brown0343a7e2020-05-01 12:54:29 +0100280SYM_FUNC_END(__hyp_set_vectors)
Marc Zyngierfd0e0c62017-04-03 19:37:39 +0100281
Mark Brown0343a7e2020-05-01 12:54:29 +0100282SYM_FUNC_START(__hyp_reset_vectors)
Marc Zyngierfd0e0c62017-04-03 19:37:39 +0100283 mov x0, #HVC_RESET_VECTORS
284 hvc #0
285 ret
Mark Brown0343a7e2020-05-01 12:54:29 +0100286SYM_FUNC_END(__hyp_reset_vectors)
Marc Zyngier0c93df962021-02-08 09:57:14 +0000287
288/*
Marc Zyngier7ddb0c3d2022-06-30 17:04:52 +0100289 * Entry point to finalise EL2 and switch to VHE if deemed capable
Ard Biesheuvel005e1262022-06-24 17:06:48 +0200290 *
291 * w0: boot mode, as returned by init_kernel_el()
Marc Zyngier0c93df962021-02-08 09:57:14 +0000292 */
Marc Zyngier7ddb0c3d2022-06-30 17:04:52 +0100293SYM_FUNC_START(finalise_el2)
Marc Zyngier0c93df962021-02-08 09:57:14 +0000294 // Need to have booted at EL2
Marc Zyngier0c93df962021-02-08 09:57:14 +0000295 cmp w0, #BOOT_CPU_MODE_EL2
296 b.ne 1f
297
298 // and still be at EL1
299 mrs x0, CurrentEL
300 cmp x0, #CurrentEL_EL1
301 b.ne 1f
302
Marc Zyngier7ddb0c3d2022-06-30 17:04:52 +0100303 mov x0, #HVC_FINALISE_EL2
Marc Zyngier0c93df962021-02-08 09:57:14 +0000304 hvc #0
3051:
Marc Zyngier0c93df962021-02-08 09:57:14 +0000306 ret
Marc Zyngier7ddb0c3d2022-06-30 17:04:52 +0100307SYM_FUNC_END(finalise_el2)