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Gregory CLEMENT009f1312012-08-02 11:16:29 +03001/*
2 * Coherency fabric: low level functions
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 *
12 * This file implements the assembly function to add a CPU to the
13 * coherency fabric. This function is called by each of the secondary
14 * CPUs during their early boot in an SMP kernel, this why this
15 * function have to callable from assembly. It can also be called by a
16 * primary CPU from C code during its boot.
17 */
18
19#include <linux/linkage.h>
20#define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0
21#define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4
22
Ben Dooksbca028e2013-02-01 10:36:22 +000023#include <asm/assembler.h>
Gregory CLEMENTccd6a132014-04-14 17:10:05 +020024#include <asm/cp15.h>
Ben Dooksbca028e2013-02-01 10:36:22 +000025
Gregory CLEMENT009f1312012-08-02 11:16:29 +030026 .text
Thomas Petazzoni30cdef92014-11-13 10:38:56 +010027/*
28 * Returns the coherency base address in r1 (r0 is untouched), or 0 if
29 * the coherency fabric is not enabled.
30 */
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +020031ENTRY(ll_get_coherency_base)
Gregory CLEMENTccd6a132014-04-14 17:10:05 +020032 mrc p15, 0, r1, c1, c0, 0
33 tst r1, #CR_M @ Check MMU bit enabled
34 bne 1f
35
Thomas Petazzoni4dd1b7f2014-05-22 14:48:01 +020036 /*
37 * MMU is disabled, use the physical address of the coherency
Thomas Petazzoni30cdef92014-11-13 10:38:56 +010038 * base address. However, if the coherency fabric isn't mapped
39 * (i.e its virtual address is zero), it means coherency is
40 * not enabled, so we return 0.
Thomas Petazzoni4dd1b7f2014-05-22 14:48:01 +020041 */
Thomas Petazzoni30cdef92014-11-13 10:38:56 +010042 ldr r1, =coherency_base
43 cmp r1, #0
44 beq 2f
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +020045 adr r1, 3f
46 ldr r3, [r1]
47 ldr r1, [r1, r3]
Gregory CLEMENTccd6a132014-04-14 17:10:05 +020048 b 2f
491:
Thomas Petazzoni4dd1b7f2014-05-22 14:48:01 +020050 /*
51 * MMU is enabled, use the virtual address of the coherency
52 * base address.
53 */
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +020054 ldr r1, =coherency_base
55 ldr r1, [r1]
Gregory CLEMENTccd6a132014-04-14 17:10:05 +0200562:
Russell King6ebbf2c2014-06-30 16:29:12 +010057 ret lr
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +020058ENDPROC(ll_get_coherency_base)
59
Thomas Petazzoni07ae1442014-05-22 14:48:02 +020060/*
61 * Returns the coherency CPU mask in r3 (r0 is untouched). This
62 * coherency CPU mask can be used with the coherency fabric
63 * configuration and control registers. Note that the mask is already
64 * endian-swapped as appropriate so that the calling functions do not
65 * have to care about endianness issues while accessing the coherency
66 * fabric registers
67 */
68ENTRY(ll_get_coherency_cpumask)
Stefan Agner969ad772019-04-11 09:54:03 +020069 mrc p15, 0, r3, cr0, cr0, 5
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +020070 and r3, r3, #15
Gregory CLEMENTb41375f2014-04-14 17:10:06 +020071 mov r2, #(1 << 24)
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +020072 lsl r3, r2, r3
Thomas Petazzoni4fbe6392014-05-22 14:47:59 +020073ARM_BE8(rev r3, r3)
Russell King6ebbf2c2014-06-30 16:29:12 +010074 ret lr
Thomas Petazzoni07ae1442014-05-22 14:48:02 +020075ENDPROC(ll_get_coherency_cpumask)
Gregory CLEMENT009f1312012-08-02 11:16:29 +030076
Thomas Petazzoni4dd1b7f2014-05-22 14:48:01 +020077/*
78 * ll_add_cpu_to_smp_group(), ll_enable_coherency() and
79 * ll_disable_coherency() use the strex/ldrex instructions while the
80 * MMU can be disabled. The Armada XP SoC has an exclusive monitor
81 * that tracks transactions to Device and/or SO memory and thanks to
82 * that, exclusive transactions are functional even when the MMU is
83 * disabled.
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +020084 */
85
86ENTRY(ll_add_cpu_to_smp_group)
87 /*
Thomas Petazzoni4dd1b7f2014-05-22 14:48:01 +020088 * As r0 is not modified by ll_get_coherency_base() and
Thomas Petazzoni07ae1442014-05-22 14:48:02 +020089 * ll_get_coherency_cpumask(), we use it to temporarly save lr
90 * and avoid it being modified by the branch and link
91 * calls. This function is used very early in the secondary
92 * CPU boot, and no stack is available at this point.
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +020093 */
Thomas Petazzoni90ba76f2014-05-22 14:48:00 +020094 mov r0, lr
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +020095 bl ll_get_coherency_base
Thomas Petazzoni30cdef92014-11-13 10:38:56 +010096 /* Bail out if the coherency is not enabled */
97 cmp r1, #0
98 reteq r0
Thomas Petazzoni07ae1442014-05-22 14:48:02 +020099 bl ll_get_coherency_cpumask
Thomas Petazzoni90ba76f2014-05-22 14:48:00 +0200100 mov lr, r0
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +0200101 add r0, r1, #ARMADA_XP_CFB_CFG_REG_OFFSET
Nadav Haklaib60b61d2013-05-23 10:54:02 +02001021:
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +0200103 ldrex r2, [r0]
104 orr r2, r2, r3
105 strex r1, r2, [r0]
106 cmp r1, #0
107 bne 1b
Russell King6ebbf2c2014-06-30 16:29:12 +0100108 ret lr
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +0200109ENDPROC(ll_add_cpu_to_smp_group)
Gregory CLEMENT009f1312012-08-02 11:16:29 +0300110
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +0200111ENTRY(ll_enable_coherency)
112 /*
Thomas Petazzoni4dd1b7f2014-05-22 14:48:01 +0200113 * As r0 is not modified by ll_get_coherency_base() and
Thomas Petazzoni07ae1442014-05-22 14:48:02 +0200114 * ll_get_coherency_cpumask(), we use it to temporarly save lr
115 * and avoid it being modified by the branch and link
116 * calls. This function is used very early in the secondary
117 * CPU boot, and no stack is available at this point.
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +0200118 */
119 mov r0, lr
120 bl ll_get_coherency_base
Thomas Petazzoni30cdef92014-11-13 10:38:56 +0100121 /* Bail out if the coherency is not enabled */
122 cmp r1, #0
123 reteq r0
Thomas Petazzoni07ae1442014-05-22 14:48:02 +0200124 bl ll_get_coherency_cpumask
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +0200125 mov lr, r0
126 add r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
Nadav Haklaib60b61d2013-05-23 10:54:02 +02001271:
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +0200128 ldrex r2, [r0]
129 orr r2, r2, r3
130 strex r1, r2, [r0]
131 cmp r1, #0
132 bne 1b
Gregory CLEMENT009f1312012-08-02 11:16:29 +0300133 dsb
Gregory CLEMENT009f1312012-08-02 11:16:29 +0300134 mov r0, #0
Russell King6ebbf2c2014-06-30 16:29:12 +0100135 ret lr
Gregory CLEMENT2e8a5942014-04-14 17:10:08 +0200136ENDPROC(ll_enable_coherency)
137
Gregory CLEMENT1a6bfbc2014-04-14 17:10:09 +0200138ENTRY(ll_disable_coherency)
139 /*
Thomas Petazzoni4dd1b7f2014-05-22 14:48:01 +0200140 * As r0 is not modified by ll_get_coherency_base() and
Thomas Petazzoni07ae1442014-05-22 14:48:02 +0200141 * ll_get_coherency_cpumask(), we use it to temporarly save lr
142 * and avoid it being modified by the branch and link
143 * calls. This function is used very early in the secondary
144 * CPU boot, and no stack is available at this point.
Gregory CLEMENT1a6bfbc2014-04-14 17:10:09 +0200145 */
Thomas Petazzoni90ba76f2014-05-22 14:48:00 +0200146 mov r0, lr
Gregory CLEMENT1a6bfbc2014-04-14 17:10:09 +0200147 bl ll_get_coherency_base
Thomas Petazzoni30cdef92014-11-13 10:38:56 +0100148 /* Bail out if the coherency is not enabled */
149 cmp r1, #0
150 reteq r0
Thomas Petazzoni07ae1442014-05-22 14:48:02 +0200151 bl ll_get_coherency_cpumask
Thomas Petazzoni90ba76f2014-05-22 14:48:00 +0200152 mov lr, r0
Gregory CLEMENT1a6bfbc2014-04-14 17:10:09 +0200153 add r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
1541:
155 ldrex r2, [r0]
156 bic r2, r2, r3
157 strex r1, r2, [r0]
158 cmp r1, #0
159 bne 1b
160 dsb
Russell King6ebbf2c2014-06-30 16:29:12 +0100161 ret lr
Gregory CLEMENT1a6bfbc2014-04-14 17:10:09 +0200162ENDPROC(ll_disable_coherency)
Gregory CLEMENTccd6a132014-04-14 17:10:05 +0200163
164 .align 2
1653:
166 .long coherency_phys_base - .