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| <a name="ARC-Directives"></a> |
| <p> |
| Next: <a rel="next" accesskey="n" href="ARC-Modifiers.html#ARC-Modifiers">ARC Modifiers</a>, |
| Previous: <a rel="previous" accesskey="p" href="ARC-Syntax.html#ARC-Syntax">ARC Syntax</a>, |
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| |
| <h4 class="subsection">9.3.3 ARC Machine Directives</h4> |
| |
| <p><a name="index-machine-directives_002c-ARC-704"></a><a name="index-ARC-machine-directives-705"></a>The ARC version of <code>as</code> supports the following additional |
| machine directives: |
| |
| |
| <a name="index-g_t_0040code_007blcomm_007d-directive-706"></a> |
| <dl><dt><code>.lcomm </code><var>symbol</var><code>, </code><var>length</var><code>[, </code><var>alignment</var><code>]</code><dd>Reserve <var>length</var> (an absolute expression) bytes for a local common |
| denoted by <var>symbol</var>. The section and value of <var>symbol</var> are |
| those of the new local common. The addresses are allocated in the bss |
| section, so that at run-time the bytes start off zeroed. Since |
| <var>symbol</var> is not declared global, it is normally not visible to |
| <code>ld</code>. The optional third parameter, <var>alignment</var>, |
| specifies the desired alignment of the symbol in the bss section, |
| specified as a byte boundary (for example, an alignment of 16 means |
| that the least significant 4 bits of the address should be zero). The |
| alignment must be an absolute expression, and it must be a power of |
| two. If no alignment is specified, as will set the alignment to the |
| largest power of two less than or equal to the size of the symbol, up |
| to a maximum of 16. |
| |
| <p><a name="index-g_t_0040code_007blcommon_007d-directive_002c-ARC-707"></a><br><dt><code>.lcommon </code><var>symbol</var><code>, </code><var>length</var><code>[, </code><var>alignment</var><code>]</code><dd>The same as <code>lcomm</code> directive. |
| |
| <p><a name="index-g_t_0040code_007bcpu_007d-directive_002c-ARC-708"></a><br><dt><code>.cpu </code><var>cpu</var><dd>The <code>.cpu</code> directive must be followed by the desired core |
| version. Permitted values for CPU are: |
| <dl> |
| <dt><code>ARC600</code><dd>Assemble for the ARC600 instruction set. |
| |
| <br><dt><code>arc600_norm</code><dd>Assemble for ARC 600 with norm instructions. |
| |
| <br><dt><code>arc600_mul64</code><dd>Assemble for ARC 600 with mul64 instructions. |
| |
| <br><dt><code>arc600_mul32x16</code><dd>Assemble for ARC 600 with mul32x16 instructions. |
| |
| <br><dt><code>arc601</code><dd>Assemble for ARC 601 instruction set. |
| |
| <br><dt><code>arc601_norm</code><dd>Assemble for ARC 601 with norm instructions. |
| |
| <br><dt><code>arc601_mul64</code><dd>Assemble for ARC 601 with mul64 instructions. |
| |
| <br><dt><code>arc601_mul32x16</code><dd>Assemble for ARC 601 with mul32x16 instructions. |
| |
| <br><dt><code>ARC700</code><dd>Assemble for the ARC700 instruction set. |
| |
| <br><dt><code>NPS400</code><dd>Assemble for the NPS400 instruction set. |
| |
| <br><dt><code>EM</code><dd>Assemble for the ARC EM instruction set. |
| |
| <br><dt><code>arcem</code><dd>Assemble for ARC EM instruction set |
| |
| <br><dt><code>em4</code><dd>Assemble for ARC EM with code-density instructions. |
| |
| <br><dt><code>em4_dmips</code><dd>Assemble for ARC EM with code-density instructions. |
| |
| <br><dt><code>em4_fpus</code><dd>Assemble for ARC EM with code-density instructions. |
| |
| <br><dt><code>em4_fpuda</code><dd>Assemble for ARC EM with code-density, and double-precision assist |
| instructions. |
| |
| <br><dt><code>quarkse_em</code><dd>Assemble for QuarkSE-EM instruction set. |
| |
| <br><dt><code>HS</code><dd>Assemble for the ARC HS instruction set. |
| |
| <br><dt><code>archs</code><dd>Assemble for ARC HS instruction set. |
| |
| <br><dt><code>hs</code><dd>Assemble for ARC HS instruction set. |
| |
| <br><dt><code>hs34</code><dd>Assemble for ARC HS34 instruction set. |
| |
| <br><dt><code>hs38</code><dd>Assemble for ARC HS38 instruction set. |
| |
| <br><dt><code>hs38_linux</code><dd>Assemble for ARC HS38 with floating point support on. |
| |
| </dl> |
| |
| <p>Note: the <code>.cpu</code> directive overrides the command-line option |
| <code>-mcpu=</code><var>cpu</var>; a warning is emitted when the version is not |
| consistent between the two. |
| |
| <br><dt><code>.extAuxRegister </code><var>name</var><code>, </code><var>addr</var><code>, </code><var>mode</var><dd><a name="index-g_t_0040code_007bextAuxRegister_007d-directive_002c-ARC-709"></a>Auxiliary registers can be defined in the assembler source code by |
| using this directive. The first parameter, <var>name</var>, is the name of the |
| new auxiliary register. The second parameter, <var>addr</var>, is |
| address the of the auxiliary register. The third parameter, |
| <var>mode</var>, specifies whether the register is readable and/or writable |
| and is one of: |
| <dl> |
| <dt><code>r</code><dd>Read only; |
| |
| <br><dt><code>w</code><dd>Write only; |
| |
| <br><dt><code>r|w</code><dd>Read and write. |
| |
| </dl> |
| |
| <p>For example: |
| <pre class="example"> .extAuxRegister mulhi, 0x12, w |
| </pre> |
| <p>specifies a write only extension auxiliary register, <var>mulhi</var> at |
| address 0x12. |
| |
| <br><dt><code>.extCondCode </code><var>suffix</var><code>, </code><var>val</var><dd><a name="index-g_t_0040code_007bextCondCode_007d-directive_002c-ARC-710"></a>ARC supports extensible condition codes. This directive defines a new |
| condition code, to be known by the suffix, <var>suffix</var> and will |
| depend on the value, <var>val</var> in the condition code. |
| |
| <p>For example: |
| <pre class="example"> .extCondCode is_busy,0x14 |
| add.is_busy r1,r2,r3 |
| </pre> |
| <p>will only execute the <code>add</code> instruction if the condition code |
| value is 0x14. |
| |
| <br><dt><code>.extCoreRegister </code><var>name</var><code>, </code><var>regnum</var><code>, </code><var>mode</var><code>, </code><var>shortcut</var><dd><a name="index-g_t_0040code_007bextCoreRegister_007d-directive_002c-ARC-711"></a>Specifies an extension core register named <var>name</var> as a synonym for |
| the register numbered <var>regnum</var>. The register number must be |
| between 32 and 59. The third argument, <var>mode</var>, indicates whether |
| the register is readable and/or writable and is one of: |
| <dl> |
| <dt><code>r</code><dd>Read only; |
| |
| <br><dt><code>w</code><dd>Write only; |
| |
| <br><dt><code>r|w</code><dd>Read and write. |
| |
| </dl> |
| |
| <p>The final parameter, <var>shortcut</var> indicates whether the register has |
| a short cut in the pipeline. The valid values are: |
| <dl> |
| <dt><code>can_shortcut</code><dd>The register has a short cut in the pipeline; |
| |
| <br><dt><code>cannot_shortcut</code><dd>The register does not have a short cut in the pipeline. |
| </dl> |
| |
| <p>For example: |
| <pre class="example"> .extCoreRegister mlo, 57, r , can_shortcut |
| </pre> |
| <p>defines a read only extension core register, <code>mlo</code>, which is |
| register 57, and can short cut the pipeline. |
| |
| <br><dt><code>.extInstruction </code><var>name</var><code>, </code><var>opcode</var><code>, </code><var>subopcode</var><code>, </code><var>suffixclass</var><code>, </code><var>syntaxclass</var><dd><a name="index-g_t_0040code_007bextInstruction_007d-directive_002c-ARC-712"></a>ARC allows the user to specify extension instructions. These |
| extension instructions are not macros; the assembler creates encodings |
| for use of these instructions according to the specification by the |
| user. |
| |
| <p>The first argument, <var>name</var>, gives the name of the instruction. |
| |
| <p>The second argument, <var>opcode</var>, is the opcode to be used (bits 31:27 |
| in the encoding). |
| |
| <p>The third argument, <var>subopcode</var>, is the sub-opcode to be used, but |
| the correct value also depends on the fifth argument, |
| <var>syntaxclass</var> |
| |
| <p>The fourth argument, <var>suffixclass</var>, determines the kinds of |
| suffixes to be allowed. Valid values are: |
| <dl> |
| <dt><code>SUFFIX_NONE</code><dd>No suffixes are permitted; |
| |
| <br><dt><code>SUFFIX_COND</code><dd>Conditional suffixes are permitted; |
| |
| <br><dt><code>SUFFIX_FLAG</code><dd>Flag setting suffixes are permitted. |
| |
| <br><dt><code>SUFFIX_COND|SUFFIX_FLAG</code><dd>Both conditional and flag setting suffices are permitted. |
| |
| </dl> |
| |
| <p>The fifth and final argument, <var>syntaxclass</var>, determines the syntax |
| class for the instruction. It can have the following values: |
| <dl> |
| <dt><code>SYNTAX_2OP</code><dd>Two Operand Instruction; |
| |
| <br><dt><code>SYNTAX_3OP</code><dd>Three Operand Instruction. |
| |
| <br><dt><code>SYNTAX_1OP</code><dd>One Operand Instruction. |
| |
| <br><dt><code>SYNTAX_NOP</code><dd>No Operand Instruction. |
| </dl> |
| |
| <p>The syntax class may be followed by ‘<samp><span class="samp">|</span></samp>’ and one of the following |
| modifiers. |
| <dl> |
| <dt><code>OP1_MUST_BE_IMM</code><dd>Modifies syntax class <code>SYNTAX_3OP</code>, specifying that the first |
| operand of a three-operand instruction must be an immediate (i.e., the |
| result is discarded). This is usually used to set the flags using |
| specific instructions and not retain results. |
| |
| <br><dt><code>OP1_IMM_IMPLIED</code><dd>Modifies syntax class <code>SYNTAX_20P</code>, specifying that there is an |
| implied immediate destination operand which does not appear in the |
| syntax. |
| |
| <p>For example, if the source code contains an instruction like: |
| <pre class="example"> inst r1,r2 |
| </pre> |
| <p>the first argument is an implied immediate (that is, the result is |
| discarded). This is the same as though the source code were: inst |
| 0,r1,r2. |
| |
| </dl> |
| |
| <p>For example, defining a 64-bit multiplier with immediate operands: |
| <pre class="example"> .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG, |
| SYNTAX_3OP|OP1_MUST_BE_IMM |
| </pre> |
| <p>which specifies an extension instruction named <code>mp64</code> with 3 |
| operands. It sets the flags and can be used with a condition code, |
| for which the first operand is an immediate, i.e. equivalent to |
| discarding the result of the operation. |
| |
| <p>A two operands instruction variant would be: |
| <pre class="example"> .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND, |
| SYNTAX_2OP|OP1_IMM_IMPLIED |
| </pre> |
| <p>which describes a two operand instruction with an implicit first |
| immediate operand. The result of this operation would be discarded. |
| |
| <p><a name="index-g_t_0040code_007b_002earc_005fattribute_007d-directive_002c-ARC-713"></a><br><dt><code>.arc_attribute </code><var>tag</var><code>, </code><var>value</var><dd>Set the ARC object attribute <var>tag</var> to <var>value</var>. |
| |
| <p>The <var>tag</var> is either an attribute number, or one of the following: |
| <code>Tag_ARC_PCS_config</code>, <code>Tag_ARC_CPU_base</code>, |
| <code>Tag_ARC_CPU_variation</code>, <code>Tag_ARC_CPU_name</code>, |
| <code>Tag_ARC_ABI_rf16</code>, <code>Tag_ARC_ABI_osver</code>, <code>Tag_ARC_ABI_sda</code>, |
| <code>Tag_ARC_ABI_pic</code>, <code>Tag_ARC_ABI_tls</code>, <code>Tag_ARC_ABI_enumsize</code>, |
| <code>Tag_ARC_ABI_exceptions</code>, <code>Tag_ARC_ABI_double_size</code>, |
| <code>Tag_ARC_ISA_config</code>, <code>Tag_ARC_ISA_apex</code>, |
| <code>Tag_ARC_ISA_mpy_option</code> |
| |
| <p>The <var>value</var> is either a <code>number</code>, <code>"string"</code>, or |
| <code>number, "string"</code> depending on the tag. |
| |
| </dl> |
| |
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| |
