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| <h4 class="subsection">9.6.2 Syntax</h4> |
| |
| <p><a name="index-Blackfin-syntax-850"></a><a name="index-syntax_002c-Blackfin-851"></a> |
| <dl> |
| <dt><code>Special Characters</code><dd>Assembler input is free format and may appear anywhere on the line. |
| One instruction may extend across multiple lines or more than one |
| instruction may appear on the same line. White space (space, tab, |
| comments or newline) may appear anywhere between tokens. A token must |
| not have embedded spaces. Tokens include numbers, register names, |
| keywords, user identifiers, and also some multicharacter special |
| symbols like "+=", "/*" or "||". |
| |
| <p>Comments are introduced by the ‘<samp><span class="samp">#</span></samp>’ character and extend to the |
| end of the current line. If the ‘<samp><span class="samp">#</span></samp>’ appears as the first |
| character of a line, the whole line is treated as a comment, but in |
| this case the line can also be a logical line number directive |
| (see <a href="Comments.html#Comments">Comments</a>) or a preprocessor control command |
| (see <a href="Preprocessing.html#Preprocessing">Preprocessing</a>). |
| |
| <br><dt><code>Instruction Delimiting</code><dd>A semicolon must terminate every instruction. Sometimes a complete |
| instruction will consist of more than one operation. There are two |
| cases where this occurs. The first is when two general operations |
| are combined. Normally a comma separates the different parts, as in |
| |
| <pre class="smallexample"> a0= r3.h * r2.l, a1 = r3.l * r2.h ; |
| </pre> |
| <p>The second case occurs when a general instruction is combined with one |
| or two memory references for joint issue. The latter portions are |
| set off by a "||" token. |
| |
| <pre class="smallexample"> a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; |
| </pre> |
| <p>Multiple instructions can occur on the same line. Each must be |
| terminated by a semicolon character. |
| |
| <br><dt><code>Register Names</code><dd> |
| The assembler treats register names and instruction keywords in a case |
| insensitive manner. User identifiers are case sensitive. Thus, R3.l, |
| R3.L, r3.l and r3.L are all equivalent input to the assembler. |
| |
| <p>Register names are reserved and may not be used as program identifiers. |
| |
| <p>Some operations (such as "Move Register") require a register pair. |
| Register pairs are always data registers and are denoted using a colon, |
| eg., R3:2. The larger number must be written firsts. Note that the |
| hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0. |
| |
| <p>Some instructions (such as –SP (Push Multiple)) require a group of |
| adjacent registers. Adjacent registers are denoted in the syntax by |
| the range enclosed in parentheses and separated by a colon, eg., (R7:3). |
| Again, the larger number appears first. |
| |
| <p>Portions of a particular register may be individually specified. This |
| is written with a dot (".") following the register name and then a |
| letter denoting the desired portion. For 32-bit registers, ".H" |
| denotes the most significant ("High") portion. ".L" denotes the |
| least-significant portion. The subdivisions of the 40-bit registers |
| are described later. |
| |
| <br><dt><code>Accumulators</code><dd>The set of 40-bit registers A1 and A0 that normally contain data that |
| is being manipulated. Each accumulator can be accessed in four ways. |
| |
| <dl> |
| <dt><code>one 40-bit register</code><dd>The register will be referred to as A1 or A0. |
| <br><dt><code>one 32-bit register</code><dd>The registers are designated as A1.W or A0.W. |
| <br><dt><code>two 16-bit registers</code><dd>The registers are designated as A1.H, A1.L, A0.H or A0.L. |
| <br><dt><code>one 8-bit register</code><dd>The registers are designated as A1.X or A0.X for the bits that |
| extend beyond bit 31. |
| </dl> |
| |
| <br><dt><code>Data Registers</code><dd>The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that |
| normally contain data for manipulation. These are abbreviated as |
| D-register or Dreg. Data registers can be accessed as 32-bit registers |
| or as two independent 16-bit registers. The least significant 16 bits |
| of each register is called the "low" half and is designated with ".L" |
| following the register name. The most significant 16 bits are called |
| the "high" half and is designated with ".H" following the name. |
| |
| <pre class="smallexample"> R7.L, r2.h, r4.L, R0.H |
| </pre> |
| <br><dt><code>Pointer Registers</code><dd>The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that |
| normally contain byte addresses of data structures. These are |
| abbreviated as P-register or Preg. |
| |
| <pre class="smallexample"> p2, p5, fp, sp |
| </pre> |
| <br><dt><code>Stack Pointer SP</code><dd>The stack pointer contains the 32-bit address of the last occupied |
| byte location in the stack. The stack grows by decrementing the |
| stack pointer. |
| |
| <br><dt><code>Frame Pointer FP</code><dd>The frame pointer contains the 32-bit address of the previous frame |
| pointer in the stack. It is located at the top of a frame. |
| |
| <br><dt><code>Loop Top</code><dd>LT0 and LT1. These registers contain the 32-bit address of the top of |
| a zero overhead loop. |
| |
| <br><dt><code>Loop Count</code><dd>LC0 and LC1. These registers contain the 32-bit counter of the zero |
| overhead loop executions. |
| |
| <br><dt><code>Loop Bottom</code><dd>LB0 and LB1. These registers contain the 32-bit address of the bottom |
| of a zero overhead loop. |
| |
| <br><dt><code>Index Registers</code><dd>The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte |
| addresses of data structures. Abbreviated I-register or Ireg. |
| |
| <br><dt><code>Modify Registers</code><dd>The set of 32-bit registers (M0, M1, M2, M3) that normally contain |
| offset values that are added and subtracted to one of the index |
| registers. Abbreviated as Mreg. |
| |
| <br><dt><code>Length Registers</code><dd>The set of 32-bit registers (L0, L1, L2, L3) that normally contain the |
| length in bytes of the circular buffer. Abbreviated as Lreg. Clear |
| the Lreg to disable circular addressing for the corresponding Ireg. |
| |
| <br><dt><code>Base Registers</code><dd>The set of 32-bit registers (B0, B1, B2, B3) that normally contain the |
| base address in bytes of the circular buffer. Abbreviated as Breg. |
| |
| <br><dt><code>Floating Point</code><dd>The Blackfin family has no hardware floating point but the .float |
| directive generates ieee floating point numbers for use with software |
| floating point libraries. |
| |
| <br><dt><code>Blackfin Opcodes</code><dd>For detailed information on the Blackfin machine instruction set, see |
| the Blackfin Processor Instruction Set Reference. |
| |
| </dl> |
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