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| <h4 class="subsection">9.36.1 Options</h4> |
| |
| <p><a name="index-options-for-PowerPC-1947"></a><a name="index-PowerPC-options-1948"></a><a name="index-architectures_002c-PowerPC-1949"></a><a name="index-PowerPC-architectures-1950"></a>The PowerPC chip family includes several successive levels, using the same |
| core instruction set, but including a few additional instructions at |
| each level. There are exceptions to this however. For details on what |
| instructions each variant supports, please see the chip's architecture |
| reference manual. |
| |
| <p>The following table lists all available PowerPC options. |
| |
| <!-- man begin OPTIONS --> |
| <dl> |
| <dt><code>-a32</code><dd>Generate ELF32 or XCOFF32. |
| |
| <br><dt><code>-a64</code><dd>Generate ELF64 or XCOFF64. |
| |
| <br><dt><code>-K PIC</code><dd>Set EF_PPC_RELOCATABLE_LIB in ELF flags. |
| |
| <br><dt><code>-mpwrx | -mpwr2</code><dd>Generate code for POWER/2 (RIOS2). |
| |
| <br><dt><code>-mpwr</code><dd>Generate code for POWER (RIOS1) |
| |
| <br><dt><code>-m601</code><dd>Generate code for PowerPC 601. |
| |
| <br><dt><code>-mppc, -mppc32, -m603, -m604</code><dd>Generate code for PowerPC 603/604. |
| |
| <br><dt><code>-m403, -m405</code><dd>Generate code for PowerPC 403/405. |
| |
| <br><dt><code>-m440</code><dd>Generate code for PowerPC 440. BookE and some 405 instructions. |
| |
| <br><dt><code>-m464</code><dd>Generate code for PowerPC 464. |
| |
| <br><dt><code>-m476</code><dd>Generate code for PowerPC 476. |
| |
| <br><dt><code>-m7400, -m7410, -m7450, -m7455</code><dd>Generate code for PowerPC 7400/7410/7450/7455. |
| |
| <br><dt><code>-m750cl, -mgekko, -mbroadway</code><dd>Generate code for PowerPC 750CL/Gekko/Broadway. |
| |
| <br><dt><code>-m821, -m850, -m860</code><dd>Generate code for PowerPC 821/850/860. |
| |
| <br><dt><code>-mppc64, -m620</code><dd>Generate code for PowerPC 620/625/630. |
| |
| <br><dt><code>-me500, -me500x2</code><dd>Generate code for Motorola e500 core complex. |
| |
| <br><dt><code>-me500mc</code><dd>Generate code for Freescale e500mc core complex. |
| |
| <br><dt><code>-me500mc64</code><dd>Generate code for Freescale e500mc64 core complex. |
| |
| <br><dt><code>-me5500</code><dd>Generate code for Freescale e5500 core complex. |
| |
| <br><dt><code>-me6500</code><dd>Generate code for Freescale e6500 core complex. |
| |
| <br><dt><code>-mspe</code><dd>Generate code for Motorola SPE instructions. |
| |
| <br><dt><code>-mspe2</code><dd>Generate code for Freescale SPE2 instructions. |
| |
| <br><dt><code>-mtitan</code><dd>Generate code for AppliedMicro Titan core complex. |
| |
| <br><dt><code>-mppc64bridge</code><dd>Generate code for PowerPC 64, including bridge insns. |
| |
| <br><dt><code>-mbooke</code><dd>Generate code for 32-bit BookE. |
| |
| <br><dt><code>-ma2</code><dd>Generate code for A2 architecture. |
| |
| <br><dt><code>-me300</code><dd>Generate code for PowerPC e300 family. |
| |
| <br><dt><code>-maltivec</code><dd>Generate code for processors with AltiVec instructions. |
| |
| <br><dt><code>-mvle</code><dd>Generate code for Freescale PowerPC VLE instructions. |
| |
| <br><dt><code>-mvsx</code><dd>Generate code for processors with Vector-Scalar (VSX) instructions. |
| |
| <br><dt><code>-mhtm</code><dd>Generate code for processors with Hardware Transactional Memory instructions. |
| |
| <br><dt><code>-mpower4, -mpwr4</code><dd>Generate code for Power4 architecture. |
| |
| <br><dt><code>-mpower5, -mpwr5, -mpwr5x</code><dd>Generate code for Power5 architecture. |
| |
| <br><dt><code>-mpower6, -mpwr6</code><dd>Generate code for Power6 architecture. |
| |
| <br><dt><code>-mpower7, -mpwr7</code><dd>Generate code for Power7 architecture. |
| |
| <br><dt><code>-mpower8, -mpwr8</code><dd>Generate code for Power8 architecture. |
| |
| <br><dt><code>-mpower9, -mpwr9</code><dd>Generate code for Power9 architecture. |
| |
| <br><dt><code>-mcell</code><br><dt><code>-mcell</code><dd>Generate code for Cell Broadband Engine architecture. |
| |
| <br><dt><code>-mcom</code><dd>Generate code Power/PowerPC common instructions. |
| |
| <br><dt><code>-many</code><dd>Generate code for any architecture (PWR/PWRX/PPC). |
| |
| <br><dt><code>-mregnames</code><dd>Allow symbolic names for registers. |
| |
| <br><dt><code>-mno-regnames</code><dd>Do not allow symbolic names for registers. |
| |
| <br><dt><code>-mrelocatable</code><dd>Support for GCC's -mrelocatable option. |
| |
| <br><dt><code>-mrelocatable-lib</code><dd>Support for GCC's -mrelocatable-lib option. |
| |
| <br><dt><code>-memb</code><dd>Set PPC_EMB bit in ELF flags. |
| |
| <br><dt><code>-mlittle, -mlittle-endian, -le</code><dd>Generate code for a little endian machine. |
| |
| <br><dt><code>-mbig, -mbig-endian, -be</code><dd>Generate code for a big endian machine. |
| |
| <br><dt><code>-msolaris</code><dd>Generate code for Solaris. |
| |
| <br><dt><code>-mno-solaris</code><dd>Do not generate code for Solaris. |
| |
| <br><dt><code>-nops=</code><var>count</var><dd>If an alignment directive inserts more than <var>count</var> nops, put a |
| branch at the beginning to skip execution of the nops. |
| </dl> |
| <!-- man end --> |
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