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| |
| <h4 class="subsection">9.44.1 Options</h4> |
| |
| <p><a name="index-options-for-SPARC-2139"></a><a name="index-SPARC-options-2140"></a><a name="index-architectures_002c-SPARC-2141"></a><a name="index-SPARC-architectures-2142"></a>The SPARC chip family includes several successive versions, using the same |
| core instruction set, but including a few additional instructions at |
| each version. There are exceptions to this however. For details on what |
| instructions each variant supports, please see the chip's architecture |
| reference manual. |
| |
| <p>By default, <code>as</code> assumes the core instruction set (SPARC |
| v6), but “bumps” the architecture level as needed: it switches to |
| successively higher architectures as it encounters instructions that |
| only exist in the higher levels. |
| |
| <p>If not configured for SPARC v9 (<code>sparc64-*-*</code>) GAS will not bump |
| past sparclite by default, an option must be passed to enable the |
| v9 instructions. |
| |
| <p>GAS treats sparclite as being compatible with v8, unless an architecture |
| is explicitly requested. SPARC v9 is always incompatible with sparclite. |
| |
| <!-- The order here is the same as the order of enum sparc_opcode_arch_val --> |
| <!-- to give the user a sense of the order of the "bumping". --> |
| |
| <a name="index-g_t_002dAv6-2143"></a> |
| <a name="index-g_t_002dAv7-2144"></a> |
| <a name="index-g_t_002dAv8-2145"></a> |
| <a name="index-g_t_002dAleon-2146"></a> |
| <a name="index-g_t_002dAsparclet-2147"></a> |
| <a name="index-g_t_002dAsparclite-2148"></a> |
| <a name="index-g_t_002dAv9-2149"></a> |
| <a name="index-g_t_002dAv9a-2150"></a> |
| <a name="index-g_t_002dAv9b-2151"></a> |
| <a name="index-g_t_002dAv9c-2152"></a> |
| <a name="index-g_t_002dAv9d-2153"></a> |
| <a name="index-g_t_002dAv9e-2154"></a> |
| <a name="index-g_t_002dAv9v-2155"></a> |
| <a name="index-g_t_002dAv9m-2156"></a> |
| <a name="index-g_t_002dAsparc-2157"></a> |
| <a name="index-g_t_002dAsparcvis-2158"></a> |
| <a name="index-g_t_002dAsparcvis2-2159"></a> |
| <a name="index-g_t_002dAsparcfmaf-2160"></a> |
| <a name="index-g_t_002dAsparcima-2161"></a> |
| <a name="index-g_t_002dAsparcvis3-2162"></a> |
| <a name="index-g_t_002dAsparcvis3r-2163"></a> |
| <dl><dt><code>-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite</code><dt><code>-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd |</code><dt><code>-Av8plusv | -Av8plusm | -Av8plusm8</code><dt><code>-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m | -Av9m8</code><dt><code>-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima</code><dt><code>-Asparcvis3 | -Asparcvis3r | -Asparc5 | -Asparc6</code><dd>Use one of the ‘<samp><span class="samp">-A</span></samp>’ options to select one of the SPARC |
| architectures explicitly. If you select an architecture explicitly, |
| <code>as</code> reports a fatal error if it encounters an instruction |
| or feature requiring an incompatible or higher level. |
| |
| <p>‘<samp><span class="samp">-Av8plus</span></samp>’, ‘<samp><span class="samp">-Av8plusa</span></samp>’, ‘<samp><span class="samp">-Av8plusb</span></samp>’, ‘<samp><span class="samp">-Av8plusc</span></samp>’, |
| ‘<samp><span class="samp">-Av8plusd</span></samp>’, and ‘<samp><span class="samp">-Av8plusv</span></samp>’ select a 32 bit environment. |
| |
| <p>‘<samp><span class="samp">-Av9</span></samp>’, ‘<samp><span class="samp">-Av9a</span></samp>’, ‘<samp><span class="samp">-Av9b</span></samp>’, ‘<samp><span class="samp">-Av9c</span></samp>’, ‘<samp><span class="samp">-Av9d</span></samp>’, |
| ‘<samp><span class="samp">-Av9e</span></samp>’, ‘<samp><span class="samp">-Av9v</span></samp>’ and ‘<samp><span class="samp">-Av9m</span></samp>’ select a 64 bit |
| environment and are not available unless GAS is explicitly configured |
| with 64 bit environment support. |
| |
| <p>‘<samp><span class="samp">-Av8plusa</span></samp>’ and ‘<samp><span class="samp">-Av9a</span></samp>’ enable the SPARC V9 instruction set with |
| UltraSPARC VIS 1.0 extensions. |
| |
| <p>‘<samp><span class="samp">-Av8plusb</span></samp>’ and ‘<samp><span class="samp">-Av9b</span></samp>’ enable the UltraSPARC VIS 2.0 instructions, |
| as well as the instructions enabled by ‘<samp><span class="samp">-Av8plusa</span></samp>’ and ‘<samp><span class="samp">-Av9a</span></samp>’. |
| |
| <p>‘<samp><span class="samp">-Av8plusc</span></samp>’ and ‘<samp><span class="samp">-Av9c</span></samp>’ enable the UltraSPARC Niagara instructions, |
| as well as the instructions enabled by ‘<samp><span class="samp">-Av8plusb</span></samp>’ and ‘<samp><span class="samp">-Av9b</span></samp>’. |
| |
| <p>‘<samp><span class="samp">-Av8plusd</span></samp>’ and ‘<samp><span class="samp">-Av9d</span></samp>’ enable the floating point fused |
| multiply-add, VIS 3.0, and HPC extension instructions, as well as the |
| instructions enabled by ‘<samp><span class="samp">-Av8plusc</span></samp>’ and ‘<samp><span class="samp">-Av9c</span></samp>’. |
| |
| <p>‘<samp><span class="samp">-Av8pluse</span></samp>’ and ‘<samp><span class="samp">-Av9e</span></samp>’ enable the cryptographic |
| instructions, as well as the instructions enabled by ‘<samp><span class="samp">-Av8plusd</span></samp>’ |
| and ‘<samp><span class="samp">-Av9d</span></samp>’. |
| |
| <p>‘<samp><span class="samp">-Av8plusv</span></samp>’ and ‘<samp><span class="samp">-Av9v</span></samp>’ enable floating point unfused |
| multiply-add, and integer multiply-add, as well as the instructions |
| enabled by ‘<samp><span class="samp">-Av8pluse</span></samp>’ and ‘<samp><span class="samp">-Av9e</span></samp>’. |
| |
| <p>‘<samp><span class="samp">-Av8plusm</span></samp>’ and ‘<samp><span class="samp">-Av9m</span></samp>’ enable the VIS 4.0, subtract extended, |
| xmpmul, xmontmul and xmontsqr instructions, as well as the instructions |
| enabled by ‘<samp><span class="samp">-Av8plusv</span></samp>’ and ‘<samp><span class="samp">-Av9v</span></samp>’. |
| |
| <p>‘<samp><span class="samp">-Av8plusm8</span></samp>’ and ‘<samp><span class="samp">-Av9m8</span></samp>’ enable the instructions introduced |
| in the Oracle SPARC Architecture 2017 and the M8 processor, as |
| well as the instructions enabled by ‘<samp><span class="samp">-Av8plusm</span></samp>’ and ‘<samp><span class="samp">-Av9m</span></samp>’. |
| |
| <p>‘<samp><span class="samp">-Asparc</span></samp>’ specifies a v9 environment. It is equivalent to |
| ‘<samp><span class="samp">-Av9</span></samp>’ if the word size is 64-bit, and ‘<samp><span class="samp">-Av8plus</span></samp>’ otherwise. |
| |
| <p>‘<samp><span class="samp">-Asparcvis</span></samp>’ specifies a v9a environment. It is equivalent to |
| ‘<samp><span class="samp">-Av9a</span></samp>’ if the word size is 64-bit, and ‘<samp><span class="samp">-Av8plusa</span></samp>’ otherwise. |
| |
| <p>‘<samp><span class="samp">-Asparcvis2</span></samp>’ specifies a v9b environment. It is equivalent to |
| ‘<samp><span class="samp">-Av9b</span></samp>’ if the word size is 64-bit, and ‘<samp><span class="samp">-Av8plusb</span></samp>’ otherwise. |
| |
| <p>‘<samp><span class="samp">-Asparcfmaf</span></samp>’ specifies a v9b environment with the floating point |
| fused multiply-add instructions enabled. |
| |
| <p>‘<samp><span class="samp">-Asparcima</span></samp>’ specifies a v9b environment with the integer |
| multiply-add instructions enabled. |
| |
| <p>‘<samp><span class="samp">-Asparcvis3</span></samp>’ specifies a v9b environment with the VIS 3.0, |
| HPC , and floating point fused multiply-add instructions enabled. |
| |
| <p>‘<samp><span class="samp">-Asparcvis3r</span></samp>’ specifies a v9b environment with the VIS 3.0, HPC, |
| and floating point unfused multiply-add instructions enabled. |
| |
| <p>‘<samp><span class="samp">-Asparc5</span></samp>’ is equivalent to ‘<samp><span class="samp">-Av9m</span></samp>’. |
| |
| <p>‘<samp><span class="samp">-Asparc6</span></samp>’ is equivalent to ‘<samp><span class="samp">-Av9m8</span></samp>’. |
| |
| <br><dt><code>-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc</code><dt><code>-xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm |</code><dt><code>-xarch=v8plusm8 | -xarch=v9 | -xarch=v9a | -xarch=v9b</code><dt><code>-xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v</code><dt><code>-xarch=v9m | -xarch=v9m8</code><dt><code>-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2</code><dt><code>-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3</code><dt><code>-xarch=sparcvis3r | -xarch=sparc5 | -xarch=sparc6</code><dd>For compatibility with the SunOS v9 assembler. These options are |
| equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, |
| -Av8plusv, -Av8plusm, -Av8plusm8, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, |
| -Av9e, -Av9v, -Av9m, -Av9m8, -Asparc, -Asparcvis, -Asparcvis2, |
| -Asparcfmaf, -Asparcima, -Asparcvis3, -Asparcvis3r, -Asparc5 and |
| -Asparc6 respectively. |
| |
| <br><dt><code>-bump</code><dd>Warn whenever it is necessary to switch to another level. |
| If an architecture level is explicitly requested, GAS will not issue |
| warnings until that level is reached, and will then bump the level |
| as required (except between incompatible levels). |
| |
| <br><dt><code>-32 | -64</code><dd>Select the word size, either 32 bits or 64 bits. |
| These options are only available with the ELF object file format, |
| and require that the necessary BFD support has been included. |
| |
| <br><dt><code>--dcti-couples-detect</code><dd>Warn if a DCTI (delayed control transfer instruction) couple is found |
| when generating code for a variant of the SPARC architecture in which |
| the execution of the couple is unpredictable, or very slow. This is |
| disabled by default. |
| </dl> |
| |
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| |
