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| <h5 class="subsubsection">9.44.3.2 Register Names</h5> |
| |
| <p><a name="index-Sparc-registers-2174"></a><a name="index-register-names_002c-Sparc-2175"></a> |
| The Sparc integer register file is broken down into global, |
| outgoing, local, and incoming. |
| |
| <ul> |
| <li>The 8 global registers are referred to as ‘<samp><span class="samp">%g</span><var>n</var></samp>’. |
| |
| <li>The 8 outgoing registers are referred to as ‘<samp><span class="samp">%o</span><var>n</var></samp>’. |
| |
| <li>The 8 local registers are referred to as ‘<samp><span class="samp">%l</span><var>n</var></samp>’. |
| |
| <li>The 8 incoming registers are referred to as ‘<samp><span class="samp">%i</span><var>n</var></samp>’. |
| |
| <li>The frame pointer register ‘<samp><span class="samp">%i6</span></samp>’ can be referenced using |
| the alias ‘<samp><span class="samp">%fp</span></samp>’. |
| |
| <li>The stack pointer register ‘<samp><span class="samp">%o6</span></samp>’ can be referenced using |
| the alias ‘<samp><span class="samp">%sp</span></samp>’. |
| </ul> |
| |
| <p>Floating point registers are simply referred to as ‘<samp><span class="samp">%f</span><var>n</var></samp>’. |
| When assembling for pre-V9, only 32 floating point registers |
| are available. For V9 and later there are 64, but there are |
| restrictions when referencing the upper 32 registers. They |
| can only be accessed as double or quad, and thus only even |
| or quad numbered accesses are allowed. For example, ‘<samp><span class="samp">%f34</span></samp>’ |
| is a legal floating point register, but ‘<samp><span class="samp">%f35</span></samp>’ is not. |
| |
| <p>Floating point registers accessed as double can also be referred using |
| the ‘<samp><span class="samp">%d</span><var>n</var></samp>’ notation, where <var>n</var> is even. Similarly, |
| floating point registers accessed as quad can be referred using the |
| ‘<samp><span class="samp">%q</span><var>n</var></samp>’ notation, where <var>n</var> is a multiple of 4. For |
| example, ‘<samp><span class="samp">%f4</span></samp>’ can be denoted as both ‘<samp><span class="samp">%d4</span></samp>’ and ‘<samp><span class="samp">%q4</span></samp>’. |
| On the other hand, ‘<samp><span class="samp">%f2</span></samp>’ can be denoted as ‘<samp><span class="samp">%d2</span></samp>’ but not as |
| ‘<samp><span class="samp">%q2</span></samp>’. |
| |
| <p>Certain V9 instructions allow access to ancillary state registers. |
| Most simply they can be referred to as ‘<samp><span class="samp">%asr</span><var>n</var></samp>’ where |
| <var>n</var> can be from 16 to 31. However, there are some aliases |
| defined to reference ASR registers defined for various UltraSPARC |
| processors: |
| |
| <ul> |
| <li>The tick compare register is referred to as ‘<samp><span class="samp">%tick_cmpr</span></samp>’. |
| |
| <li>The system tick register is referred to as ‘<samp><span class="samp">%stick</span></samp>’. An alias, |
| ‘<samp><span class="samp">%sys_tick</span></samp>’, exists but is deprecated and should not be used |
| by new software. |
| |
| <li>The system tick compare register is referred to as ‘<samp><span class="samp">%stick_cmpr</span></samp>’. |
| An alias, ‘<samp><span class="samp">%sys_tick_cmpr</span></samp>’, exists but is deprecated and should |
| not be used by new software. |
| |
| <li>The software interrupt register is referred to as ‘<samp><span class="samp">%softint</span></samp>’. |
| |
| <li>The set software interrupt register is referred to as ‘<samp><span class="samp">%set_softint</span></samp>’. |
| The mnemonic ‘<samp><span class="samp">%softint_set</span></samp>’ is provided as an alias. |
| |
| <li>The clear software interrupt register is referred to as |
| ‘<samp><span class="samp">%clear_softint</span></samp>’. The mnemonic ‘<samp><span class="samp">%softint_clear</span></samp>’ is provided |
| as an alias. |
| |
| <li>The performance instrumentation counters register is referred to as |
| ‘<samp><span class="samp">%pic</span></samp>’. |
| |
| <li>The performance control register is referred to as ‘<samp><span class="samp">%pcr</span></samp>’. |
| |
| <li>The graphics status register is referred to as ‘<samp><span class="samp">%gsr</span></samp>’. |
| |
| <li>The V9 dispatch control register is referred to as ‘<samp><span class="samp">%dcr</span></samp>’. |
| </ul> |
| |
| <p>Various V9 branch and conditional move instructions allow |
| specification of which set of integer condition codes to |
| test. These are referred to as ‘<samp><span class="samp">%xcc</span></samp>’ and ‘<samp><span class="samp">%icc</span></samp>’. |
| |
| <p>Additionally, GAS supports the so-called “natural” condition codes; |
| these are referred to as ‘<samp><span class="samp">%ncc</span></samp>’ and reference to ‘<samp><span class="samp">%icc</span></samp>’ if |
| the word size is 32, ‘<samp><span class="samp">%xcc</span></samp>’ if the word size is 64. |
| |
| <p>In V9, there are 4 sets of floating point condition codes |
| which are referred to as ‘<samp><span class="samp">%fcc</span><var>n</var></samp>’. |
| |
| <p>Several special privileged and non-privileged registers |
| exist: |
| |
| <ul> |
| <li>The V9 address space identifier register is referred to as ‘<samp><span class="samp">%asi</span></samp>’. |
| |
| <li>The V9 restorable windows register is referred to as ‘<samp><span class="samp">%canrestore</span></samp>’. |
| |
| <li>The V9 savable windows register is referred to as ‘<samp><span class="samp">%cansave</span></samp>’. |
| |
| <li>The V9 clean windows register is referred to as ‘<samp><span class="samp">%cleanwin</span></samp>’. |
| |
| <li>The V9 current window pointer register is referred to as ‘<samp><span class="samp">%cwp</span></samp>’. |
| |
| <li>The floating-point queue register is referred to as ‘<samp><span class="samp">%fq</span></samp>’. |
| |
| <li>The V8 co-processor queue register is referred to as ‘<samp><span class="samp">%cq</span></samp>’. |
| |
| <li>The floating point status register is referred to as ‘<samp><span class="samp">%fsr</span></samp>’. |
| |
| <li>The other windows register is referred to as ‘<samp><span class="samp">%otherwin</span></samp>’. |
| |
| <li>The V9 program counter register is referred to as ‘<samp><span class="samp">%pc</span></samp>’. |
| |
| <li>The V9 next program counter register is referred to as ‘<samp><span class="samp">%npc</span></samp>’. |
| |
| <li>The V9 processor interrupt level register is referred to as ‘<samp><span class="samp">%pil</span></samp>’. |
| |
| <li>The V9 processor state register is referred to as ‘<samp><span class="samp">%pstate</span></samp>’. |
| |
| <li>The trap base address register is referred to as ‘<samp><span class="samp">%tba</span></samp>’. |
| |
| <li>The V9 tick register is referred to as ‘<samp><span class="samp">%tick</span></samp>’. |
| |
| <li>The V9 trap level is referred to as ‘<samp><span class="samp">%tl</span></samp>’. |
| |
| <li>The V9 trap program counter is referred to as ‘<samp><span class="samp">%tpc</span></samp>’. |
| |
| <li>The V9 trap next program counter is referred to as ‘<samp><span class="samp">%tnpc</span></samp>’. |
| |
| <li>The V9 trap state is referred to as ‘<samp><span class="samp">%tstate</span></samp>’. |
| |
| <li>The V9 trap type is referred to as ‘<samp><span class="samp">%tt</span></samp>’. |
| |
| <li>The V9 condition codes is referred to as ‘<samp><span class="samp">%ccr</span></samp>’. |
| |
| <li>The V9 floating-point registers state is referred to as ‘<samp><span class="samp">%fprs</span></samp>’. |
| |
| <li>The V9 version register is referred to as ‘<samp><span class="samp">%ver</span></samp>’. |
| |
| <li>The V9 window state register is referred to as ‘<samp><span class="samp">%wstate</span></samp>’. |
| |
| <li>The Y register is referred to as ‘<samp><span class="samp">%y</span></samp>’. |
| |
| <li>The V8 window invalid mask register is referred to as ‘<samp><span class="samp">%wim</span></samp>’. |
| |
| <li>The V8 processor state register is referred to as ‘<samp><span class="samp">%psr</span></samp>’. |
| |
| <li>The V9 global register level register is referred to as ‘<samp><span class="samp">%gl</span></samp>’. |
| </ul> |
| |
| <p>Several special register names exist for hypervisor mode code: |
| |
| <ul> |
| <li>The hyperprivileged processor state register is referred to as |
| ‘<samp><span class="samp">%hpstate</span></samp>’. |
| |
| <li>The hyperprivileged trap state register is referred to as ‘<samp><span class="samp">%htstate</span></samp>’. |
| |
| <li>The hyperprivileged interrupt pending register is referred to as |
| ‘<samp><span class="samp">%hintp</span></samp>’. |
| |
| <li>The hyperprivileged trap base address register is referred to as |
| ‘<samp><span class="samp">%htba</span></samp>’. |
| |
| <li>The hyperprivileged implementation version register is referred |
| to as ‘<samp><span class="samp">%hver</span></samp>’. |
| |
| <li>The hyperprivileged system tick offset register is referred to as |
| ‘<samp><span class="samp">%hstick_offset</span></samp>’. Note that there is no ‘<samp><span class="samp">%hstick</span></samp>’ register, |
| the normal ‘<samp><span class="samp">%stick</span></samp>’ is used. |
| |
| <li>The hyperprivileged system tick enable register is referred to as |
| ‘<samp><span class="samp">%hstick_enable</span></samp>’. |
| |
| <li>The hyperprivileged system tick compare register is referred |
| to as ‘<samp><span class="samp">%hstick_cmpr</span></samp>’. |
| </ul> |
| |
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| |
