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| <h5 class="subsubsection">9.44.3.5 Size Translations</h5> |
| |
| <p><a name="index-Sparc-size-translations-2180"></a><a name="index-size_002c-translations_002c-Sparc-2181"></a> |
| Often it is desirable to write code in an operand size agnostic |
| manner. <code>as</code> provides support for this via |
| operand size opcode translations. Translations are supported |
| for loads, stores, shifts, compare-and-swap atomics, and the |
| ‘<samp><span class="samp">clr</span></samp>’ synthetic instruction. |
| |
| <p>If generating 32-bit code, <code>as</code> will generate the |
| 32-bit opcode. Whereas if 64-bit code is being generated, |
| the 64-bit opcode will be emitted. For example <code>ldn</code> |
| will be transformed into <code>ld</code> for 32-bit code and |
| <code>ldx</code> for 64-bit code. |
| |
| <p>Here is an example meant to demonstrate all the supported |
| opcode translations: |
| |
| <pre class="example"> ldn [%o0], %o1 |
| ldna [%o0] %asi, %o2 |
| stn %o1, [%o0] |
| stna %o2, [%o0] %asi |
| slln %o3, 3, %o3 |
| srln %o4, 8, %o4 |
| sran %o5, 12, %o5 |
| casn [%o0], %o1, %o2 |
| casna [%o0] %asi, %o1, %o2 |
| clrn %g1 |
| </pre> |
| <p>In 32-bit mode <code>as</code> will emit: |
| |
| <pre class="example"> ld [%o0], %o1 |
| lda [%o0] %asi, %o2 |
| st %o1, [%o0] |
| sta %o2, [%o0] %asi |
| sll %o3, 3, %o3 |
| srl %o4, 8, %o4 |
| sra %o5, 12, %o5 |
| cas [%o0], %o1, %o2 |
| casa [%o0] %asi, %o1, %o2 |
| clr %g1 |
| </pre> |
| <p>And in 64-bit mode <code>as</code> will emit: |
| |
| <pre class="example"> ldx [%o0], %o1 |
| ldxa [%o0] %asi, %o2 |
| stx %o1, [%o0] |
| stxa %o2, [%o0] %asi |
| sllx %o3, 3, %o3 |
| srlx %o4, 8, %o4 |
| srax %o5, 12, %o5 |
| casx [%o0], %o1, %o2 |
| casxa [%o0] %asi, %o1, %o2 |
| clrx %g1 |
| </pre> |
| <p>Finally, the ‘<samp><span class="samp">.nword</span></samp>’ translating directive is supported |
| as well. It is documented in the section on Sparc machine |
| directives. |
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