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| <h4 class="subsection">9.16.5 Register Naming</h4> |
| |
| <p><a name="index-i386-registers-1207"></a><a name="index-registers_002c-i386-1208"></a><a name="index-x86_002d64-registers-1209"></a><a name="index-registers_002c-x86_002d64-1210"></a>Register operands are always prefixed with ‘<samp><span class="samp">%</span></samp>’. The 80386 registers |
| consist of |
| |
| <ul> |
| <li>the 8 32-bit registers ‘<samp><span class="samp">%eax</span></samp>’ (the accumulator), ‘<samp><span class="samp">%ebx</span></samp>’, |
| ‘<samp><span class="samp">%ecx</span></samp>’, ‘<samp><span class="samp">%edx</span></samp>’, ‘<samp><span class="samp">%edi</span></samp>’, ‘<samp><span class="samp">%esi</span></samp>’, ‘<samp><span class="samp">%ebp</span></samp>’ (the |
| frame pointer), and ‘<samp><span class="samp">%esp</span></samp>’ (the stack pointer). |
| |
| <li>the 8 16-bit low-ends of these: ‘<samp><span class="samp">%ax</span></samp>’, ‘<samp><span class="samp">%bx</span></samp>’, ‘<samp><span class="samp">%cx</span></samp>’, |
| ‘<samp><span class="samp">%dx</span></samp>’, ‘<samp><span class="samp">%di</span></samp>’, ‘<samp><span class="samp">%si</span></samp>’, ‘<samp><span class="samp">%bp</span></samp>’, and ‘<samp><span class="samp">%sp</span></samp>’. |
| |
| <li>the 8 8-bit registers: ‘<samp><span class="samp">%ah</span></samp>’, ‘<samp><span class="samp">%al</span></samp>’, ‘<samp><span class="samp">%bh</span></samp>’, |
| ‘<samp><span class="samp">%bl</span></samp>’, ‘<samp><span class="samp">%ch</span></samp>’, ‘<samp><span class="samp">%cl</span></samp>’, ‘<samp><span class="samp">%dh</span></samp>’, and ‘<samp><span class="samp">%dl</span></samp>’ (These |
| are the high-bytes and low-bytes of ‘<samp><span class="samp">%ax</span></samp>’, ‘<samp><span class="samp">%bx</span></samp>’, |
| ‘<samp><span class="samp">%cx</span></samp>’, and ‘<samp><span class="samp">%dx</span></samp>’) |
| |
| <li>the 6 section registers ‘<samp><span class="samp">%cs</span></samp>’ (code section), ‘<samp><span class="samp">%ds</span></samp>’ |
| (data section), ‘<samp><span class="samp">%ss</span></samp>’ (stack section), ‘<samp><span class="samp">%es</span></samp>’, ‘<samp><span class="samp">%fs</span></samp>’, |
| and ‘<samp><span class="samp">%gs</span></samp>’. |
| |
| <li>the 5 processor control registers ‘<samp><span class="samp">%cr0</span></samp>’, ‘<samp><span class="samp">%cr2</span></samp>’, |
| ‘<samp><span class="samp">%cr3</span></samp>’, ‘<samp><span class="samp">%cr4</span></samp>’, and ‘<samp><span class="samp">%cr8</span></samp>’. |
| |
| <li>the 6 debug registers ‘<samp><span class="samp">%db0</span></samp>’, ‘<samp><span class="samp">%db1</span></samp>’, ‘<samp><span class="samp">%db2</span></samp>’, |
| ‘<samp><span class="samp">%db3</span></samp>’, ‘<samp><span class="samp">%db6</span></samp>’, and ‘<samp><span class="samp">%db7</span></samp>’. |
| |
| <li>the 2 test registers ‘<samp><span class="samp">%tr6</span></samp>’ and ‘<samp><span class="samp">%tr7</span></samp>’. |
| |
| <li>the 8 floating point register stack ‘<samp><span class="samp">%st</span></samp>’ or equivalently |
| ‘<samp><span class="samp">%st(0)</span></samp>’, ‘<samp><span class="samp">%st(1)</span></samp>’, ‘<samp><span class="samp">%st(2)</span></samp>’, ‘<samp><span class="samp">%st(3)</span></samp>’, |
| ‘<samp><span class="samp">%st(4)</span></samp>’, ‘<samp><span class="samp">%st(5)</span></samp>’, ‘<samp><span class="samp">%st(6)</span></samp>’, and ‘<samp><span class="samp">%st(7)</span></samp>’. |
| These registers are overloaded by 8 MMX registers ‘<samp><span class="samp">%mm0</span></samp>’, |
| ‘<samp><span class="samp">%mm1</span></samp>’, ‘<samp><span class="samp">%mm2</span></samp>’, ‘<samp><span class="samp">%mm3</span></samp>’, ‘<samp><span class="samp">%mm4</span></samp>’, ‘<samp><span class="samp">%mm5</span></samp>’, |
| ‘<samp><span class="samp">%mm6</span></samp>’ and ‘<samp><span class="samp">%mm7</span></samp>’. |
| |
| <li>the 8 128-bit SSE registers registers ‘<samp><span class="samp">%xmm0</span></samp>’, ‘<samp><span class="samp">%xmm1</span></samp>’, ‘<samp><span class="samp">%xmm2</span></samp>’, |
| ‘<samp><span class="samp">%xmm3</span></samp>’, ‘<samp><span class="samp">%xmm4</span></samp>’, ‘<samp><span class="samp">%xmm5</span></samp>’, ‘<samp><span class="samp">%xmm6</span></samp>’ and ‘<samp><span class="samp">%xmm7</span></samp>’. |
| </ul> |
| |
| <p>The AMD x86-64 architecture extends the register set by: |
| |
| <ul> |
| <li>enhancing the 8 32-bit registers to 64-bit: ‘<samp><span class="samp">%rax</span></samp>’ (the |
| accumulator), ‘<samp><span class="samp">%rbx</span></samp>’, ‘<samp><span class="samp">%rcx</span></samp>’, ‘<samp><span class="samp">%rdx</span></samp>’, ‘<samp><span class="samp">%rdi</span></samp>’, |
| ‘<samp><span class="samp">%rsi</span></samp>’, ‘<samp><span class="samp">%rbp</span></samp>’ (the frame pointer), ‘<samp><span class="samp">%rsp</span></samp>’ (the stack |
| pointer) |
| |
| <li>the 8 extended registers ‘<samp><span class="samp">%r8</span></samp>’–‘<samp><span class="samp">%r15</span></samp>’. |
| |
| <li>the 8 32-bit low ends of the extended registers: ‘<samp><span class="samp">%r8d</span></samp>’–‘<samp><span class="samp">%r15d</span></samp>’. |
| |
| <li>the 8 16-bit low ends of the extended registers: ‘<samp><span class="samp">%r8w</span></samp>’–‘<samp><span class="samp">%r15w</span></samp>’. |
| |
| <li>the 8 8-bit low ends of the extended registers: ‘<samp><span class="samp">%r8b</span></samp>’–‘<samp><span class="samp">%r15b</span></samp>’. |
| |
| <li>the 4 8-bit registers: ‘<samp><span class="samp">%sil</span></samp>’, ‘<samp><span class="samp">%dil</span></samp>’, ‘<samp><span class="samp">%bpl</span></samp>’, ‘<samp><span class="samp">%spl</span></samp>’. |
| |
| <li>the 8 debug registers: ‘<samp><span class="samp">%db8</span></samp>’–‘<samp><span class="samp">%db15</span></samp>’. |
| |
| <li>the 8 128-bit SSE registers: ‘<samp><span class="samp">%xmm8</span></samp>’–‘<samp><span class="samp">%xmm15</span></samp>’. |
| </ul> |
| |
| <p>With the AVX extensions more registers were made available: |
| |
| <ul> |
| <li>the 16 256-bit SSE ‘<samp><span class="samp">%ymm0</span></samp>’–‘<samp><span class="samp">%ymm15</span></samp>’ (only the first 8 |
| available in 32-bit mode). The bottom 128 bits are overlaid with the |
| ‘<samp><span class="samp">xmm0</span></samp>’–‘<samp><span class="samp">xmm15</span></samp>’ registers. |
| |
| </ul> |
| |
| <p>The AVX2 extensions made in 64-bit mode more registers available: |
| |
| <ul> |
| <li>the 16 128-bit registers ‘<samp><span class="samp">%xmm16</span></samp>’–‘<samp><span class="samp">%xmm31</span></samp>’ and the 16 256-bit |
| registers ‘<samp><span class="samp">%ymm16</span></samp>’–‘<samp><span class="samp">%ymm31</span></samp>’. |
| |
| </ul> |
| |
| <p>The AVX512 extensions added the following registers: |
| |
| <ul> |
| <li>the 32 512-bit registers ‘<samp><span class="samp">%zmm0</span></samp>’–‘<samp><span class="samp">%zmm31</span></samp>’ (only the first 8 |
| available in 32-bit mode). The bottom 128 bits are overlaid with the |
| ‘<samp><span class="samp">%xmm0</span></samp>’–‘<samp><span class="samp">%xmm31</span></samp>’ registers and the first 256 bits are |
| overlaid with the ‘<samp><span class="samp">%ymm0</span></samp>’–‘<samp><span class="samp">%ymm31</span></samp>’ registers. |
| |
| <li>the 8 mask registers ‘<samp><span class="samp">%k0</span></samp>’–‘<samp><span class="samp">%k7</span></samp>’. |
| |
| </ul> |
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