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| <h5 class="subsubsection">E.5.2.1 <acronym>MIPS</acronym> Register Packet Format</h5> |
| |
| <p><a name="index-register-packet-format_002c-_0040acronym_007bMIPS_007d-3554"></a> |
| The following <code>g</code>/<code>G</code> packets have previously been defined. |
| In the below, some thirty-two bit registers are transferred as |
| sixty-four bits. Those registers should be zero/sign extended (which?) |
| to fill the space allocated. Register bytes are transferred in target |
| byte order. The two nibbles within a register byte are transferred |
| most-significant – least-significant. |
| |
| <dl> |
| <dt><span class="roman">MIPS32</span><dd>All registers are transferred as thirty-two bit quantities in the order: |
| 32 general-purpose; sr; lo; hi; bad; cause; pc; 32 floating-point |
| registers; fsr; fir; fp. |
| |
| <br><dt><span class="roman">MIPS64</span><dd>All registers are transferred as sixty-four bit quantities (including |
| thirty-two bit registers such as <code>sr</code>). The ordering is the same |
| as <code>MIPS32</code>. |
| |
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