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| <h4 class="subsection">21.3.6 OpenRISC 1000</h4> |
| |
| <p><a name="index-OpenRISC-1000-1587"></a> |
| The OpenRISC 1000 provides a free RISC instruction set architecture. It is |
| mainly provided as a soft-core which can run on Xilinx, Altera and other |
| FPGA's. |
| |
| <p><span class="sc">gdb</span> for OpenRISC supports the below commands when connecting to |
| a target: |
| |
| |
| <a name="index-target-sim-1588"></a> |
| <dl><dt><code>target sim</code><dd> |
| Runs the builtin CPU simulator which can run very basic |
| programs but does not support most hardware functions like MMU. |
| For more complex use cases the user is advised to run an external |
| target, and connect using ‘<samp><span class="samp">target remote</span></samp>’. |
| |
| <p>Example: <code>target sim</code> |
| |
| <br><dt><code>set debug or1k</code><dd>Toggle whether to display OpenRISC-specific debugging messages from the |
| OpenRISC target support subsystem. |
| |
| <br><dt><code>show debug or1k</code><dd>Show whether OpenRISC-specific debugging messages are enabled. |
| </dl> |
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