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| <a name="PowerPC-Features"></a> |
| <p> |
| Next: <a rel="next" accesskey="n" href="RISC_002dV-Features.html#RISC_002dV-Features">RISC-V Features</a>, |
| Previous: <a rel="previous" accesskey="p" href="OpenRISC-1000-Features.html#OpenRISC-1000-Features">OpenRISC 1000 Features</a>, |
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| |
| <h4 class="subsection">G.5.11 PowerPC Features</h4> |
| |
| <p><a name="index-target-descriptions_002c-PowerPC-features-3668"></a> |
| The ‘<samp><span class="samp">org.gnu.gdb.power.core</span></samp>’ feature is required for PowerPC |
| targets. It should contain registers ‘<samp><span class="samp">r0</span></samp>’ through ‘<samp><span class="samp">r31</span></samp>’, |
| ‘<samp><span class="samp">pc</span></samp>’, ‘<samp><span class="samp">msr</span></samp>’, ‘<samp><span class="samp">cr</span></samp>’, ‘<samp><span class="samp">lr</span></samp>’, ‘<samp><span class="samp">ctr</span></samp>’, and |
| ‘<samp><span class="samp">xer</span></samp>’. They may be 32-bit or 64-bit depending on the target. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.fpu</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">f0</span></samp>’ through ‘<samp><span class="samp">f31</span></samp>’ and ‘<samp><span class="samp">fpscr</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.altivec</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">vr0</span></samp>’ through ‘<samp><span class="samp">vr31</span></samp>’, ‘<samp><span class="samp">vscr</span></samp>’, and |
| ‘<samp><span class="samp">vrsave</span></samp>’. <span class="sc">gdb</span> will define pseudo-registers ‘<samp><span class="samp">v0</span></samp>’ |
| through ‘<samp><span class="samp">v31</span></samp>’ as aliases for the corresponding ‘<samp><span class="samp">vrX</span></samp>’ |
| registers. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.vsx</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">vs0h</span></samp>’ through ‘<samp><span class="samp">vs31h</span></samp>’. <span class="sc">gdb</span> will |
| combine these registers with the floating point registers (‘<samp><span class="samp">f0</span></samp>’ |
| through ‘<samp><span class="samp">f31</span></samp>’) and the altivec registers (‘<samp><span class="samp">vr0</span></samp>’ through |
| ‘<samp><span class="samp">vr31</span></samp>’) to present the 128-bit wide registers ‘<samp><span class="samp">vs0</span></samp>’ through |
| ‘<samp><span class="samp">vs63</span></samp>’, the set of vector-scalar registers for POWER7. |
| Therefore, this feature requires both ‘<samp><span class="samp">org.gnu.gdb.power.fpu</span></samp>’ and |
| ‘<samp><span class="samp">org.gnu.gdb.power.altivec</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.spe</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">ev0h</span></samp>’ through ‘<samp><span class="samp">ev31h</span></samp>’, ‘<samp><span class="samp">acc</span></samp>’, and |
| ‘<samp><span class="samp">spefscr</span></samp>’. SPE targets should provide 32-bit registers in |
| ‘<samp><span class="samp">org.gnu.gdb.power.core</span></samp>’ and provide the upper halves in |
| ‘<samp><span class="samp">ev0h</span></samp>’ through ‘<samp><span class="samp">ev31h</span></samp>’. <span class="sc">gdb</span> will combine |
| these to present registers ‘<samp><span class="samp">ev0</span></samp>’ through ‘<samp><span class="samp">ev31</span></samp>’ to the |
| user. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.ppr</span></samp>’ feature is optional. It should |
| contain the 64-bit register ‘<samp><span class="samp">ppr</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.dscr</span></samp>’ feature is optional. It should |
| contain the 64-bit register ‘<samp><span class="samp">dscr</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.tar</span></samp>’ feature is optional. It should |
| contain the 64-bit register ‘<samp><span class="samp">tar</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.ebb</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">bescr</span></samp>’, ‘<samp><span class="samp">ebbhr</span></samp>’ and ‘<samp><span class="samp">ebbrr</span></samp>’, all |
| 64-bit wide. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.linux.pmu</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">mmcr0</span></samp>’, ‘<samp><span class="samp">mmcr2</span></samp>’, ‘<samp><span class="samp">siar</span></samp>’, ‘<samp><span class="samp">sdar</span></samp>’ |
| and ‘<samp><span class="samp">sier</span></samp>’, all 64-bit wide. This is the subset of the isa 2.07 |
| server PMU registers provided by <span class="sc">gnu</span>/Linux. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.htm.spr</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">tfhar</span></samp>’, ‘<samp><span class="samp">texasr</span></samp>’ and ‘<samp><span class="samp">tfiar</span></samp>’, all |
| 64-bit wide. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.htm.core</span></samp>’ feature is optional. It should |
| contain the checkpointed general-purpose registers ‘<samp><span class="samp">cr0</span></samp>’ through |
| ‘<samp><span class="samp">cr31</span></samp>’, as well as the checkpointed registers ‘<samp><span class="samp">clr</span></samp>’ and |
| ‘<samp><span class="samp">cctr</span></samp>’. These registers may all be either 32-bit or 64-bit |
| depending on the target. It should also contain the checkpointed |
| registers ‘<samp><span class="samp">ccr</span></samp>’ and ‘<samp><span class="samp">cxer</span></samp>’, which should both be 32-bit |
| wide. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.htm.fpu</span></samp>’ feature is optional. It should |
| contain the checkpointed 64-bit floating-point registers ‘<samp><span class="samp">cf0</span></samp>’ |
| through ‘<samp><span class="samp">cf31</span></samp>’, as well as the checkpointed 64-bit register |
| ‘<samp><span class="samp">cfpscr</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.htm.altivec</span></samp>’ feature is optional. It |
| should contain the checkpointed altivec registers ‘<samp><span class="samp">cvr0</span></samp>’ through |
| ‘<samp><span class="samp">cvr31</span></samp>’, all 128-bit wide. It should also contain the |
| checkpointed registers ‘<samp><span class="samp">cvscr</span></samp>’ and ‘<samp><span class="samp">cvrsave</span></samp>’, both 32-bit |
| wide. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.htm.vsx</span></samp>’ feature is optional. It should |
| contain registers ‘<samp><span class="samp">cvs0h</span></samp>’ through ‘<samp><span class="samp">cvs31h</span></samp>’. <span class="sc">gdb</span> |
| will combine these registers with the checkpointed floating point |
| registers (‘<samp><span class="samp">cf0</span></samp>’ through ‘<samp><span class="samp">cf31</span></samp>’) and the checkpointed |
| altivec registers (‘<samp><span class="samp">cvr0</span></samp>’ through ‘<samp><span class="samp">cvr31</span></samp>’) to present the |
| 128-bit wide checkpointed vector-scalar registers ‘<samp><span class="samp">cvs0</span></samp>’ through |
| ‘<samp><span class="samp">cvs63</span></samp>’. Therefore, this feature requires both |
| ‘<samp><span class="samp">org.gnu.gdb.power.htm.altivec</span></samp>’ and |
| ‘<samp><span class="samp">org.gnu.gdb.power.htm.fpu</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.htm.ppr</span></samp>’ feature is optional. It should |
| contain the 64-bit checkpointed register ‘<samp><span class="samp">cppr</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.htm.dscr</span></samp>’ feature is optional. It should |
| contain the 64-bit checkpointed register ‘<samp><span class="samp">cdscr</span></samp>’. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.power.htm.tar</span></samp>’ feature is optional. It should |
| contain the 64-bit checkpointed register ‘<samp><span class="samp">ctar</span></samp>’. |
| |
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| |
