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| <h4 class="subsection">G.5.12 RISC-V Features</h4> |
| |
| <p><a name="index-target-descriptions_002c-RISC_002dV-Features-3669"></a> |
| The ‘<samp><span class="samp">org.gnu.gdb.riscv.cpu</span></samp>’ feature is required for RISC-V |
| targets. It should contain the registers ‘<samp><span class="samp">x0</span></samp>’ through |
| ‘<samp><span class="samp">x31</span></samp>’, and ‘<samp><span class="samp">pc</span></samp>’. Either the architectural names (‘<samp><span class="samp">x0</span></samp>’, |
| ‘<samp><span class="samp">x1</span></samp>’, etc) can be used, or the ABI names (‘<samp><span class="samp">zero</span></samp>’, ‘<samp><span class="samp">ra</span></samp>’, |
| etc). |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.riscv.fpu</span></samp>’ feature is optional. If present, it |
| should contain registers ‘<samp><span class="samp">f0</span></samp>’ through ‘<samp><span class="samp">f31</span></samp>’, ‘<samp><span class="samp">fflags</span></samp>’, |
| ‘<samp><span class="samp">frm</span></samp>’, and ‘<samp><span class="samp">fcsr</span></samp>’. As with the cpu feature, either the |
| architectural register names, or the ABI names can be used. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.riscv.virtual</span></samp>’ feature is optional. If present, |
| it should contain registers that are not backed by real registers on |
| the target, but are instead virtual, where the register value is |
| derived from other target state. In many ways these are like |
| <span class="sc">gdb</span>s pseudo-registers, except implemented by the target. |
| Currently the only register expected in this set is the one byte |
| ‘<samp><span class="samp">priv</span></samp>’ register that contains the target's privilege level in the |
| least significant two bits. |
| |
| <p>The ‘<samp><span class="samp">org.gnu.gdb.riscv.csr</span></samp>’ feature is optional. If present, it |
| should contain all of the target's standard CSRs. Standard CSRs are |
| those defined in the RISC-V specification documents. There is some |
| overlap between this feature and the fpu feature; the ‘<samp><span class="samp">fflags</span></samp>’, |
| ‘<samp><span class="samp">frm</span></samp>’, and ‘<samp><span class="samp">fcsr</span></samp>’ registers could be in either feature. The |
| expectation is that these registers will be in the fpu feature if the |
| target has floating point hardware, but can be moved into the csr |
| feature if the target has the floating point control registers, but no |
| other floating point hardware. |
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