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| <a name="MIPS-Options"></a> |
| <div class="header"> |
| <p> |
| Next: <a href="MIPS-Macros.html#MIPS-Macros" accesskey="n" rel="next">MIPS Macros</a>, Up: <a href="MIPS_002dDependent.html#MIPS_002dDependent" accesskey="u" rel="up">MIPS-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p> |
| </div> |
| <hr> |
| <a name="Assembler-options"></a> |
| <h4 class="subsection">9.27.1 Assembler options</h4> |
| |
| <p>The MIPS configurations of <small>GNU</small> <code>as</code> support these |
| special options: |
| </p> |
| <dl compact="compact"> |
| <dd><a name="index-_002dG-option-_0028MIPS_0029"></a> |
| </dd> |
| <dt><code>-G <var>num</var></code></dt> |
| <dd><p>Set the “small data” limit to <var>n</var> bytes. The default limit is 8 bytes. |
| See <a href="MIPS-Small-Data.html#MIPS-Small-Data">Controlling the use of small data accesses</a>. |
| </p> |
| <a name="index-_002dEB-option-_0028MIPS_0029"></a> |
| <a name="index-_002dEL-option-_0028MIPS_0029"></a> |
| <a name="index-MIPS-big_002dendian-output"></a> |
| <a name="index-MIPS-little_002dendian-output"></a> |
| <a name="index-big_002dendian-output_002c-MIPS"></a> |
| <a name="index-little_002dendian-output_002c-MIPS"></a> |
| </dd> |
| <dt><code>-EB</code></dt> |
| <dt><code>-EL</code></dt> |
| <dd><p>Any MIPS configuration of <code>as</code> can select big-endian or |
| little-endian output at run time (unlike the other <small>GNU</small> development |
| tools, which must be configured for one or the other). Use ‘<samp>-EB</samp>’ |
| to select big-endian output, and ‘<samp>-EL</samp>’ for little-endian. |
| </p> |
| </dd> |
| <dt><code>-KPIC</code></dt> |
| <dd><a name="index-PIC-selection_002c-MIPS"></a> |
| <a name="index-_002dKPIC-option_002c-MIPS"></a> |
| <p>Generate SVR4-style PIC. This option tells the assembler to generate |
| SVR4-style position-independent macro expansions. It also tells the |
| assembler to mark the output file as PIC. |
| </p> |
| </dd> |
| <dt><code>-mvxworks-pic</code></dt> |
| <dd><a name="index-_002dmvxworks_002dpic-option_002c-MIPS"></a> |
| <p>Generate VxWorks PIC. This option tells the assembler to generate |
| VxWorks-style position-independent macro expansions. |
| </p> |
| <a name="index-MIPS-architecture-options"></a> |
| </dd> |
| <dt><code>-mips1</code></dt> |
| <dt><code>-mips2</code></dt> |
| <dt><code>-mips3</code></dt> |
| <dt><code>-mips4</code></dt> |
| <dt><code>-mips5</code></dt> |
| <dt><code>-mips32</code></dt> |
| <dt><code>-mips32r2</code></dt> |
| <dt><code>-mips32r3</code></dt> |
| <dt><code>-mips32r5</code></dt> |
| <dt><code>-mips32r6</code></dt> |
| <dt><code>-mips64</code></dt> |
| <dt><code>-mips64r2</code></dt> |
| <dt><code>-mips64r3</code></dt> |
| <dt><code>-mips64r5</code></dt> |
| <dt><code>-mips64r6</code></dt> |
| <dd><p>Generate code for a particular MIPS Instruction Set Architecture level. |
| ‘<samp>-mips1</samp>’ corresponds to the R2000 and R3000 processors, |
| ‘<samp>-mips2</samp>’ to the R6000 processor, ‘<samp>-mips3</samp>’ to the |
| R4000 processor, and ‘<samp>-mips4</samp>’ to the R8000 and R10000 processors. |
| ‘<samp>-mips5</samp>’, ‘<samp>-mips32</samp>’, ‘<samp>-mips32r2</samp>’, ‘<samp>-mips32r3</samp>’, |
| ‘<samp>-mips32r5</samp>’, ‘<samp>-mips32r6</samp>’, ‘<samp>-mips64</samp>’, ‘<samp>-mips64r2</samp>’, |
| ‘<samp>-mips64r3</samp>’, ‘<samp>-mips64r5</samp>’, and ‘<samp>-mips64r6</samp>’ correspond to |
| generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 |
| Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 |
| Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, |
| respectively. You can also switch instruction sets during the assembly; |
| see <a href="MIPS-ISA.html#MIPS-ISA">Directives to override the ISA level</a>. |
| </p> |
| </dd> |
| <dt><code>-mgp32</code></dt> |
| <dt><code>-mfp32</code></dt> |
| <dd><p>Some macros have different expansions for 32-bit and 64-bit registers. |
| The register sizes are normally inferred from the ISA and ABI, but these |
| flags force a certain group of registers to be treated as 32 bits wide at |
| all times. ‘<samp>-mgp32</samp>’ controls the size of general-purpose registers |
| and ‘<samp>-mfp32</samp>’ controls the size of floating-point registers. |
| </p> |
| <p>The <code>.set gp=32</code> and <code>.set fp=32</code> directives allow the size |
| of registers to be changed for parts of an object. The default value is |
| restored by <code>.set gp=default</code> and <code>.set fp=default</code>. |
| </p> |
| <p>On some MIPS variants there is a 32-bit mode flag; when this flag is |
| set, 64-bit instructions generate a trap. Also, some 32-bit OSes only |
| save the 32-bit registers on a context switch, so it is essential never |
| to use the 64-bit registers. |
| </p> |
| </dd> |
| <dt><code>-mgp64</code></dt> |
| <dt><code>-mfp64</code></dt> |
| <dd><p>Assume that 64-bit registers are available. This is provided in the |
| interests of symmetry with ‘<samp>-mgp32</samp>’ and ‘<samp>-mfp32</samp>’. |
| </p> |
| <p>The <code>.set gp=64</code> and <code>.set fp=64</code> directives allow the size |
| of registers to be changed for parts of an object. The default value is |
| restored by <code>.set gp=default</code> and <code>.set fp=default</code>. |
| </p> |
| </dd> |
| <dt><code>-mfpxx</code></dt> |
| <dd><p>Make no assumptions about whether 32-bit or 64-bit floating-point |
| registers are available. This is provided to support having modules |
| compatible with either ‘<samp>-mfp32</samp>’ or ‘<samp>-mfp64</samp>’. This option can |
| only be used with MIPS II and above. |
| </p> |
| <p>The <code>.set fp=xx</code> directive allows a part of an object to be marked |
| as not making assumptions about 32-bit or 64-bit FP registers. The |
| default value is restored by <code>.set fp=default</code>. |
| </p> |
| </dd> |
| <dt><code>-modd-spreg</code></dt> |
| <dt><code>-mno-odd-spreg</code></dt> |
| <dd><p>Enable use of floating-point operations on odd-numbered single-precision |
| registers when supported by the ISA. ‘<samp>-mfpxx</samp>’ implies |
| ‘<samp>-mno-odd-spreg</samp>’, otherwise the default is ‘<samp>-modd-spreg</samp>’ |
| </p> |
| </dd> |
| <dt><code>-mips16</code></dt> |
| <dt><code>-no-mips16</code></dt> |
| <dd><p>Generate code for the MIPS 16 processor. This is equivalent to putting |
| <code>.set mips16</code> at the start of the assembly file. ‘<samp>-no-mips16</samp>’ |
| turns off this option. |
| </p> |
| </dd> |
| <dt><code>-mmicromips</code></dt> |
| <dt><code>-mno-micromips</code></dt> |
| <dd><p>Generate code for the microMIPS processor. This is equivalent to putting |
| <code>.set micromips</code> at the start of the assembly file. ‘<samp>-mno-micromips</samp>’ |
| turns off this option. This is equivalent to putting <code>.set nomicromips</code> |
| at the start of the assembly file. |
| </p> |
| </dd> |
| <dt><code>-msmartmips</code></dt> |
| <dt><code>-mno-smartmips</code></dt> |
| <dd><p>Enables the SmartMIPS extensions to the MIPS32 instruction set, which |
| provides a number of new instructions which target smartcard and |
| cryptographic applications. This is equivalent to putting |
| <code>.set smartmips</code> at the start of the assembly file. |
| ‘<samp>-mno-smartmips</samp>’ turns off this option. |
| </p> |
| </dd> |
| <dt><code>-mips3d</code></dt> |
| <dt><code>-no-mips3d</code></dt> |
| <dd><p>Generate code for the MIPS-3D Application Specific Extension. |
| This tells the assembler to accept MIPS-3D instructions. |
| ‘<samp>-no-mips3d</samp>’ turns off this option. |
| </p> |
| </dd> |
| <dt><code>-mdmx</code></dt> |
| <dt><code>-no-mdmx</code></dt> |
| <dd><p>Generate code for the MDMX Application Specific Extension. |
| This tells the assembler to accept MDMX instructions. |
| ‘<samp>-no-mdmx</samp>’ turns off this option. |
| </p> |
| </dd> |
| <dt><code>-mdsp</code></dt> |
| <dt><code>-mno-dsp</code></dt> |
| <dd><p>Generate code for the DSP Release 1 Application Specific Extension. |
| This tells the assembler to accept DSP Release 1 instructions. |
| ‘<samp>-mno-dsp</samp>’ turns off this option. |
| </p> |
| </dd> |
| <dt><code>-mdspr2</code></dt> |
| <dt><code>-mno-dspr2</code></dt> |
| <dd><p>Generate code for the DSP Release 2 Application Specific Extension. |
| This option implies -mdsp. |
| This tells the assembler to accept DSP Release 2 instructions. |
| ‘<samp>-mno-dspr2</samp>’ turns off this option. |
| </p> |
| </dd> |
| <dt><code>-mmt</code></dt> |
| <dt><code>-mno-mt</code></dt> |
| <dd><p>Generate code for the MT Application Specific Extension. |
| This tells the assembler to accept MT instructions. |
| ‘<samp>-mno-mt</samp>’ turns off this option. |
| </p> |
| </dd> |
| <dt><code>-mmcu</code></dt> |
| <dt><code>-mno-mcu</code></dt> |
| <dd><p>Generate code for the MCU Application Specific Extension. |
| This tells the assembler to accept MCU instructions. |
| ‘<samp>-mno-mcu</samp>’ turns off this option. |
| </p> |
| </dd> |
| <dt><code>-mmsa</code></dt> |
| <dt><code>-mno-msa</code></dt> |
| <dd><p>Generate code for the MIPS SIMD Architecture Extension. |
| This tells the assembler to accept MSA instructions. |
| ‘<samp>-mno-msa</samp>’ turns off this option. |
| </p> |
| </dd> |
| <dt><code>-mxpa</code></dt> |
| <dt><code>-mno-xpa</code></dt> |
| <dd><p>Generate code for the MIPS eXtended Physical Address (XPA) Extension. |
| This tells the assembler to accept XPA instructions. |
| ‘<samp>-mno-xpa</samp>’ turns off this option. |
| </p> |
| </dd> |
| <dt><code>-mvirt</code></dt> |
| <dt><code>-mno-virt</code></dt> |
| <dd><p>Generate code for the Virtualization Application Specific Extension. |
| This tells the assembler to accept Virtualization instructions. |
| ‘<samp>-mno-virt</samp>’ turns off this option. |
| </p> |
| </dd> |
| <dt><code>-minsn32</code></dt> |
| <dt><code>-mno-insn32</code></dt> |
| <dd><p>Only use 32-bit instruction encodings when generating code for the |
| microMIPS processor. This option inhibits the use of any 16-bit |
| instructions. This is equivalent to putting <code>.set insn32</code> at |
| the start of the assembly file. ‘<samp>-mno-insn32</samp>’ turns off this |
| option. This is equivalent to putting <code>.set noinsn32</code> at the |
| start of the assembly file. By default ‘<samp>-mno-insn32</samp>’ is |
| selected, allowing all instructions to be used. |
| </p> |
| </dd> |
| <dt><code>-mfix7000</code></dt> |
| <dt><code>-mno-fix7000</code></dt> |
| <dd><p>Cause nops to be inserted if the read of the destination register |
| of an mfhi or mflo instruction occurs in the following two instructions. |
| </p> |
| </dd> |
| <dt><code>-mfix-rm7000</code></dt> |
| <dt><code>-mno-fix-rm7000</code></dt> |
| <dd><p>Cause nops to be inserted if a dmult or dmultu instruction is |
| followed by a load instruction. |
| </p> |
| </dd> |
| <dt><code>-mfix-loongson2f-jump</code></dt> |
| <dt><code>-mno-fix-loongson2f-jump</code></dt> |
| <dd><p>Eliminate instruction fetch from outside 256M region to work around the |
| Loongson2F ‘<samp>jump</samp>’ instructions. Without it, under extreme cases, |
| the kernel may crash. The issue has been solved in latest processor |
| batches, but this fix has no side effect to them. |
| </p> |
| </dd> |
| <dt><code>-mfix-loongson2f-nop</code></dt> |
| <dt><code>-mno-fix-loongson2f-nop</code></dt> |
| <dd><p>Replace nops by <code>or at,at,zero</code> to work around the Loongson2F |
| ‘<samp>nop</samp>’ errata. Without it, under extreme cases, the CPU might |
| deadlock. The issue has been solved in later Loongson2F batches, but |
| this fix has no side effect to them. |
| </p> |
| </dd> |
| <dt><code>-mfix-vr4120</code></dt> |
| <dt><code>-mno-fix-vr4120</code></dt> |
| <dd><p>Insert nops to work around certain VR4120 errata. This option is |
| intended to be used on GCC-generated code: it is not designed to catch |
| all problems in hand-written assembler code. |
| </p> |
| </dd> |
| <dt><code>-mfix-vr4130</code></dt> |
| <dt><code>-mno-fix-vr4130</code></dt> |
| <dd><p>Insert nops to work around the VR4130 ‘<samp>mflo</samp>’/‘<samp>mfhi</samp>’ errata. |
| </p> |
| </dd> |
| <dt><code>-mfix-24k</code></dt> |
| <dt><code>-mno-fix-24k</code></dt> |
| <dd><p>Insert nops to work around the 24K ‘<samp>eret</samp>’/‘<samp>deret</samp>’ errata. |
| </p> |
| </dd> |
| <dt><code>-mfix-cn63xxp1</code></dt> |
| <dt><code>-mno-fix-cn63xxp1</code></dt> |
| <dd><p>Replace <code>pref</code> hints 0 - 4 and 6 - 24 with hint 28 to work around |
| certain CN63XXP1 errata. |
| </p> |
| </dd> |
| <dt><code>-m4010</code></dt> |
| <dt><code>-no-m4010</code></dt> |
| <dd><p>Generate code for the LSI R4010 chip. This tells the assembler to |
| accept the R4010-specific instructions (‘<samp>addciu</samp>’, ‘<samp>ffc</samp>’, |
| etc.), and to not schedule ‘<samp>nop</samp>’ instructions around accesses to |
| the ‘<samp>HI</samp>’ and ‘<samp>LO</samp>’ registers. ‘<samp>-no-m4010</samp>’ turns off this |
| option. |
| </p> |
| </dd> |
| <dt><code>-m4650</code></dt> |
| <dt><code>-no-m4650</code></dt> |
| <dd><p>Generate code for the MIPS R4650 chip. This tells the assembler to accept |
| the ‘<samp>mad</samp>’ and ‘<samp>madu</samp>’ instruction, and to not schedule ‘<samp>nop</samp>’ |
| instructions around accesses to the ‘<samp>HI</samp>’ and ‘<samp>LO</samp>’ registers. |
| ‘<samp>-no-m4650</samp>’ turns off this option. |
| </p> |
| </dd> |
| <dt><code>-m3900</code></dt> |
| <dt><code>-no-m3900</code></dt> |
| <dt><code>-m4100</code></dt> |
| <dt><code>-no-m4100</code></dt> |
| <dd><p>For each option ‘<samp>-m<var>nnnn</var></samp>’, generate code for the MIPS |
| R<var>nnnn</var> chip. This tells the assembler to accept instructions |
| specific to that chip, and to schedule for that chip’s hazards. |
| </p> |
| </dd> |
| <dt><code>-march=<var>cpu</var></code></dt> |
| <dd><p>Generate code for a particular MIPS CPU. It is exactly equivalent to |
| ‘<samp>-m<var>cpu</var></samp>’, except that there are more value of <var>cpu</var> |
| understood. Valid <var>cpu</var> value are: |
| </p> |
| <blockquote> |
| <p>2000, |
| 3000, |
| 3900, |
| 4000, |
| 4010, |
| 4100, |
| 4111, |
| vr4120, |
| vr4130, |
| vr4181, |
| 4300, |
| 4400, |
| 4600, |
| 4650, |
| 5000, |
| rm5200, |
| rm5230, |
| rm5231, |
| rm5261, |
| rm5721, |
| vr5400, |
| vr5500, |
| 6000, |
| rm7000, |
| 8000, |
| rm9000, |
| 10000, |
| 12000, |
| 14000, |
| 16000, |
| 4kc, |
| 4km, |
| 4kp, |
| 4ksc, |
| 4kec, |
| 4kem, |
| 4kep, |
| 4ksd, |
| m4k, |
| m4kp, |
| m14k, |
| m14kc, |
| m14ke, |
| m14kec, |
| 24kc, |
| 24kf2_1, |
| 24kf, |
| 24kf1_1, |
| 24kec, |
| 24kef2_1, |
| 24kef, |
| 24kef1_1, |
| 34kc, |
| 34kf2_1, |
| 34kf, |
| 34kf1_1, |
| 34kn, |
| 74kc, |
| 74kf2_1, |
| 74kf, |
| 74kf1_1, |
| 74kf3_2, |
| 1004kc, |
| 1004kf2_1, |
| 1004kf, |
| 1004kf1_1, |
| p5600, |
| 5kc, |
| 5kf, |
| 20kc, |
| 25kf, |
| sb1, |
| sb1a, |
| i6400, |
| loongson2e, |
| loongson2f, |
| loongson3a, |
| octeon, |
| octeon+, |
| octeon2, |
| octeon3, |
| xlr, |
| xlp |
| </p></blockquote> |
| |
| <p>For compatibility reasons, ‘<samp><var>n</var>x</samp>’ and ‘<samp><var>b</var>fx</samp>’ are |
| accepted as synonyms for ‘<samp><var>n</var>f1_1</samp>’. These values are |
| deprecated. |
| </p> |
| </dd> |
| <dt><code>-mtune=<var>cpu</var></code></dt> |
| <dd><p>Schedule and tune for a particular MIPS CPU. Valid <var>cpu</var> values are |
| identical to ‘<samp>-march=<var>cpu</var></samp>’. |
| </p> |
| </dd> |
| <dt><code>-mabi=<var>abi</var></code></dt> |
| <dd><p>Record which ABI the source code uses. The recognized arguments |
| are: ‘<samp>32</samp>’, ‘<samp>n32</samp>’, ‘<samp>o64</samp>’, ‘<samp>64</samp>’ and ‘<samp>eabi</samp>’. |
| </p> |
| </dd> |
| <dt><code>-msym32</code></dt> |
| <dt><code>-mno-sym32</code></dt> |
| <dd><a name="index-_002dmsym32"></a> |
| <a name="index-_002dmno_002dsym32"></a> |
| <p>Equivalent to adding <code>.set sym32</code> or <code>.set nosym32</code> to |
| the beginning of the assembler input. See <a href="MIPS-Symbol-Sizes.html#MIPS-Symbol-Sizes">MIPS Symbol Sizes</a>. |
| </p> |
| <a name="index-_002dnocpp-ignored-_0028MIPS_0029"></a> |
| </dd> |
| <dt><code>-nocpp</code></dt> |
| <dd><p>This option is ignored. It is accepted for command-line compatibility with |
| other assemblers, which use it to turn off C style preprocessing. With |
| <small>GNU</small> <code>as</code>, there is no need for ‘<samp>-nocpp</samp>’, because the |
| <small>GNU</small> assembler itself never runs the C preprocessor. |
| </p> |
| </dd> |
| <dt><code>-msoft-float</code></dt> |
| <dt><code>-mhard-float</code></dt> |
| <dd><p>Disable or enable floating-point instructions. Note that by default |
| floating-point instructions are always allowed even with CPU targets |
| that don’t have support for these instructions. |
| </p> |
| </dd> |
| <dt><code>-msingle-float</code></dt> |
| <dt><code>-mdouble-float</code></dt> |
| <dd><p>Disable or enable double-precision floating-point operations. Note |
| that by default double-precision floating-point operations are always |
| allowed even with CPU targets that don’t have support for these |
| operations. |
| </p> |
| </dd> |
| <dt><code>--construct-floats</code></dt> |
| <dt><code>--no-construct-floats</code></dt> |
| <dd><p>The <code>--no-construct-floats</code> option disables the construction of |
| double width floating point constants by loading the two halves of the |
| value into the two single width floating point registers that make up |
| the double width register. This feature is useful if the processor |
| support the FR bit in its status register, and this bit is known (by |
| the programmer) to be set. This bit prevents the aliasing of the double |
| width register by the single width registers. |
| </p> |
| <p>By default <code>--construct-floats</code> is selected, allowing construction |
| of these floating point constants. |
| </p> |
| </dd> |
| <dt><code>--relax-branch</code></dt> |
| <dt><code>--no-relax-branch</code></dt> |
| <dd><p>The ‘<samp>--relax-branch</samp>’ option enables the relaxation of out-of-range |
| branches. Any branches whose target cannot be reached directly are |
| converted to a small instruction sequence including an inverse-condition |
| branch to the physically next instruction, and a jump to the original |
| target is inserted between the two instructions. In PIC code the jump |
| will involve further instructions for address calculation. |
| </p> |
| <p>The <code>BC1ANY2F</code>, <code>BC1ANY2T</code>, <code>BC1ANY4F</code>, <code>BC1ANY4T</code>, |
| <code>BPOSGE32</code> and <code>BPOSGE64</code> instructions are excluded from |
| relaxation, because they have no complementing counterparts. They could |
| be relaxed with the use of a longer sequence involving another branch, |
| however this has not been implemented and if their target turns out of |
| reach, they produce an error even if branch relaxation is enabled. |
| </p> |
| <p>Also no MIPS16 branches are ever relaxed. |
| </p> |
| <p>By default ‘<samp>--no-relax-branch</samp>’ is selected, causing any out-of-range |
| branches to produce an error. |
| </p> |
| <a name="index-_002dmnan_003d-command-line-option_002c-MIPS"></a> |
| </dd> |
| <dt><code>-mnan=<var>encoding</var></code></dt> |
| <dd><p>This option indicates whether the source code uses the IEEE 2008 |
| NaN encoding (<samp>-mnan=2008</samp>) or the original MIPS encoding |
| (<samp>-mnan=legacy</samp>). It is equivalent to adding a <code>.nan</code> |
| directive to the beginning of the source file. See <a href="MIPS-NaN-Encodings.html#MIPS-NaN-Encodings">MIPS NaN Encodings</a>. |
| </p> |
| <p><samp>-mnan=legacy</samp> is the default if no <samp>-mnan</samp> option or |
| <code>.nan</code> directive is used. |
| </p> |
| </dd> |
| <dt><code>--trap</code></dt> |
| <dt><code>--no-break</code></dt> |
| <dd><p><code>as</code> automatically macro expands certain division and |
| multiplication instructions to check for overflow and division by zero. This |
| option causes <code>as</code> to generate code to take a trap exception |
| rather than a break exception when an error is detected. The trap instructions |
| are only supported at Instruction Set Architecture level 2 and higher. |
| </p> |
| </dd> |
| <dt><code>--break</code></dt> |
| <dt><code>--no-trap</code></dt> |
| <dd><p>Generate code to take a break exception rather than a trap exception when an |
| error is detected. This is the default. |
| </p> |
| </dd> |
| <dt><code>-mpdr</code></dt> |
| <dt><code>-mno-pdr</code></dt> |
| <dd><p>Control generation of <code>.pdr</code> sections. Off by default on IRIX, on |
| elsewhere. |
| </p> |
| </dd> |
| <dt><code>-mshared</code></dt> |
| <dt><code>-mno-shared</code></dt> |
| <dd><p>When generating code using the Unix calling conventions (selected by |
| ‘<samp>-KPIC</samp>’ or ‘<samp>-mcall_shared</samp>’), gas will normally generate code |
| which can go into a shared library. The ‘<samp>-mno-shared</samp>’ option |
| tells gas to generate code which uses the calling convention, but can |
| not go into a shared library. The resulting code is slightly more |
| efficient. This option only affects the handling of the |
| ‘<samp>.cpload</samp>’ and ‘<samp>.cpsetup</samp>’ pseudo-ops. |
| </p></dd> |
| </dl> |
| |
| <hr> |
| <div class="header"> |
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