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<a name="Example"></a>
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<a name="Example-of-define_005finsn"></a>
<h3 class="section">16.3 Example of <code>define_insn</code></h3>
<a name="index-define_005finsn-example"></a>
<p>Here is an example of an instruction pattern, taken from the machine
description for the 68000/68020.
</p>
<div class="smallexample">
<pre class="smallexample">(define_insn &quot;tstsi&quot;
[(set (cc0)
(match_operand:SI 0 &quot;general_operand&quot; &quot;rm&quot;))]
&quot;&quot;
&quot;*
{
if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
return \&quot;tstl %0\&quot;;
return \&quot;cmpl #0,%0\&quot;;
}&quot;)
</pre></div>
<p>This can also be written using braced strings:
</p>
<div class="smallexample">
<pre class="smallexample">(define_insn &quot;tstsi&quot;
[(set (cc0)
(match_operand:SI 0 &quot;general_operand&quot; &quot;rm&quot;))]
&quot;&quot;
{
if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
return &quot;tstl %0&quot;;
return &quot;cmpl #0,%0&quot;;
})
</pre></div>
<p>This describes an instruction which sets the condition codes based on the
value of a general operand. It has no condition, so any insn with an RTL
description of the form shown may be matched to this pattern. The name
&lsquo;<samp>tstsi</samp>&rsquo; means &ldquo;test a <code>SImode</code> value&rdquo; and tells the RTL
generation pass that, when it is necessary to test such a value, an insn
to do so can be constructed using this pattern.
</p>
<p>The output control string is a piece of C code which chooses which
output template to return based on the kind of operand and the specific
type of CPU for which code is being generated.
</p>
<p>&lsquo;<samp>&quot;rm&quot;</samp>&rsquo; is an operand constraint. Its meaning is explained below.
</p>
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