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| <a name="ARM"></a> |
| <div class="header"> |
| <p> |
| Next: <a href="HPPA-ELF32.html#HPPA-ELF32" accesskey="n" rel="next">HPPA ELF32</a>, Previous: <a href="M68HC11_002f68HC12.html#M68HC11_002f68HC12" accesskey="p" rel="prev">M68HC11/68HC12</a>, Up: <a href="Machine-Dependent.html#Machine-Dependent" accesskey="u" rel="up">Machine Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="LD-Index.html#LD-Index" title="Index" rel="index">Index</a>]</p> |
| </div> |
| <hr> |
| <a name="ld-and-the-ARM-family"></a> |
| <h3 class="section">4.4 <code>ld</code> and the ARM family</h3> |
| |
| <a name="index-ARM-interworking-support"></a> |
| <a name="index-_002d_002dsupport_002dold_002dcode"></a> |
| <p>For the ARM, <code>ld</code> will generate code stubs to allow functions calls |
| between ARM and Thumb code. These stubs only work with code that has |
| been compiled and assembled with the ‘<samp>-mthumb-interwork</samp>’ command |
| line option. If it is necessary to link with old ARM object files or |
| libraries, which have not been compiled with the -mthumb-interwork |
| option then the ‘<samp>--support-old-code</samp>’ command line switch should be |
| given to the linker. This will make it generate larger stub functions |
| which will work with non-interworking aware ARM code. Note, however, |
| the linker does not support generating stubs for function calls to |
| non-interworking aware Thumb code. |
| </p> |
| <a name="index-thumb-entry-point"></a> |
| <a name="index-entry-point_002c-thumb"></a> |
| <a name="index-_002d_002dthumb_002dentry_003dentry"></a> |
| <p>The ‘<samp>--thumb-entry</samp>’ switch is a duplicate of the generic |
| ‘<samp>--entry</samp>’ switch, in that it sets the program’s starting address. |
| But it also sets the bottom bit of the address, so that it can be |
| branched to using a BX instruction, and the program will start |
| executing in Thumb mode straight away. |
| </p> |
| <a name="index-PE-import-table-prefixing"></a> |
| <a name="index-_002d_002duse_002dnul_002dprefixed_002dimport_002dtables"></a> |
| <p>The ‘<samp>--use-nul-prefixed-import-tables</samp>’ switch is specifying, that |
| the import tables idata4 and idata5 have to be generated with a zero |
| element prefix for import libraries. This is the old style to generate |
| import tables. By default this option is turned off. |
| </p> |
| <a name="index-BE8"></a> |
| <a name="index-_002d_002dbe8"></a> |
| <p>The ‘<samp>--be8</samp>’ switch instructs <code>ld</code> to generate BE8 format |
| executables. This option is only valid when linking big-endian objects. |
| The resulting image will contain big-endian data and little-endian code. |
| </p> |
| <a name="index-TARGET1"></a> |
| <a name="index-_002d_002dtarget1_002drel"></a> |
| <a name="index-_002d_002dtarget1_002dabs"></a> |
| <p>The ‘<samp>R_ARM_TARGET1</samp>’ relocation is typically used for entries in the |
| ‘<samp>.init_array</samp>’ section. It is interpreted as either ‘<samp>R_ARM_REL32</samp>’ |
| or ‘<samp>R_ARM_ABS32</samp>’, depending on the target. The ‘<samp>--target1-rel</samp>’ |
| and ‘<samp>--target1-abs</samp>’ switches override the default. |
| </p> |
| <a name="index-TARGET2"></a> |
| <a name="index-_002d_002dtarget2_003dtype"></a> |
| <p>The ‘<samp>--target2=type</samp>’ switch overrides the default definition of the |
| ‘<samp>R_ARM_TARGET2</samp>’ relocation. Valid values for ‘<samp>type</samp>’, their |
| meanings, and target defaults are as follows: |
| </p><dl compact="compact"> |
| <dt>‘<samp>rel</samp>’</dt> |
| <dd><p>‘<samp>R_ARM_REL32</samp>’ (arm*-*-elf, arm*-*-eabi) |
| </p></dd> |
| <dt>‘<samp>abs</samp>’</dt> |
| <dd><p>‘<samp>R_ARM_ABS32</samp>’ (arm*-*-symbianelf) |
| </p></dd> |
| <dt>‘<samp>got-rel</samp>’</dt> |
| <dd><p>‘<samp>R_ARM_GOT_PREL</samp>’ (arm*-*-linux, arm*-*-*bsd) |
| </p></dd> |
| </dl> |
| |
| <a name="index-FIX_005fV4BX"></a> |
| <a name="index-_002d_002dfix_002dv4bx"></a> |
| <p>The ‘<samp>R_ARM_V4BX</samp>’ relocation (defined by the ARM AAELF |
| specification) enables objects compiled for the ARMv4 architecture to be |
| interworking-safe when linked with other objects compiled for ARMv4t, but |
| also allows pure ARMv4 binaries to be built from the same ARMv4 objects. |
| </p> |
| <p>In the latter case, the switch <samp>--fix-v4bx</samp> must be passed to the |
| linker, which causes v4t <code>BX rM</code> instructions to be rewritten as |
| <code>MOV PC,rM</code>, since v4 processors do not have a <code>BX</code> instruction. |
| </p> |
| <p>In the former case, the switch should not be used, and ‘<samp>R_ARM_V4BX</samp>’ |
| relocations are ignored. |
| </p> |
| <a name="index-FIX_005fV4BX_005fINTERWORKING"></a> |
| <a name="index-_002d_002dfix_002dv4bx_002dinterworking"></a> |
| <p>Replace <code>BX rM</code> instructions identified by ‘<samp>R_ARM_V4BX</samp>’ |
| relocations with a branch to the following veneer: |
| </p> |
| <div class="smallexample"> |
| <pre class="smallexample">TST rM, #1 |
| MOVEQ PC, rM |
| BX Rn |
| </pre></div> |
| |
| <p>This allows generation of libraries/applications that work on ARMv4 cores |
| and are still interworking safe. Note that the above veneer clobbers the |
| condition flags, so may cause incorrect program behavior in rare cases. |
| </p> |
| <a name="index-USE_005fBLX"></a> |
| <a name="index-_002d_002duse_002dblx"></a> |
| <p>The ‘<samp>--use-blx</samp>’ switch enables the linker to use ARM/Thumb |
| BLX instructions (available on ARMv5t and above) in various |
| situations. Currently it is used to perform calls via the PLT from Thumb |
| code using BLX rather than using BX and a mode-switching stub before |
| each PLT entry. This should lead to such calls executing slightly faster. |
| </p> |
| <p>This option is enabled implicitly for SymbianOS, so there is no need to |
| specify it if you are using that target. |
| </p> |
| <a name="index-VFP11_005fDENORM_005fFIX"></a> |
| <a name="index-_002d_002dvfp11_002ddenorm_002dfix"></a> |
| <p>The ‘<samp>--vfp11-denorm-fix</samp>’ switch enables a link-time workaround for a |
| bug in certain VFP11 coprocessor hardware, which sometimes allows |
| instructions with denorm operands (which must be handled by support code) |
| to have those operands overwritten by subsequent instructions before |
| the support code can read the intended values. |
| </p> |
| <p>The bug may be avoided in scalar mode if you allow at least one |
| intervening instruction between a VFP11 instruction which uses a register |
| and another instruction which writes to the same register, or at least two |
| intervening instructions if vector mode is in use. The bug only affects |
| full-compliance floating-point mode: you do not need this workaround if |
| you are using "runfast" mode. Please contact ARM for further details. |
| </p> |
| <p>If you know you are using buggy VFP11 hardware, you can |
| enable this workaround by specifying the linker option |
| ‘<samp>--vfp-denorm-fix=scalar</samp>’ if you are using the VFP11 scalar |
| mode only, or ‘<samp>--vfp-denorm-fix=vector</samp>’ if you are using |
| vector mode (the latter also works for scalar code). The default is |
| ‘<samp>--vfp-denorm-fix=none</samp>’. |
| </p> |
| <p>If the workaround is enabled, instructions are scanned for |
| potentially-troublesome sequences, and a veneer is created for each |
| such sequence which may trigger the erratum. The veneer consists of the |
| first instruction of the sequence and a branch back to the subsequent |
| instruction. The original instruction is then replaced with a branch to |
| the veneer. The extra cycles required to call and return from the veneer |
| are sufficient to avoid the erratum in both the scalar and vector cases. |
| </p> |
| <a name="index-ARM1176-erratum-workaround"></a> |
| <a name="index-_002d_002dfix_002darm1176"></a> |
| <a name="index-_002d_002dno_002dfix_002darm1176"></a> |
| <p>The ‘<samp>--fix-arm1176</samp>’ switch enables a link-time workaround for an erratum |
| in certain ARM1176 processors. The workaround is enabled by default if you |
| are targeting ARM v6 (excluding ARM v6T2) or earlier. It can be disabled |
| unconditionally by specifying ‘<samp>--no-fix-arm1176</samp>’. |
| </p> |
| <p>Further information is available in the “ARM1176JZ-S and ARM1176JZF-S |
| Programmer Advice Notice” available on the ARM documentation website at: |
| http://infocenter.arm.com/. |
| </p> |
| <a name="index-NO_005fENUM_005fSIZE_005fWARNING"></a> |
| <a name="index-_002d_002dno_002denum_002dsize_002dwarning"></a> |
| <p>The <samp>--no-enum-size-warning</samp> switch prevents the linker from |
| warning when linking object files that specify incompatible EABI |
| enumeration size attributes. For example, with this switch enabled, |
| linking of an object file using 32-bit enumeration values with another |
| using enumeration values fitted into the smallest possible space will |
| not be diagnosed. |
| </p> |
| <a name="index-NO_005fWCHAR_005fSIZE_005fWARNING"></a> |
| <a name="index-_002d_002dno_002dwchar_002dsize_002dwarning"></a> |
| <p>The <samp>--no-wchar-size-warning</samp> switch prevents the linker from |
| warning when linking object files that specify incompatible EABI |
| <code>wchar_t</code> size attributes. For example, with this switch enabled, |
| linking of an object file using 32-bit <code>wchar_t</code> values with another |
| using 16-bit <code>wchar_t</code> values will not be diagnosed. |
| </p> |
| <a name="index-PIC_005fVENEER"></a> |
| <a name="index-_002d_002dpic_002dveneer"></a> |
| <p>The ‘<samp>--pic-veneer</samp>’ switch makes the linker use PIC sequences for |
| ARM/Thumb interworking veneers, even if the rest of the binary |
| is not PIC. This avoids problems on uClinux targets where |
| ‘<samp>--emit-relocs</samp>’ is used to generate relocatable binaries. |
| </p> |
| <a name="index-STUB_005fGROUP_005fSIZE"></a> |
| <a name="index-_002d_002dstub_002dgroup_002dsize_003dN"></a> |
| <p>The linker will automatically generate and insert small sequences of |
| code into a linked ARM ELF executable whenever an attempt is made to |
| perform a function call to a symbol that is too far away. The |
| placement of these sequences of instructions - called stubs - is |
| controlled by the command line option <samp>--stub-group-size=N</samp>. |
| The placement is important because a poor choice can create a need for |
| duplicate stubs, increasing the code size. The linker will try to |
| group stubs together in order to reduce interruptions to the flow of |
| code, but it needs guidance as to how big these groups should be and |
| where they should be placed. |
| </p> |
| <p>The value of ‘<samp>N</samp>’, the parameter to the |
| <samp>--stub-group-size=</samp> option controls where the stub groups are |
| placed. If it is negative then all stubs are placed after the first |
| branch that needs them. If it is positive then the stubs can be |
| placed either before or after the branches that need them. If the |
| value of ‘<samp>N</samp>’ is 1 (either +1 or -1) then the linker will choose |
| exactly where to place groups of stubs, using its built in heuristics. |
| A value of ‘<samp>N</samp>’ greater than 1 (or smaller than -1) tells the |
| linker that a single group of stubs can service at most ‘<samp>N</samp>’ bytes |
| from the input sections. |
| </p> |
| <p>The default, if <samp>--stub-group-size=</samp> is not specified, is |
| ‘<samp>N = +1</samp>’. |
| </p> |
| <p>Farcalls stubs insertion is fully supported for the ARM-EABI target |
| only, because it relies on object files properties not present |
| otherwise. |
| </p> |
| <a name="index-Cortex_002dA8-erratum-workaround"></a> |
| <a name="index-_002d_002dfix_002dcortex_002da8"></a> |
| <a name="index-_002d_002dno_002dfix_002dcortex_002da8"></a> |
| <p>The ‘<samp>--fix-cortex-a8</samp>’ switch enables a link-time workaround for an erratum in certain Cortex-A8 processors. The workaround is enabled by default if you are targeting the ARM v7-A architecture profile. It can be enabled otherwise by specifying ‘<samp>--fix-cortex-a8</samp>’, or disabled unconditionally by specifying ‘<samp>--no-fix-cortex-a8</samp>’. |
| </p> |
| <p>The erratum only affects Thumb-2 code. Please contact ARM for further details. |
| </p> |
| <a name="index-Cortex_002dA53-erratum-835769-workaround"></a> |
| <a name="index-_002d_002dfix_002dcortex_002da53_002d835769"></a> |
| <a name="index-_002d_002dno_002dfix_002dcortex_002da53_002d835769"></a> |
| <p>The ‘<samp>--fix-cortex-a53-835769</samp>’ switch enables a link-time workaround for erratum 835769 present on certain early revisions of Cortex-A53 processors. The workaround is disabled by default. It can be enabled by specifying ‘<samp>--fix-cortex-a53-835769</samp>’, or disabled unconditionally by specifying ‘<samp>--no-fix-cortex-a53-835769</samp>’. |
| </p> |
| <p>Please contact ARM for further details. |
| </p> |
| <a name="index-_002d_002dmerge_002dexidx_002dentries"></a> |
| <a name="index-_002d_002dno_002dmerge_002dexidx_002dentries-1"></a> |
| <a name="index-Merging-exidx-entries"></a> |
| <p>The ‘<samp>--no-merge-exidx-entries</samp>’ switch disables the merging of adjacent exidx entries in debuginfo. |
| </p> |
| <a name="index-_002d_002dlong_002dplt"></a> |
| <a name="index-32_002dbit-PLT-entries"></a> |
| <p>The ‘<samp>--long-plt</samp>’ option enables the use of 16 byte PLT entries |
| which support up to 4Gb of code. The default is to use 12 byte PLT |
| entries which only support 512Mb of code. |
| </p> |
| |
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| Next: <a href="HPPA-ELF32.html#HPPA-ELF32" accesskey="n" rel="next">HPPA ELF32</a>, Previous: <a href="M68HC11_002f68HC12.html#M68HC11_002f68HC12" accesskey="p" rel="prev">M68HC11/68HC12</a>, Up: <a href="Machine-Dependent.html#Machine-Dependent" accesskey="u" rel="up">Machine Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="LD-Index.html#LD-Index" title="Index" rel="index">Index</a>]</p> |
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