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This is as.info, produced by makeinfo version 5.2 from as.texinfo.
This file documents the GNU Assembler "as".
Copyright (C) 1991-2014 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3 or
any later version published by the Free Software Foundation; with no
Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
Texts. A copy of the license is included in the section entitled "GNU
Free Documentation License".
INFO-DIR-SECTION Software development
START-INFO-DIR-ENTRY
* As: (as). The GNU assembler.
* Gas: (as). The GNU assembler.
END-INFO-DIR-ENTRY

File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent
9.38.3 Instruction syntax
-------------------------
The assembler syntax closely follows the syntax outlined in Enterprise
Systems Architecture/390 Principles of Operation (SA22-7201) and the
z/Architecture Principles of Operation (SA22-7832).
Each instruction has two major parts, the instruction mnemonic and
the instruction operands. The instruction format varies.
* Menu:
* s390 Register:: Register Naming
* s390 Mnemonics:: Instruction Mnemonics
* s390 Operands:: Instruction Operands
* s390 Formats:: Instruction Formats
* s390 Aliases:: Instruction Aliases
* s390 Operand Modifier:: Instruction Operand Modifier
* s390 Instruction Marker:: Instruction Marker
* s390 Literal Pool Entries:: Literal Pool Entries

File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax
9.38.3.1 Register naming
........................
The 'as' recognizes a number of predefined symbols for the various
processor registers. A register specification in one of the instruction
formats is an unsigned integer between 0 and 15. The specific
instruction and the position of the register in the instruction format
denotes the type of the register. The register symbols are prefixed
with '%':
%rN the 16 general purpose registers, 0 <= N <= 15
%fN the 16 floating point registers, 0 <= N <= 15
%aN the 16 access registers, 0 <= N <= 15
%cN the 16 control registers, 0 <= N <= 15
%lit an alias for the general purpose register %r13
%sp an alias for the general purpose register %r15

File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax
9.38.3.2 Instruction Mnemonics
..............................
All instructions documented in the Principles of Operation are supported
with the mnemonic and order of operands as described. The instruction
mnemonic identifies the instruction format (*note s390 Formats::) and
the specific operation code for the instruction. For example, the 'lr'
mnemonic denotes the instruction format 'RR' with the operation code
'0x18'.
The definition of the various mnemonics follows a scheme, where the
first character usually hint at the type of the instruction:
a add instruction, for example 'al' for add logical 32-bit
b branch instruction, for example 'bc' for branch on condition
c compare or convert instruction, for example 'cr' for compare
register 32-bit
d divide instruction, for example 'dlr' devide logical register
64-bit to 32-bit
i insert instruction, for example 'ic' insert character
l load instruction, for example 'ltr' load and test register
mv move instruction, for example 'mvc' move character
m multiply instruction, for example 'mh' multiply halfword
n and instruction, for example 'ni' and immediate
o or instruction, for example 'oc' or character
sla, sll shift left single instruction
sra, srl shift right single instruction
st store instruction, for example 'stm' store multiple
s subtract instruction, for example 'slr' subtract
logical 32-bit
t test or translate instruction, of example 'tm' test under mask
x exclusive or instruction, for example 'xc' exclusive or
character
Certain characters at the end of the mnemonic may describe a property
of the instruction:
c the instruction uses a 8-bit character operand
f the instruction extends a 32-bit operand to 64 bit
g the operands are treated as 64-bit values
h the operand uses a 16-bit halfword operand
i the instruction uses an immediate operand
l the instruction uses unsigned, logical operands
m the instruction uses a mask or operates on multiple values
r if r is the last character, the instruction operates on registers
y the instruction uses 20-bit displacements
There are many exceptions to the scheme outlined in the above lists,
in particular for the priviledged instructions. For non-priviledged
instruction it works quite well, for example the instruction 'clgfr' c:
compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- to
64-bit extension, r: register operands. The instruction compares an
64-bit value in a register with the zero extended 32-bit value from a
second register. For a complete list of all mnemonics see appendix B in
the Principles of Operation.

File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax
9.38.3.3 Instruction Operands
.............................
Instruction operands can be grouped into three classes, operands located
in registers, immediate operands, and operands in storage.
A register operand can be located in general, floating-point, access,
or control register. The register is identified by a four-bit field.
The field containing the register operand is called the R field.
Immediate operands are contained within the instruction and can have
8, 16 or 32 bits. The field containing the immediate operand is called
the I field. Dependent on the instruction the I field is either signed
or unsigned.
A storage operand consists of an address and a length. The address
of a storage operands can be specified in any of these ways:
* The content of a single general R
* The sum of the content of a general register called the base
register B plus the content of a displacement field D
* The sum of the contents of two general registers called the index
register X and the base register B plus the content of a
displacement field
* The sum of the current instruction address and a 32-bit signed
immediate field multiplied by two.
The length of a storage operand can be:
* Implied by the instruction
* Specified by a bitmask
* Specified by a four-bit or eight-bit length field L
* Specified by the content of a general register
The notation for storage operand addresses formed from multiple
fields is as follows:
'Dn(Bn)'
the address for operand number n is formed from the content of
general register Bn called the base register and the displacement
field Dn.
'Dn(Xn,Bn)'
the address for operand number n is formed from the content of
general register Xn called the index register, general register Bn
called the base register and the displacement field Dn.
'Dn(Ln,Bn)'
the address for operand number n is formed from the content of
general regiser Bn called the base register and the displacement
field Dn. The length of the operand n is specified by the field
Ln.
The base registers Bn and the index registers Xn of a storage operand
can be skipped. If Bn and Xn are skipped, a zero will be stored to the
operand field. The notation changes as follows:
full notation short notation
----------------------------------------------
Dn(0,Bn) Dn(Bn)
Dn(0,0) Dn
Dn(0) Dn
Dn(Ln,0) Dn(Ln)

File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax
9.38.3.4 Instruction Formats
............................
The Principles of Operation manuals lists 26 instruction formats where
some of the formats have multiple variants. For the '.insn' pseudo
directive the assembler recognizes some of the formats. Typically, the
most general variant of the instruction format is used by the '.insn'
directive.
The following table lists the abbreviations used in the table of
instruction formats:
OpCode / OpCd Part of the op code.
Bx Base register number for operand x.
Dx Displacement for operand x.
DLx Displacement lower 12 bits for operand x.
DHx Displacement higher 8-bits for operand x.
Rx Register number for operand x.
Xx Index register number for operand x.
Ix Signed immediate for operand x.
Ux Unsigned immediate for operand x.
An instruction is two, four, or six bytes in length and must be
aligned on a 2 byte boundary. The first two bits of the instruction
specify the length of the instruction, 00 indicates a two byte
instruction, 01 and 10 indicates a four byte instruction, and 11
indicates a six byte instruction.
The following table lists the s390 instruction formats that are
available with the '.insn' pseudo directive:
'E format'
+-------------+
| OpCode |
+-------------+
0 15
'RI format: <insn> R1,I2'
+--------+----+----+------------------+
| OpCode | R1 |OpCd| I2 |
+--------+----+----+------------------+
0 8 12 16 31
'RIE format: <insn> R1,R3,I2'
+--------+----+----+------------------+--------+--------+
| OpCode | R1 | R3 | I2 |////////| OpCode |
+--------+----+----+------------------+--------+--------+
0 8 12 16 32 40 47
'RIL format: <insn> R1,I2'
+--------+----+----+------------------------------------+
| OpCode | R1 |OpCd| I2 |
+--------+----+----+------------------------------------+
0 8 12 16 47
'RILU format: <insn> R1,U2'
+--------+----+----+------------------------------------+
| OpCode | R1 |OpCd| U2 |
+--------+----+----+------------------------------------+
0 8 12 16 47
'RIS format: <insn> R1,I2,M3,D4(B4)'
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | M3 | B4 | D4 | I2 | Opcode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 36 47
'RR format: <insn> R1,R2'
+--------+----+----+
| OpCode | R1 | R2 |
+--------+----+----+
0 8 12 15
'RRE format: <insn> R1,R2'
+------------------+--------+----+----+
| OpCode |////////| R1 | R2 |
+------------------+--------+----+----+
0 16 24 28 31
'RRF format: <insn> R1,R2,R3,M4'
+------------------+----+----+----+----+
| OpCode | R3 | M4 | R1 | R2 |
+------------------+----+----+----+----+
0 16 20 24 28 31
'RRS format: <insn> R1,R2,M3,D4(B4)'
+--------+----+----+----+-------------+----+----+--------+
| OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode |
+--------+----+----+----+-------------+----+----+--------+
0 8 12 16 20 32 36 40 47
'RS format: <insn> R1,R3,D2(B2)'
+--------+----+----+----+-------------+
| OpCode | R1 | R3 | B2 | D2 |
+--------+----+----+----+-------------+
0 8 12 16 20 31
'RSE format: <insn> R1,R3,D2(B2)'
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | R3 | B2 | D2 |////////| OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 40 47
'RSI format: <insn> R1,R3,I2'
+--------+----+----+------------------------------------+
| OpCode | R1 | R3 | I2 |
+--------+----+----+------------------------------------+
0 8 12 16 47
'RSY format: <insn> R1,R3,D2(B2)'
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 40 47
'RX format: <insn> R1,D2(X2,B2)'
+--------+----+----+----+-------------+
| OpCode | R1 | X2 | B2 | D2 |
+--------+----+----+----+-------------+
0 8 12 16 20 31
'RXE format: <insn> R1,D2(X2,B2)'
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | X2 | B2 | D2 |////////| OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 40 47
'RXF format: <insn> R1,R3,D2(X2,B2)'
+--------+----+----+----+-------------+----+---+--------+
| OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode |
+--------+----+----+----+-------------+----+---+--------+
0 8 12 16 20 32 36 40 47
'RXY format: <insn> R1,D2(X2,B2)'
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 36 40 47
'S format: <insn> D2(B2)'
+------------------+----+-------------+
| OpCode | B2 | D2 |
+------------------+----+-------------+
0 16 20 31
'SI format: <insn> D1(B1),I2'
+--------+---------+----+-------------+
| OpCode | I2 | B1 | D1 |
+--------+---------+----+-------------+
0 8 16 20 31
'SIY format: <insn> D1(B1),U2'
+--------+---------+----+-------------+--------+--------+
| OpCode | I2 | B1 | DL1 | DH1 | OpCode |
+--------+---------+----+-------------+--------+--------+
0 8 16 20 32 36 40 47
'SIL format: <insn> D1(B1),I2'
+------------------+----+-------------+-----------------+
| OpCode | B1 | D1 | I2 |
+------------------+----+-------------+-----------------+
0 16 20 32 47
'SS format: <insn> D1(R1,B1),D2(B3),R3'
+--------+----+----+----+-------------+----+------------+
| OpCode | R1 | R3 | B1 | D1 | B2 | D2 |
+--------+----+----+----+-------------+----+------------+
0 8 12 16 20 32 36 47
'SSE format: <insn> D1(B1),D2(B2)'
+------------------+----+-------------+----+------------+
| OpCode | B1 | D1 | B2 | D2 |
+------------------+----+-------------+----+------------+
0 8 12 16 20 32 36 47
'SSF format: <insn> D1(B1),D2(B2),R3'
+--------+----+----+----+-------------+----+------------+
| OpCode | R3 |OpCd| B1 | D1 | B2 | D2 |
+--------+----+----+----+-------------+----+------------+
0 8 12 16 20 32 36 47
For the complete list of all instruction format variants see the
Principles of Operation manuals.

File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax
9.38.3.5 Instruction Aliases
............................
A specific bit pattern can have multiple mnemonics, for example the bit
pattern '0xa7000000' has the mnemonics 'tmh' and 'tmlh'. In addition,
there are a number of mnemonics recognized by 'as' that are not present
in the Principles of Operation. These are the short forms of the branch
instructions, where the condition code mask operand is encoded in the
mnemonic. This is relevant for the branch instructions, the compare and
branch instructions, and the compare and trap instructions.
For the branch instructions there are 20 condition code strings that
can be used as part of the mnemonic in place of a mask operand in the
instruction format:
instruction short form
----------------------------------------------
bcr M1,R2 b<m>r R2
bc M1,D2(X2,B2) b<m> D2(X2,B2)
brc M1,I2 j<m> I2
brcl M1,I2 jg<m> I2
In the mnemonic for a branch instruction the condition code string
<m> can be any of the following:
o jump on overflow / if ones
h jump on A high
p jump on plus
nle jump on not low or equal
l jump on A low
m jump on minus
nhe jump on not high or equal
lh jump on low or high
ne jump on A not equal B
nz jump on not zero / if not zeros
e jump on A equal B
z jump on zero / if zeroes
nlh jump on not low or high
he jump on high or equal
nl jump on A not low
nm jump on not minus / if not mixed
le jump on low or equal
nh jump on A not high
np jump on not plus
no jump on not overflow / if not ones
For the compare and branch, and compare and trap instructions there
are 12 condition code strings that can be used as part of the mnemonic
in place of a mask operand in the instruction format:
instruction short form
------------------------------------------------------------
crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4)
cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4)
crj R1,R2,M3,I4 crj<m> R1,R2,I4
cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4
cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4)
cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4)
cij R1,I2,M3,I4 cij<m> R1,I2,I4
cgij R1,I2,M3,I4 cgij<m> R1,I2,I4
crt R1,R2,M3 crt<m> R1,R2
cgrt R1,R2,M3 cgrt<m> R1,R2
cit R1,I2,M3 cit<m> R1,I2
cgit R1,I2,M3 cgit<m> R1,I2
clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4)
clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4)
clrj R1,R2,M3,I4 clrj<m> R1,R2,I4
clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4
clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4)
clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4)
clij R1,I2,M3,I4 clij<m> R1,I2,I4
clgij R1,I2,M3,I4 clgij<m> R1,I2,I4
clrt R1,R2,M3 clrt<m> R1,R2
clgrt R1,R2,M3 clgrt<m> R1,R2
clfit R1,I2,M3 clfit<m> R1,I2
clgit R1,I2,M3 clgit<m> R1,I2
In the mnemonic for a compare and branch and compare and trap
instruction the condition code string <m> can be any of the following:
h jump on A high
nle jump on not low or equal
l jump on A low
nhe jump on not high or equal
ne jump on A not equal B
lh jump on low or high
e jump on A equal B
nlh jump on not low or high
nl jump on A not low
he jump on high or equal
nh jump on A not high
le jump on low or equal

File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax
9.38.3.6 Instruction Operand Modifier
.....................................
If a symbol modifier is attached to a symbol in an expression for an
instruction operand field, the symbol term is replaced with a reference
to an object in the global offset table (GOT) or the procedure linkage
table (PLT). The following expressions are allowed: 'symbol@modifier +
constant', 'symbol@modifier + label + constant', and 'symbol@modifier -
label + constant'. The term 'symbol' is the symbol that will be entered
into the GOT or PLT, 'label' is a local label, and 'constant' is an
arbitrary expression that the assembler can evaluate to a constant
value.
The term '(symbol + constant1)@modifier +/- label + constant2' is
also accepted but a warning message is printed and the term is converted
to 'symbol@modifier +/- label + constant1 + constant2'.
'@got'
'@got12'
The @got modifier can be used for displacement fields, 16-bit
immediate fields and 32-bit pc-relative immediate fields. The
@got12 modifier is synonym to @got. The symbol is added to the
GOT. For displacement fields and 16-bit immediate fields the symbol
term is replaced with the offset from the start of the GOT to the
GOT slot for the symbol. For a 32-bit pc-relative field the
pc-relative offset to the GOT slot from the current instruction
address is used.
'@gotent'
The @gotent modifier can be used for 32-bit pc-relative immediate
fields. The symbol is added to the GOT and the symbol term is
replaced with the pc-relative offset from the current instruction
to the GOT slot for the symbol.
'@gotoff'
The @gotoff modifier can be used for 16-bit immediate fields. The
symbol term is replaced with the offset from the start of the GOT
to the address of the symbol.
'@gotplt'
The @gotplt modifier can be used for displacement fields, 16-bit
immediate fields, and 32-bit pc-relative immediate fields. A
procedure linkage table entry is generated for the symbol and a
jump slot for the symbol is added to the GOT. For displacement
fields and 16-bit immediate fields the symbol term is replaced with
the offset from the start of the GOT to the jump slot for the
symbol. For a 32-bit pc-relative field the pc-relative offset to
the jump slot from the current instruction address is used.
'@plt'
The @plt modifier can be used for 16-bit and 32-bit pc-relative
immediate fields. A procedure linkage table entry is generated for
the symbol. The symbol term is replaced with the relative offset
from the current instruction to the PLT entry for the symbol.
'@pltoff'
The @pltoff modifier can be used for 16-bit immediate fields. The
symbol term is replaced with the offset from the start of the PLT
to the address of the symbol.
'@gotntpoff'
The @gotntpoff modifier can be used for displacement fields. The
symbol is added to the static TLS block and the negated offset to
the symbol in the static TLS block is added to the GOT. The symbol
term is replaced with the offset to the GOT slot from the start of
the GOT.
'@indntpoff'
The @indntpoff modifier can be used for 32-bit pc-relative
immediate fields. The symbol is added to the static TLS block and
the negated offset to the symbol in the static TLS block is added
to the GOT. The symbol term is replaced with the pc-relative offset
to the GOT slot from the current instruction address.
For more information about the thread local storage modifiers
'gotntpoff' and 'indntpoff' see the ELF extension documentation 'ELF
Handling For Thread-Local Storage'.

File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax
9.38.3.7 Instruction Marker
...........................
The thread local storage instruction markers are used by the linker to
perform code optimization.
':tls_load'
The :tls_load marker is used to flag the load instruction in the
initial exec TLS model that retrieves the offset from the thread
pointer to a thread local storage variable from the GOT.
':tls_gdcall'
The :tls_gdcall marker is used to flag the branch-and-save
instruction to the __tls_get_offset function in the global dynamic
TLS model.
':tls_ldcall'
The :tls_ldcall marker is used to flag the branch-and-save
instruction to the __tls_get_offset function in the local dynamic
TLS model.
For more information about the thread local storage instruction
marker and the linker optimizations see the ELF extension documentation
'ELF Handling For Thread-Local Storage'.

File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax
9.38.3.8 Literal Pool Entries
.............................
A literal pool is a collection of values. To access the values a
pointer to the literal pool is loaded to a register, the literal pool
register. Usually, register %r13 is used as the literal pool register
(*note s390 Register::). Literal pool entries are created by adding the
suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an
instruction operand. The expression is added to the literal pool and
the operand is replaced with the offset to the literal in the literal
pool.
':lit1'
The literal pool entry is created as an 8-bit value. An operand
modifier must not be used for the original expression.
':lit2'
The literal pool entry is created as a 16 bit value. The operand
modifier @got may be used in the original expression. The term
'x@got:lit2' will put the got offset for the global symbol x to the
literal pool as 16 bit value.
':lit4'
The literal pool entry is created as a 32-bit value. The operand
modifier @got and @plt may be used in the original expression. The
term 'x@got:lit4' will put the got offset for the global symbol x
to the literal pool as a 32-bit value. The term 'x@plt:lit4' will
put the plt offset for the global symbol x to the literal pool as a
32-bit value.
':lit8'
The literal pool entry is created as a 64-bit value. The operand
modifier @got and @plt may be used in the original expression. The
term 'x@got:lit8' will put the got offset for the global symbol x
to the literal pool as a 64-bit value. The term 'x@plt:lit8' will
put the plt offset for the global symbol x to the literal pool as a
64-bit value.
The assembler directive '.ltorg' is used to emit all literal pool
entries to the current position.

File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent
9.38.4 Assembler Directives
---------------------------
'as' for s390 supports all of the standard ELF assembler directives as
outlined in the main part of this document. Some directives have been
extended and there are some additional directives, which are only
available for the s390 'as'.
'.insn'
This directive permits the numeric representation of an
instructions and makes the assembler insert the operands according
to one of the instructions formats for '.insn' (*note s390
Formats::). For example, the instruction 'l %r1,24(%r15)' could be
written as '.insn rx,0x58000000,%r1,24(%r15)'.
'.short'
'.long'
'.quad'
This directive places one or more 16-bit (.short), 32-bit (.long),
or 64-bit (.quad) values into the current section. If an ELF or
TLS modifier is used only the following expressions are allowed:
'symbol@modifier + constant', 'symbol@modifier + label + constant',
and 'symbol@modifier - label + constant'. The following modifiers
are available:
'@got'
'@got12'
The @got modifier can be used for .short, .long and .quad.
The @got12 modifier is synonym to @got. The symbol is added
to the GOT. The symbol term is replaced with offset from the
start of the GOT to the GOT slot for the symbol.
'@gotoff'
The @gotoff modifier can be used for .short, .long and .quad.
The symbol term is replaced with the offset from the start of
the GOT to the address of the symbol.
'@gotplt'
The @gotplt modifier can be used for .long and .quad. A
procedure linkage table entry is generated for the symbol and
a jump slot for the symbol is added to the GOT. The symbol
term is replaced with the offset from the start of the GOT to
the jump slot for the symbol.
'@plt'
The @plt modifier can be used for .long and .quad. A
procedure linkage table entry us generated for the symbol.
The symbol term is replaced with the address of the PLT entry
for the symbol.
'@pltoff'
The @pltoff modifier can be used for .short, .long and .quad.
The symbol term is replaced with the offset from the start of
the PLT to the address of the symbol.
'@tlsgd'
'@tlsldm'
The @tlsgd and @tlsldm modifier can be used for .long and
.quad. A tls_index structure for the symbol is added to the
GOT. The symbol term is replaced with the offset from the
start of the GOT to the tls_index structure.
'@gotntpoff'
'@indntpoff'
The @gotntpoff and @indntpoff modifier can be used for .long
and .quad. The symbol is added to the static TLS block and
the negated offset to the symbol in the static TLS block is
added to the GOT. For @gotntpoff the symbol term is replaced
with the offset from the start of the GOT to the GOT slot, for
@indntpoff the symbol term is replaced with the address of the
GOT slot.
'@dtpoff'
The @dtpoff modifier can be used for .long and .quad. The
symbol term is replaced with the offset of the symbol relative
to the start of the TLS block it is contained in.
'@ntpoff'
The @ntpoff modifier can be used for .long and .quad. The
symbol term is replaced with the offset of the symbol relative
to the TCB pointer.
For more information about the thread local storage modifiers see
the ELF extension documentation 'ELF Handling For Thread-Local
Storage'.
'.ltorg'
This directive causes the current contents of the literal pool to
be dumped to the current location (*note s390 Literal Pool
Entries::).
'.machine string'
This directive allows you to change the machine for which code is
generated. 'string' may be any of the '-march=' selection options
(without the -march=), 'push', or 'pop'. '.machine push' saves the
currently selected cpu, which may be restored with '.machine pop'.
Be aware that the cpu string has to be put into double quotes in
case it contains characters not appropriate for identifiers. So
you have to write '"z9-109"' instead of just 'z9-109'.
'.machinemode string'
This directive allows to change the architecture mode for which
code is being generated. 'string' may be 'esa', 'zarch',
'zarch_nohighgprs', 'push', or 'pop'. '.machinemode
zarch_nohighgprs' can be used to prevent the 'highgprs' flag from
being set in the ELF header of the output file. This is useful in
situations where the code is gated with a runtime check which makes
sure that the code is only executed on kernels providing the
'highgprs' feature. '.machinemode push' saves the currently
selected mode, which may be restored with '.machinemode pop'.

File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent
9.38.5 Floating Point
---------------------
The assembler recognizes both the IEEE floating-point instruction and
the hexadecimal floating-point instructions. The floating-point
constructors '.float', '.single', and '.double' always emit the IEEE
format. To assemble hexadecimal floating-point constants the '.long'
and '.quad' directives must be used.

File: as.info, Node: SCORE-Dependent, Next: SH-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies
9.39 SCORE Dependent Features
=============================
* Menu:
* SCORE-Opts:: Assembler options
* SCORE-Pseudo:: SCORE Assembler Directives
* SCORE-Syntax:: Syntax

File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent
9.39.1 Options
--------------
The following table lists all available SCORE options.
'-G NUM'
This option sets the largest size of an object that can be
referenced implicitly with the 'gp' register. The default value is
8.
'-EB'
Assemble code for a big-endian cpu
'-EL'
Assemble code for a little-endian cpu
'-FIXDD'
Assemble code for fix data dependency
'-NWARN'
Assemble code for no warning message for fix data dependency
'-SCORE5'
Assemble code for target is SCORE5
'-SCORE5U'
Assemble code for target is SCORE5U
'-SCORE7'
Assemble code for target is SCORE7, this is default setting
'-SCORE3'
Assemble code for target is SCORE3
'-march=score7'
Assemble code for target is SCORE7, this is default setting
'-march=score3'
Assemble code for target is SCORE3
'-USE_R1'
Assemble code for no warning message when using temp register r1
'-KPIC'
Generate code for PIC. This option tells the assembler to generate
score position-independent macro expansions. It also tells the
assembler to mark the output file as PIC.
'-O0'
Assembler will not perform any optimizations
'-V'
Sunplus release version

File: as.info, Node: SCORE-Pseudo, Next: SCORE-Syntax, Prev: SCORE-Opts, Up: SCORE-Dependent
9.39.2 SCORE Assembler Directives
---------------------------------
A number of assembler directives are available for SCORE. The following
table is far from complete.
'.set nwarn'
Let the assembler not to generate warnings if the source machine
language instructions happen data dependency.
'.set fixdd'
Let the assembler to insert bubbles (32 bit nop instruction / 16
bit nop! Instruction) if the source machine language instructions
happen data dependency.
'.set nofixdd'
Let the assembler to generate warnings if the source machine
language instructions happen data dependency. (Default)
'.set r1'
Let the assembler not to generate warnings if the source program
uses r1. allow user to use r1
'set nor1'
Let the assembler to generate warnings if the source program uses
r1. (Default)
'.sdata'
Tell the assembler to add subsequent data into the sdata section
'.rdata'
Tell the assembler to add subsequent data into the rdata section
'.frame "frame-register", "offset", "return-pc-register"'
Describe a stack frame. "frame-register" is the frame register,
"offset" is the distance from the frame register to the virtual
frame pointer, "return-pc-register" is the return program register.
You must use ".ent" before ".frame" and only one ".frame" can be
used per ".ent".
'.mask "bitmask", "frameoffset"'
Indicate which of the integer registers are saved in the current
function's stack frame, this is for the debugger to explain the
frame chain.
'.ent "proc-name"'
Set the beginning of the procedure "proc_name". Use this directive
when you want to generate information for the debugger.
'.end proc-name'
Set the end of a procedure. Use this directive to generate
information for the debugger.
'.bss'
Switch the destination of following statements into the bss
section, which is used for data that is uninitialized anywhere.

File: as.info, Node: SCORE-Syntax, Prev: SCORE-Pseudo, Up: SCORE-Dependent
9.39.3 SCORE Syntax
-------------------
* Menu:
* SCORE-Chars:: Special Characters

File: as.info, Node: SCORE-Chars, Up: SCORE-Syntax
9.39.3.1 Special Characters
...........................
The presence of a '#' appearing anywhere on a line indicates the start
of a comment that extends to the end of that line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
The ';' character can be used to separate statements on the same
line.

File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies
9.40 Renesas / SuperH SH Dependent Features
===========================================
* Menu:
* SH Options:: Options
* SH Syntax:: Syntax
* SH Floating Point:: Floating Point
* SH Directives:: SH Machine Directives
* SH Opcodes:: Opcodes

File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent
9.40.1 Options
--------------
'as' has following command-line options for the Renesas (formerly
Hitachi) / SuperH SH family.
'--little'
Generate little endian code.
'--big'
Generate big endian code.
'--relax'
Alter jump instructions for long displacements.
'--small'
Align sections to 4 byte boundaries, not 16.
'--dsp'
Enable sh-dsp insns, and disable sh3e / sh4 insns.
'--renesas'
Disable optimization with section symbol for compatibility with
Renesas assembler.
'--allow-reg-prefix'
Allow '$' as a register name prefix.
'--fdpic'
Generate an FDPIC object file.
'--isa=sh4 | sh4a'
Specify the sh4 or sh4a instruction set.
'--isa=dsp'
Enable sh-dsp insns, and disable sh3e / sh4 insns.
'--isa=fp'
Enable sh2e, sh3e, sh4, and sh4a insn sets.
'--isa=all'
Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
'-h-tick-hex'
Support H'00 style hex constants in addition to 0x00 style.

File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent
9.40.2 Syntax
-------------
* Menu:
* SH-Chars:: Special Characters
* SH-Regs:: Register Names
* SH-Addressing:: Addressing Modes

File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax
9.40.2.1 Special Characters
...........................
'!' is the line comment character.
You can use ';' instead of a newline to separate statements.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line could also be a
logical line number directive (*note Comments::) or a preprocessor
control command (*note Preprocessing::).
Since '$' has no special meaning, you may use it in symbol names.

File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax
9.40.2.2 Register Names
.......................
You can use the predefined symbols 'r0', 'r1', 'r2', 'r3', 'r4', 'r5',
'r6', 'r7', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', and 'r15' to
refer to the SH registers.
The SH also has these control registers:
'pr'
procedure register (holds return address)
'pc'
program counter
'mach'
'macl'
high and low multiply accumulator registers
'sr'
status register
'gbr'
global base register
'vbr'
vector base register (for interrupt vectors)

File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax
9.40.2.3 Addressing Modes
.........................
'as' understands the following addressing modes for the SH. 'RN' in the
following refers to any of the numbered registers, but _not_ the control
registers.
'RN'
Register direct
'@RN'
Register indirect
'@-RN'
Register indirect with pre-decrement
'@RN+'
Register indirect with post-increment
'@(DISP, RN)'
Register indirect with displacement
'@(R0, RN)'
Register indexed
'@(DISP, GBR)'
'GBR' offset
'@(R0, GBR)'
GBR indexed
'ADDR'
'@(DISP, PC)'
PC relative address (for branch or for addressing memory). The
'as' implementation allows you to use the simpler form ADDR
anywhere a PC relative address is called for; the alternate form is
supported for compatibility with other assemblers.
'#IMM'
Immediate data

File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent
9.40.3 Floating Point
---------------------
SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
SH groups can use '.float' directive to generate IEEE floating-point
numbers.
SH2E and SH3E support single-precision floating point calculations as
well as entirely PCAPI compatible emulation of double-precision floating
point calculations. SH2E and SH3E instructions are a subset of the
floating point calculations conforming to the IEEE754 standard.
In addition to single-precision and double-precision floating-point
operation capability, the on-chip FPU of SH4 has a 128-bit graphic
engine that enables 32-bit floating-point data to be processed 128 bits
at a time. It also supports 4 * 4 array operations and inner product
operations. Also, a superscalar architecture is employed that enables
simultaneous execution of two instructions (including FPU instructions),
providing performance of up to twice that of conventional architectures
at the same frequency.

File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent
9.40.4 SH Machine Directives
----------------------------
'uaword'
'ualong'
'uaquad'
'as' will issue a warning when a misaligned '.word', '.long', or
'.quad' directive is used. You may use '.uaword', '.ualong', or
'.uaquad' to indicate that the value is intentionally misaligned.

File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent
9.40.5 Opcodes
--------------
For detailed information on the SH machine instruction set, see
'SH-Microcomputer User's Manual' (Renesas) or 'SH-4 32-bit CPU Core
Architecture' (SuperH) and 'SuperH (SH) 64-Bit RISC Series' (SuperH).
'as' implements all the standard SH opcodes. No additional
pseudo-instructions are needed on this family. Note, however, that
because 'as' supports a simpler form of PC-relative addressing, you may
simply write (for example)
mov.l bar,r0
where other assemblers might require an explicit displacement to 'bar'
from the program counter:
mov.l @(DISP, PC)
Here is a summary of SH opcodes:
Legend:
Rn a numbered register
Rm another numbered register
#imm immediate data
disp displacement
disp8 8-bit displacement
disp12 12-bit displacement
add #imm,Rn lds.l @Rn+,PR
add Rm,Rn mac.w @Rm+,@Rn+
addc Rm,Rn mov #imm,Rn
addv Rm,Rn mov Rm,Rn
and #imm,R0 mov.b Rm,@(R0,Rn)
and Rm,Rn mov.b Rm,@-Rn
and.b #imm,@(R0,GBR) mov.b Rm,@Rn
bf disp8 mov.b @(disp,Rm),R0
bra disp12 mov.b @(disp,GBR),R0
bsr disp12 mov.b @(R0,Rm),Rn
bt disp8 mov.b @Rm+,Rn
clrmac mov.b @Rm,Rn
clrt mov.b R0,@(disp,Rm)
cmp/eq #imm,R0 mov.b R0,@(disp,GBR)
cmp/eq Rm,Rn mov.l Rm,@(disp,Rn)
cmp/ge Rm,Rn mov.l Rm,@(R0,Rn)
cmp/gt Rm,Rn mov.l Rm,@-Rn
cmp/hi Rm,Rn mov.l Rm,@Rn
cmp/hs Rm,Rn mov.l @(disp,Rn),Rm
cmp/pl Rn mov.l @(disp,GBR),R0
cmp/pz Rn mov.l @(disp,PC),Rn
cmp/str Rm,Rn mov.l @(R0,Rm),Rn
div0s Rm,Rn mov.l @Rm+,Rn
div0u mov.l @Rm,Rn
div1 Rm,Rn mov.l R0,@(disp,GBR)
exts.b Rm,Rn mov.w Rm,@(R0,Rn)
exts.w Rm,Rn mov.w Rm,@-Rn
extu.b Rm,Rn mov.w Rm,@Rn
extu.w Rm,Rn mov.w @(disp,Rm),R0
jmp @Rn mov.w @(disp,GBR),R0
jsr @Rn mov.w @(disp,PC),Rn
ldc Rn,GBR mov.w @(R0,Rm),Rn
ldc Rn,SR mov.w @Rm+,Rn
ldc Rn,VBR mov.w @Rm,Rn
ldc.l @Rn+,GBR mov.w R0,@(disp,Rm)
ldc.l @Rn+,SR mov.w R0,@(disp,GBR)
ldc.l @Rn+,VBR mova @(disp,PC),R0
lds Rn,MACH movt Rn
lds Rn,MACL muls Rm,Rn
lds Rn,PR mulu Rm,Rn
lds.l @Rn+,MACH neg Rm,Rn
lds.l @Rn+,MACL negc Rm,Rn
nop stc VBR,Rn
not Rm,Rn stc.l GBR,@-Rn
or #imm,R0 stc.l SR,@-Rn
or Rm,Rn stc.l VBR,@-Rn
or.b #imm,@(R0,GBR) sts MACH,Rn
rotcl Rn sts MACL,Rn
rotcr Rn sts PR,Rn
rotl Rn sts.l MACH,@-Rn
rotr Rn sts.l MACL,@-Rn
rte sts.l PR,@-Rn
rts sub Rm,Rn
sett subc Rm,Rn
shal Rn subv Rm,Rn
shar Rn swap.b Rm,Rn
shll Rn swap.w Rm,Rn
shll16 Rn tas.b @Rn
shll2 Rn trapa #imm
shll8 Rn tst #imm,R0
shlr Rn tst Rm,Rn
shlr16 Rn tst.b #imm,@(R0,GBR)
shlr2 Rn xor #imm,R0
shlr8 Rn xor Rm,Rn
sleep xor.b #imm,@(R0,GBR)
stc GBR,Rn xtrct Rm,Rn
stc SR,Rn

File: as.info, Node: SH64-Dependent, Next: Sparc-Dependent, Prev: SH-Dependent, Up: Machine Dependencies
9.41 SuperH SH64 Dependent Features
===================================
* Menu:
* SH64 Options:: Options
* SH64 Syntax:: Syntax
* SH64 Directives:: SH64 Machine Directives
* SH64 Opcodes:: Opcodes

File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent
9.41.1 Options
--------------
'-isa=sh4 | sh4a'
Specify the sh4 or sh4a instruction set.
'-isa=dsp'
Enable sh-dsp insns, and disable sh3e / sh4 insns.
'-isa=fp'
Enable sh2e, sh3e, sh4, and sh4a insn sets.
'-isa=all'
Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
'-isa=shmedia | -isa=shcompact'
Specify the default instruction set. 'SHmedia' specifies the
32-bit opcodes, and 'SHcompact' specifies the 16-bit opcodes
compatible with previous SH families. The default depends on the
ABI selected; the default for the 64-bit ABI is SHmedia, and the
default for the 32-bit ABI is SHcompact. If neither the ABI nor
the ISA is specified, the default is 32-bit SHcompact.
Note that the '.mode' pseudo-op is not permitted if the ISA is not
specified on the command line.
'-abi=32 | -abi=64'
Specify the default ABI. If the ISA is specified and the ABI is
not, the default ABI depends on the ISA, with SHmedia defaulting to
64-bit and SHcompact defaulting to 32-bit.
Note that the '.abi' pseudo-op is not permitted if the ABI is not
specified on the command line. When the ABI is specified on the
command line, any '.abi' pseudo-ops in the source must match it.
'-shcompact-const-crange'
Emit code-range descriptors for constants in SHcompact code
sections.
'-no-mix'
Disallow SHmedia code in the same section as constants and
SHcompact code.
'-no-expand'
Do not expand MOVI, PT, PTA or PTB instructions.
'-expand-pt32'
With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.
'-h-tick-hex'
Support H'00 style hex constants in addition to 0x00 style.

File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent
9.41.2 Syntax
-------------
* Menu:
* SH64-Chars:: Special Characters
* SH64-Regs:: Register Names
* SH64-Addressing:: Addressing Modes

File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax
9.41.2.1 Special Characters
...........................
'!' is the line comment character.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line could also be a
logical line number directive (*note Comments::) or a preprocessor
control command (*note Preprocessing::).
You can use ';' instead of a newline to separate statements.
Since '$' has no special meaning, you may use it in symbol names.

File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax
9.41.2.2 Register Names
.......................
You can use the predefined symbols 'r0' through 'r63' to refer to the
SH64 general registers, 'cr0' through 'cr63' for control registers,
'tr0' through 'tr7' for target address registers, 'fr0' through 'fr63'
for single-precision floating point registers, 'dr0' through 'dr62'
(even numbered registers only) for double-precision floating point
registers, 'fv0' through 'fv60' (multiples of four only) for
single-precision floating point vectors, 'fp0' through 'fp62' (even
numbered registers only) for single-precision floating point pairs,
'mtrx0' through 'mtrx48' (multiples of 16 only) for 4x4 matrices of
single-precision floating point registers, 'pc' for the program counter,
and 'fpscr' for the floating point status and control register.
You can also refer to the control registers by the mnemonics 'sr',
'ssr', 'pssr', 'intevt', 'expevt', 'pexpevt', 'tra', 'spc', 'pspc',
'resvec', 'vbr', 'tea', 'dcr', 'kcr0', 'kcr1', 'ctc', and 'usr'.

File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax
9.41.2.3 Addressing Modes
.........................
SH64 operands consist of either a register or immediate value. The
immediate value can be a constant or label reference (or portion of a
label reference), as in this example:
movi 4,r2
pt function, tr4
movi (function >> 16) & 65535,r0
shori function & 65535, r0
ld.l r0,4,r0
Instruction label references can reference labels in either SHmedia
or SHcompact. To differentiate between the two, labels in SHmedia
sections will always have the least significant bit set (i.e. they will
be odd), which SHcompact labels will have the least significant bit
reset (i.e. they will be even). If you need to reference the actual
address of a label, you can use the 'datalabel' modifier, as in this
example:
.long function
.long datalabel function
In that example, the first longword may or may not have the least
significant bit set depending on whether the label is an SHmedia label
or an SHcompact label. The second longword will be the actual address
of the label, regardless of what type of label it is.

File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, Up: SH64-Dependent
9.41.3 SH64 Machine Directives
------------------------------
In addition to the SH directives, the SH64 provides the following
directives:
'.mode [shmedia|shcompact]'
'.isa [shmedia|shcompact]'
Specify the ISA for the following instructions (the two directives
are equivalent). Note that programs such as 'objdump' rely on
symbolic labels to determine when such mode switches occur (by
checking the least significant bit of the label's address), so such
mode/isa changes should always be followed by a label (in practice,
this is true anyway). Note that you cannot use these directives if
you didn't specify an ISA on the command line.
'.abi [32|64]'
Specify the ABI for the following instructions. Note that you
cannot use this directive unless you specified an ABI on the
command line, and the ABIs specified must match.

File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent
9.41.4 Opcodes
--------------
For detailed information on the SH64 machine instruction set, see
'SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.).
'as' implements all the standard SH64 opcodes. In addition, the
following pseudo-opcodes may be expanded into one or more alternate
opcodes:
'movi'
If the value doesn't fit into a standard 'movi' opcode, 'as' will
replace the 'movi' with a sequence of 'movi' and 'shori' opcodes.
'pt'
This expands to a sequence of 'movi' and 'shori' opcode, followed
by a 'ptrel' opcode, or to a 'pta' or 'ptb' opcode, depending on
the label referenced.

File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies
9.42 SPARC Dependent Features
=============================
* Menu:
* Sparc-Opts:: Options
* Sparc-Aligned-Data:: Option to enforce aligned data
* Sparc-Syntax:: Syntax
* Sparc-Float:: Floating Point
* Sparc-Directives:: Sparc Machine Directives

File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent
9.42.1 Options
--------------
The SPARC chip family includes several successive versions, using the
same core instruction set, but including a few additional instructions
at each version. There are exceptions to this however. For details on
what instructions each variant supports, please see the chip's
architecture reference manual.
By default, 'as' assumes the core instruction set (SPARC v6), but
"bumps" the architecture level as needed: it switches to successively
higher architectures as it encounters instructions that only exist in
the higher levels.
If not configured for SPARC v9 ('sparc64-*-*') GAS will not bump past
sparclite by default, an option must be passed to enable the v9
instructions.
GAS treats sparclite as being compatible with v8, unless an
architecture is explicitly requested. SPARC v9 is always incompatible
with sparclite.
'-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite'
'-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv'
'-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m'
'-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima'
'-Asparcvis3 | -Asparcvis3r'
Use one of the '-A' options to select one of the SPARC
architectures explicitly. If you select an architecture
explicitly, 'as' reports a fatal error if it encounters an
instruction or feature requiring an incompatible or higher level.
'-Av8plus', '-Av8plusa', '-Av8plusb', '-Av8plusc', '-Av8plusd', and
'-Av8plusv' select a 32 bit environment.
'-Av9', '-Av9a', '-Av9b', '-Av9c', '-Av9d', '-Av9e', '-Av9v' and
'-Av9m' select a 64 bit environment and are not available unless
GAS is explicitly configured with 64 bit environment support.
'-Av8plusa' and '-Av9a' enable the SPARC V9 instruction set with
UltraSPARC VIS 1.0 extensions.
'-Av8plusb' and '-Av9b' enable the UltraSPARC VIS 2.0 instructions,
as well as the instructions enabled by '-Av8plusa' and '-Av9a'.
'-Av8plusc' and '-Av9c' enable the UltraSPARC Niagara instructions,
as well as the instructions enabled by '-Av8plusb' and '-Av9b'.
'-Av8plusd' and '-Av9d' enable the floating point fused
multiply-add, VIS 3.0, and HPC extension instructions, as well as
the instructions enabled by '-Av8plusc' and '-Av9c'.
'-Av8pluse' and '-Av9e' enable the cryptographic instructions, as
well as the instructions enabled by '-Av8plusd' and '-Av9d'.
'-Av8plusv' and '-Av9v' enable floating point unfused multiply-add,
and integer multiply-add, as well as the instructions enabled by
'-Av8pluse' and '-Av9e'.
'-Av8plusm' and '-Av9m' enable the VIS 4.0, subtract extended,
xmpmul, xmontmul and xmontsqr instructions, as well as the
instructions enabled by '-Av8plusv' and '-Av9v'.
'-Asparc' specifies a v9 environment. It is equivalent to '-Av9'
if the word size is 64-bit, and '-Av8plus' otherwise.
'-Asparcvis' specifies a v9a environment. It is equivalent to
'-Av9a' if the word size is 64-bit, and '-Av8plusa' otherwise.
'-Asparcvis2' specifies a v9b environment. It is equivalent to
'-Av9b' if the word size is 64-bit, and '-Av8plusb' otherwise.
'-Asparcfmaf' specifies a v9b environment with the floating point
fused multiply-add instructions enabled.
'-Asparcima' specifies a v9b environment with the integer
multiply-add instructions enabled.
'-Asparcvis3' specifies a v9b environment with the VIS 3.0, HPC ,
and floating point fused multiply-add instructions enabled.
'-Asparcvis3r' specifies a v9b environment with the VIS 3.0, HPC,
and floating point unfused multiply-add instructions enabled.
'-Asparc5' is equivalent to '-Av9m'.
'-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc'
'-xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a'
'-xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m'
'-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2'
'-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3'
'-xarch=sparcvis3r | -xarch=sparc5'
For compatibility with the SunOS v9 assembler. These options are
equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
-Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e, -Av9v, -Av9m,
-Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima,
-Asparcvis3, and -Asparcvis3r, respectively.
'-bump'
Warn whenever it is necessary to switch to another level. If an
architecture level is explicitly requested, GAS will not issue
warnings until that level is reached, and will then bump the level
as required (except between incompatible levels).
'-32 | -64'
Select the word size, either 32 bits or 64 bits. These options are
only available with the ELF object file format, and require that
the necessary BFD support has been included.

File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent
9.42.2 Enforcing aligned data
-----------------------------
SPARC GAS normally permits data to be misaligned. For example, it
permits the '.long' pseudo-op to be used on a byte boundary. However,
the native SunOS assemblers issue an error when they see misaligned
data.
You can use the '--enforce-aligned-data' option to make SPARC GAS
also issue an error about misaligned data, just as the SunOS assemblers
do.
The '--enforce-aligned-data' option is not the default because gcc
issues misaligned data pseudo-ops when it initializes certain packed
data structures (structures defined using the 'packed' attribute). You
may have to assemble with GAS in order to initialize packed data
structures in your own code.

File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent
9.42.3 Sparc Syntax
-------------------
The assembler syntax closely follows The Sparc Architecture Manual,
versions 8 and 9, as well as most extensions defined by Sun for their
UltraSPARC and Niagara line of processors.
* Menu:
* Sparc-Chars:: Special Characters
* Sparc-Regs:: Register Names
* Sparc-Constants:: Constant Names
* Sparc-Relocs:: Relocations
* Sparc-Size-Translations:: Size Translations

File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax
9.42.3.1 Special Characters
...........................
A '!' character appearing anywhere on a line indicates the start of a
comment that extends to the end of that line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line could also be a
logical line number directive (*note Comments::) or a preprocessor
control command (*note Preprocessing::).
';' can be used instead of a newline to separate statements.

File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax
9.42.3.2 Register Names
.......................
The Sparc integer register file is broken down into global, outgoing,
local, and incoming.
* The 8 global registers are referred to as '%gN'.
* The 8 outgoing registers are referred to as '%oN'.
* The 8 local registers are referred to as '%lN'.
* The 8 incoming registers are referred to as '%iN'.
* The frame pointer register '%i6' can be referenced using the alias
'%fp'.
* The stack pointer register '%o6' can be referenced using the alias
'%sp'.
Floating point registers are simply referred to as '%fN'. When
assembling for pre-V9, only 32 floating point registers are available.
For V9 and later there are 64, but there are restrictions when
referencing the upper 32 registers. They can only be accessed as double
or quad, and thus only even or quad numbered accesses are allowed. For
example, '%f34' is a legal floating point register, but '%f35' is not.
Certain V9 instructions allow access to ancillary state registers.
Most simply they can be referred to as '%asrN' where N can be from 16 to
31. However, there are some aliases defined to reference ASR registers
defined for various UltraSPARC processors:
* The tick compare register is referred to as '%tick_cmpr'.
* The system tick register is referred to as '%stick'. An alias,
'%sys_tick', exists but is deprecated and should not be used by new
software.
* The system tick compare register is referred to as '%stick_cmpr'.
An alias, '%sys_tick_cmpr', exists but is deprecated and should not
be used by new software.
* The software interrupt register is referred to as '%softint'.
* The set software interrupt register is referred to as
'%set_softint'. The mnemonic '%softint_set' is provided as an
alias.
* The clear software interrupt register is referred to as
'%clear_softint'. The mnemonic '%softint_clear' is provided as an
alias.
* The performance instrumentation counters register is referred to as
'%pic'.
* The performance control register is referred to as '%pcr'.
* The graphics status register is referred to as '%gsr'.
* The V9 dispatch control register is referred to as '%dcr'.
Various V9 branch and conditional move instructions allow
specification of which set of integer condition codes to test. These
are referred to as '%xcc' and '%icc'.
In V9, there are 4 sets of floating point condition codes which are
referred to as '%fccN'.
Several special privileged and non-privileged registers exist:
* The V9 address space identifier register is referred to as '%asi'.
* The V9 restorable windows register is referred to as '%canrestore'.
* The V9 savable windows register is referred to as '%cansave'.
* The V9 clean windows register is referred to as '%cleanwin'.
* The V9 current window pointer register is referred to as '%cwp'.
* The floating-point queue register is referred to as '%fq'.
* The V8 co-processor queue register is referred to as '%cq'.
* The floating point status register is referred to as '%fsr'.
* The other windows register is referred to as '%otherwin'.
* The V9 program counter register is referred to as '%pc'.
* The V9 next program counter register is referred to as '%npc'.
* The V9 processor interrupt level register is referred to as '%pil'.
* The V9 processor state register is referred to as '%pstate'.
* The trap base address register is referred to as '%tba'.
* The V9 tick register is referred to as '%tick'.
* The V9 trap level is referred to as '%tl'.
* The V9 trap program counter is referred to as '%tpc'.
* The V9 trap next program counter is referred to as '%tnpc'.
* The V9 trap state is referred to as '%tstate'.
* The V9 trap type is referred to as '%tt'.
* The V9 condition codes is referred to as '%ccr'.
* The V9 floating-point registers state is referred to as '%fprs'.
* The V9 version register is referred to as '%ver'.
* The V9 window state register is referred to as '%wstate'.
* The Y register is referred to as '%y'.
* The V8 window invalid mask register is referred to as '%wim'.
* The V8 processor state register is referred to as '%psr'.
* The V9 global register level register is referred to as '%gl'.
Several special register names exist for hypervisor mode code:
* The hyperprivileged processor state register is referred to as
'%hpstate'.
* The hyperprivileged trap state register is referred to as
'%htstate'.
* The hyperprivileged interrupt pending register is referred to as
'%hintp'.
* The hyperprivileged trap base address register is referred to as
'%htba'.
* The hyperprivileged implementation version register is referred to
as '%hver'.
* The hyperprivileged system tick offset register is referred to as
'%hstick_offset'. Note that there is no '%hstick' register, the
normal '%stick' is used.
* The hyperprivileged system tick enable register is referred to as
'%hstick_enable'.
* The hyperprivileged system tick compare register is referred to as
'%hstick_cmpr'.

File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax
9.42.3.3 Constants
..................
Several Sparc instructions take an immediate operand field for which
mnemonic names exist. Two such examples are 'membar' and 'prefetch'.
Another example are the set of V9 memory access instruction that allow
specification of an address space identifier.
The 'membar' instruction specifies a memory barrier that is the
defined by the operand which is a bitmask. The supported mask mnemonics
are:
* '#Sync' requests that all operations (including nonmemory reference
operations) appearing prior to the 'membar' must have been
performed and the effects of any exceptions become visible before
any instructions after the 'membar' may be initiated. This
corresponds to 'membar' cmask field bit 2.
* '#MemIssue' requests that all memory reference operations appearing
prior to the 'membar' must have been performed before any memory
operation after the 'membar' may be initiated. This corresponds to
'membar' cmask field bit 1.
* '#Lookaside' requests that a store appearing prior to the 'membar'
must complete before any load following the 'membar' referencing
the same address can be initiated. This corresponds to 'membar'
cmask field bit 0.
* '#StoreStore' defines that the effects of all stores appearing
prior to the 'membar' instruction must be visible to all processors
before the effect of any stores following the 'membar'. Equivalent
to the deprecated 'stbar' instruction. This corresponds to
'membar' mmask field bit 3.
* '#LoadStore' defines all loads appearing prior to the 'membar'
instruction must have been performed before the effect of any
stores following the 'membar' is visible to any other processor.
This corresponds to 'membar' mmask field bit 2.
* '#StoreLoad' defines that the effects of all stores appearing prior
to the 'membar' instruction must be visible to all processors
before loads following the 'membar' may be performed. This
corresponds to 'membar' mmask field bit 1.
* '#LoadLoad' defines that all loads appearing prior to the 'membar'
instruction must have been performed before any loads following the
'membar' may be performed. This corresponds to 'membar' mmask
field bit 0.
These values can be ored together, for example:
membar #Sync
membar #StoreLoad | #LoadLoad
membar #StoreLoad | #StoreStore
The 'prefetch' and 'prefetcha' instructions take a prefetch function
code. The following prefetch function code constant mnemonics are
available:
* '#n_reads' requests a prefetch for several reads, and corresponds
to a prefetch function code of 0.
'#one_read' requests a prefetch for one read, and corresponds to a
prefetch function code of 1.
'#n_writes' requests a prefetch for several writes (and possibly
reads), and corresponds to a prefetch function code of 2.
'#one_write' requests a prefetch for one write, and corresponds to
a prefetch function code of 3.
'#page' requests a prefetch page, and corresponds to a prefetch
function code of 4.
'#invalidate' requests a prefetch invalidate, and corresponds to a
prefetch function code of 16.
'#unified' requests a prefetch to the nearest unified cache, and
corresponds to a prefetch function code of 17.
'#n_reads_strong' requests a strong prefetch for several reads, and
corresponds to a prefetch function code of 20.
'#one_read_strong' requests a strong prefetch for one read, and
corresponds to a prefetch function code of 21.
'#n_writes_strong' requests a strong prefetch for several writes,
and corresponds to a prefetch function code of 22.
'#one_write_strong' requests a strong prefetch for one write, and
corresponds to a prefetch function code of 23.
Onle one prefetch code may be specified. Here are some examples:
prefetch [%l0 + %l2], #one_read
prefetch [%g2 + 8], #n_writes
prefetcha [%g1] 0x8, #unified
prefetcha [%o0 + 0x10] %asi, #n_reads
The actual behavior of a given prefetch function code is processor
specific. If a processor does not implement a given prefetch
function code, it will treat the prefetch instruction as a nop.
For instructions that accept an immediate address space identifier,
'as' provides many mnemonics corresponding to V9 defined as well as
UltraSPARC and Niagara extended values. For example, '#ASI_P' and
'#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor specific
manuals for details.

File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax
9.42.3.4 Relocations
....................
ELF relocations are available as defined in the 32-bit and 64-bit Sparc
ELF specifications.
'R_SPARC_HI22' is obtained using '%hi' and 'R_SPARC_LO10' is obtained
using '%lo'. Likewise 'R_SPARC_HIX22' is obtained from '%hix' and
'R_SPARC_LOX10' is obtained using '%lox'. For example:
sethi %hi(symbol), %g1
or %g1, %lo(symbol), %g1
sethi %hix(symbol), %g1
xor %g1, %lox(symbol), %g1
These "high" mnemonics extract bits 31:10 of their operand, and the
"low" mnemonics extract bits 9:0 of their operand.
V9 code model relocations can be requested as follows:
* 'R_SPARC_HH22' is requested using '%hh'. It can also be generated
using '%uhi'.
* 'R_SPARC_HM10' is requested using '%hm'. It can also be generated
using '%ulo'.
* 'R_SPARC_LM22' is requested using '%lm'.
* 'R_SPARC_H44' is requested using '%h44'.
* 'R_SPARC_M44' is requested using '%m44'.
* 'R_SPARC_L44' is requested using '%l44' or '%l34'.
* 'R_SPARC_H34' is requested using '%h34'.
The '%l34' generates a 'R_SPARC_L44' relocation because it calculates
the necessary value, and therefore no explicit 'R_SPARC_L34' relocation
needed to be created for this purpose.
The '%h34' and '%l34' relocations are used for the abs34 code model.
Here is an example abs34 address generation sequence:
sethi %h34(symbol), %g1
sllx %g1, 2, %g1
or %g1, %l34(symbol), %g1
The PC relative relocation 'R_SPARC_PC22' can be obtained by
enclosing an operand inside of '%pc22'. Likewise, the 'R_SPARC_PC10'
relocation can be obtained using '%pc10'. These are mostly used when
assembling PIC code. For example, the standard PIC sequence on Sparc to
get the base of the global offset table, PC relative, into a register,
can be performed as:
sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
Several relocations exist to allow the link editor to potentially
optimize GOT data references. The 'R_SPARC_GOTDATA_OP_HIX22' relocation
can obtained by enclosing an operand inside of '%gdop_hix22'. The
'R_SPARC_GOTDATA_OP_LOX10' relocation can obtained by enclosing an
operand inside of '%gdop_lox10'. Likewise, 'R_SPARC_GOTDATA_OP' can be
obtained by enclosing an operand inside of '%gdop'. For example,
assuming the GOT base is in register '%l7':
sethi %gdop_hix22(symbol), %l1
xor %l1, %gdop_lox10(symbol), %l1
ld [%l7 + %l1], %l2, %gdop(symbol)
There are many relocations that can be requested for access to thread
local storage variables. All of the Sparc TLS mnemonics are supported:
* 'R_SPARC_TLS_GD_HI22' is requested using '%tgd_hi22'.
* 'R_SPARC_TLS_GD_LO10' is requested using '%tgd_lo10'.
* 'R_SPARC_TLS_GD_ADD' is requested using '%tgd_add'.
* 'R_SPARC_TLS_GD_CALL' is requested using '%tgd_call'.
* 'R_SPARC_TLS_LDM_HI22' is requested using '%tldm_hi22'.
* 'R_SPARC_TLS_LDM_LO10' is requested using '%tldm_lo10'.
* 'R_SPARC_TLS_LDM_ADD' is requested using '%tldm_add'.
* 'R_SPARC_TLS_LDM_CALL' is requested using '%tldm_call'.
* 'R_SPARC_TLS_LDO_HIX22' is requested using '%tldo_hix22'.
* 'R_SPARC_TLS_LDO_LOX10' is requested using '%tldo_lox10'.
* 'R_SPARC_TLS_LDO_ADD' is requested using '%tldo_add'.
* 'R_SPARC_TLS_IE_HI22' is requested using '%tie_hi22'.
* 'R_SPARC_TLS_IE_LO10' is requested using '%tie_lo10'.
* 'R_SPARC_TLS_IE_LD' is requested using '%tie_ld'.
* 'R_SPARC_TLS_IE_LDX' is requested using '%tie_ldx'.
* 'R_SPARC_TLS_IE_ADD' is requested using '%tie_add'.
* 'R_SPARC_TLS_LE_HIX22' is requested using '%tle_hix22'.
* 'R_SPARC_TLS_LE_LOX10' is requested using '%tle_lox10'.
Here are some example TLS model sequences.
First, General Dynamic:
sethi %tgd_hi22(symbol), %l1
add %l1, %tgd_lo10(symbol), %l1
add %l7, %l1, %o0, %tgd_add(symbol)
call __tls_get_addr, %tgd_call(symbol)
nop
Local Dynamic:
sethi %tldm_hi22(symbol), %l1
add %l1, %tldm_lo10(symbol), %l1
add %l7, %l1, %o0, %tldm_add(symbol)
call __tls_get_addr, %tldm_call(symbol)
nop
sethi %tldo_hix22(symbol), %l1
xor %l1, %tldo_lox10(symbol), %l1
add %o0, %l1, %l1, %tldo_add(symbol)
Initial Exec:
sethi %tie_hi22(symbol), %l1
add %l1, %tie_lo10(symbol), %l1
ld [%l7 + %l1], %o0, %tie_ld(symbol)
add %g7, %o0, %o0, %tie_add(symbol)
sethi %tie_hi22(symbol), %l1
add %l1, %tie_lo10(symbol), %l1
ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
add %g7, %o0, %o0, %tie_add(symbol)
And finally, Local Exec:
sethi %tle_hix22(symbol), %l1
add %l1, %tle_lox10(symbol), %l1
add %g7, %l1, %l1
When assembling for 64-bit, and a secondary constant addend is
specified in an address expression that would normally generate an
'R_SPARC_LO10' relocation, the assembler will emit an 'R_SPARC_OLO10'
instead.

File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax
9.42.3.5 Size Translations
..........................
Often it is desirable to write code in an operand size agnostic manner.
'as' provides support for this via operand size opcode translations.
Translations are supported for loads, stores, shifts, compare-and-swap
atomics, and the 'clr' synthetic instruction.
If generating 32-bit code, 'as' will generate the 32-bit opcode.
Whereas if 64-bit code is being generated, the 64-bit opcode will be
emitted. For example 'ldn' will be transformed into 'ld' for 32-bit
code and 'ldx' for 64-bit code.
Here is an example meant to demonstrate all the supported opcode
translations:
ldn [%o0], %o1
ldna [%o0] %asi, %o2
stn %o1, [%o0]
stna %o2, [%o0] %asi
slln %o3, 3, %o3
srln %o4, 8, %o4
sran %o5, 12, %o5
casn [%o0], %o1, %o2
casna [%o0] %asi, %o1, %o2
clrn %g1
In 32-bit mode 'as' will emit:
ld [%o0], %o1
lda [%o0] %asi, %o2
st %o1, [%o0]
sta %o2, [%o0] %asi
sll %o3, 3, %o3
srl %o4, 8, %o4
sra %o5, 12, %o5
cas [%o0], %o1, %o2
casa [%o0] %asi, %o1, %o2
clr %g1
And in 64-bit mode 'as' will emit:
ldx [%o0], %o1
ldxa [%o0] %asi, %o2
stx %o1, [%o0]
stxa %o2, [%o0] %asi
sllx %o3, 3, %o3
srlx %o4, 8, %o4
srax %o5, 12, %o5
casx [%o0], %o1, %o2
casxa [%o0] %asi, %o1, %o2
clrx %g1
Finally, the '.nword' translating directive is supported as well. It
is documented in the section on Sparc machine directives.

File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent
9.42.4 Floating Point
---------------------
The Sparc uses IEEE floating-point numbers.

File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent
9.42.5 Sparc Machine Directives
-------------------------------
The Sparc version of 'as' supports the following additional machine
directives:
'.align'
This must be followed by the desired alignment in bytes.
'.common'
This must be followed by a symbol name, a positive number, and
'"bss"'. This behaves somewhat like '.comm', but the syntax is
different.
'.half'
This is functionally identical to '.short'.
'.nword'
On the Sparc, the '.nword' directive produces native word sized
value, ie. if assembling with -32 it is equivalent to '.word', if
assembling with -64 it is equivalent to '.xword'.
'.proc'
This directive is ignored. Any text following it on the same line
is also ignored.
'.register'
This directive declares use of a global application or system
register. It must be followed by a register name %g2, %g3, %g6 or
%g7, comma and the symbol name for that register. If symbol name
is '#scratch', it is a scratch register, if it is '#ignore', it
just suppresses any errors about using undeclared global register,
but does not emit any information about it into the object file.
This can be useful e.g. if you save the register before use and
restore it after.
'.reserve'
This must be followed by a symbol name, a positive number, and
'"bss"'. This behaves somewhat like '.lcomm', but the syntax is
different.
'.seg'
This must be followed by '"text"', '"data"', or '"data1"'. It
behaves like '.text', '.data', or '.data 1'.
'.skip'
This is functionally identical to the '.space' directive.
'.word'
On the Sparc, the '.word' directive produces 32 bit values, instead
of the 16 bit values it produces on many other machines.
'.xword'
On the Sparc V9 processor, the '.xword' directive produces 64 bit
values.

File: as.info, Node: TIC54X-Dependent, Next: TIC6X-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies
9.43 TIC54X Dependent Features
==============================
* Menu:
* TIC54X-Opts:: Command-line Options
* TIC54X-Block:: Blocking
* TIC54X-Env:: Environment Settings
* TIC54X-Constants:: Constants Syntax
* TIC54X-Subsyms:: String Substitution
* TIC54X-Locals:: Local Label Syntax
* TIC54X-Builtins:: Builtin Assembler Math Functions
* TIC54X-Ext:: Extended Addressing Support
* TIC54X-Directives:: Directives
* TIC54X-Macros:: Macro Features
* TIC54X-MMRegs:: Memory-mapped Registers
* TIC54X-Syntax:: Syntax

File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent
9.43.1 Options
--------------
The TMS320C54X version of 'as' has a few machine-dependent options.
You can use the '-mfar-mode' option to enable extended addressing
mode. All addresses will be assumed to be > 16 bits, and the
appropriate relocation types will be used. This option is equivalent to
using the '.far_mode' directive in the assembly code. If you do not use
the '-mfar-mode' option, all references will be assumed to be 16 bits.
This option may be abbreviated to '-mf'.
You can use the '-mcpu' option to specify a particular CPU. This
option is equivalent to using the '.version' directive in the assembly
code. For recognized CPU codes, see *Note '.version':
TIC54X-Directives. The default CPU version is '542'.
You can use the '-merrors-to-file' option to redirect error output to
a file (this provided for those deficient environments which don't
provide adequate output redirection). This option may be abbreviated to
'-me'.

File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent
9.43.2 Blocking
---------------
A blocked section or memory block is guaranteed not to cross the
blocking boundary (usually a page, or 128 words) if it is smaller than
the blocking size, or to start on a page boundary if it is larger than
the blocking size.

File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent
9.43.3 Environment Settings
---------------------------
'C54XDSP_DIR' and 'A_DIR' are semicolon-separated paths which are added
to the list of directories normally searched for source and include
files. 'C54XDSP_DIR' will override 'A_DIR'.

File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent
9.43.4 Constants Syntax
-----------------------
The TIC54X version of 'as' allows the following additional constant
formats, using a suffix to indicate the radix:
Binary 000000B, 011000b
Octal 10Q, 224q
Hexadecimal 45h, 0FH

File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent
9.43.5 String Substitution
--------------------------
A subset of allowable symbols (which we'll call subsyms) may be assigned
arbitrary string values. This is roughly equivalent to C preprocessor
#define macros. When 'as' encounters one of these symbols, the symbol
is replaced in the input stream by its string value. Subsym names
*must* begin with a letter.
Subsyms may be defined using the '.asg' and '.eval' directives (*Note
'.asg': TIC54X-Directives, *Note '.eval': TIC54X-Directives.
Expansion is recursive until a previously encountered symbol is seen,
at which point substitution stops.
In this example, x is replaced with SYM2; SYM2 is replaced with SYM1,
and SYM1 is replaced with x. At this point, x has already been
encountered and the substitution stops.
.asg "x",SYM1
.asg "SYM1",SYM2
.asg "SYM2",x
add x,a ; final code assembled is "add x, a"
Macro parameters are converted to subsyms; a side effect of this is
the normal 'as' '\ARG' dereferencing syntax is unnecessary. Subsyms
defined within a macro will have global scope, unless the '.var'
directive is used to identify the subsym as a local macro variable *note
'.var': TIC54X-Directives.
Substitution may be forced in situations where replacement might be
ambiguous by placing colons on either side of the subsym. The following
code:
.eval "10",x
LAB:X: add #x, a
When assembled becomes:
LAB10 add #10, a
Smaller parts of the string assigned to a subsym may be accessed with
the following syntax:
':SYMBOL(CHAR_INDEX):'
Evaluates to a single-character string, the character at
CHAR_INDEX.
':SYMBOL(START,LENGTH):'
Evaluates to a substring of SYMBOL beginning at START with length
LENGTH.

File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent
9.43.6 Local Labels
-------------------
Local labels may be defined in two ways:
* $N, where N is a decimal number between 0 and 9
* LABEL?, where LABEL is any legal symbol name.
Local labels thus defined may be redefined or automatically
generated. The scope of a local label is based on when it may be
undefined or reset. This happens when one of the following situations
is encountered:
* .newblock directive *note '.newblock': TIC54X-Directives.
* The current section is changed (.sect, .text, or .data)
* Entering or leaving an included file
* The macro scope where the label was defined is exited

File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent
9.43.7 Math Builtins
--------------------
The following built-in functions may be used to generate a
floating-point value. All return a floating-point value except '$cvi',
'$int', and '$sgn', which return an integer value.
'$acos(EXPR)'
Returns the floating point arccosine of EXPR.
'$asin(EXPR)'
Returns the floating point arcsine of EXPR.
'$atan(EXPR)'
Returns the floating point arctangent of EXPR.
'$atan2(EXPR1,EXPR2)'
Returns the floating point arctangent of EXPR1 / EXPR2.
'$ceil(EXPR)'
Returns the smallest integer not less than EXPR as floating point.
'$cosh(EXPR)'
Returns the floating point hyperbolic cosine of EXPR.
'$cos(EXPR)'
Returns the floating point cosine of EXPR.
'$cvf(EXPR)'
Returns the integer value EXPR converted to floating-point.
'$cvi(EXPR)'
Returns the floating point value EXPR converted to integer.
'$exp(EXPR)'
Returns the floating point value e ^ EXPR.
'$fabs(EXPR)'
Returns the floating point absolute value of EXPR.
'$floor(EXPR)'
Returns the largest integer that is not greater than EXPR as
floating point.
'$fmod(EXPR1,EXPR2)'
Returns the floating point remainder of EXPR1 / EXPR2.
'$int(EXPR)'
Returns 1 if EXPR evaluates to an integer, zero otherwise.
'$ldexp(EXPR1,EXPR2)'
Returns the floating point value EXPR1 * 2 ^ EXPR2.
'$log10(EXPR)'
Returns the base 10 logarithm of EXPR.
'$log(EXPR)'
Returns the natural logarithm of EXPR.
'$max(EXPR1,EXPR2)'
Returns the floating point maximum of EXPR1 and EXPR2.
'$min(EXPR1,EXPR2)'
Returns the floating point minimum of EXPR1 and EXPR2.
'$pow(EXPR1,EXPR2)'
Returns the floating point value EXPR1 ^ EXPR2.
'$round(EXPR)'
Returns the nearest integer to EXPR as a floating point number.
'$sgn(EXPR)'
Returns -1, 0, or 1 based on the sign of EXPR.
'$sin(EXPR)'
Returns the floating point sine of EXPR.
'$sinh(EXPR)'
Returns the floating point hyperbolic sine of EXPR.
'$sqrt(EXPR)'
Returns the floating point square root of EXPR.
'$tan(EXPR)'
Returns the floating point tangent of EXPR.
'$tanh(EXPR)'
Returns the floating point hyperbolic tangent of EXPR.
'$trunc(EXPR)'
Returns the integer value of EXPR truncated towards zero as
floating point.

File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent
9.43.8 Extended Addressing
--------------------------
The 'LDX' pseudo-op is provided for loading the extended addressing bits
of a label or address. For example, if an address '_label' resides in
extended program memory, the value of '_label' may be loaded as follows:
ldx #_label,16,a ; loads extended bits of _label
or #_label,a ; loads lower 16 bits of _label
bacc a ; full address is in accumulator A

File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent
9.43.9 Directives
-----------------
'.align [SIZE]'
'.even'
Align the section program counter on the next boundary, based on
SIZE. SIZE may be any power of 2. '.even' is equivalent to
'.align' with a SIZE of 2.
'1'
Align SPC to word boundary
'2'
Align SPC to longword boundary (same as .even)
'128'
Align SPC to page boundary
'.asg STRING, NAME'
Assign NAME the string STRING. String replacement is performed on
STRING before assignment.
'.eval STRING, NAME'
Evaluate the contents of string STRING and assign the result as a
string to the subsym NAME. String replacement is performed on
STRING before assignment.
'.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
Reserve space for SYMBOL in the .bss section. SIZE is in words.
If present, BLOCKING_FLAG indicates the allocated space should be
aligned on a page boundary if it would otherwise cross a page
boundary. If present, ALIGNMENT_FLAG causes the assembler to
allocate SIZE on a long word boundary.
'.byte VALUE [,...,VALUE_N]'
'.ubyte VALUE [,...,VALUE_N]'
'.char VALUE [,...,VALUE_N]'
'.uchar VALUE [,...,VALUE_N]'
Place one or more bytes into consecutive words of the current
section. The upper 8 bits of each word is zero-filled. If a label
is used, it points to the word allocated for the first byte
encountered.
'.clink ["SECTION_NAME"]'
Set STYP_CLINK flag for this section, which indicates to the linker
that if no symbols from this section are referenced, the section
should not be included in the link. If SECTION_NAME is omitted,
the current section is used.
'.c_mode'
TBD.
'.copy "FILENAME" | FILENAME'
'.include "FILENAME" | FILENAME'
Read source statements from FILENAME. The normal include search
path is used. Normally .copy will cause statements from the
included file to be printed in the assembly listing and .include
will not, but this distinction is not currently implemented.
'.data'
Begin assembling code into the .data section.
'.double VALUE [,...,VALUE_N]'
'.ldouble VALUE [,...,VALUE_N]'
'.float VALUE [,...,VALUE_N]'
'.xfloat VALUE [,...,VALUE_N]'
Place an IEEE single-precision floating-point representation of one
or more floating-point values into the current section. All but
'.xfloat' align the result on a longword boundary. Values are
stored most-significant word first.
'.drlist'
'.drnolist'
Control printing of directives to the listing file. Ignored.
'.emsg STRING'
'.mmsg STRING'
'.wmsg STRING'
Emit a user-defined error, message, or warning, respectively.
'.far_mode'
Use extended addressing when assembling statements. This should
appear only once per file, and is equivalent to the -mfar-mode
option *note '-mfar-mode': TIC54X-Opts.
'.fclist'
'.fcnolist'
Control printing of false conditional blocks to the listing file.
'.field VALUE [,SIZE]'
Initialize a bitfield of SIZE bits in the current section. If
VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16
bits. If VALUE does not fit into SIZE bits, the value will be
truncated. Successive '.field' directives will pack starting at
the current word, filling the most significant bits first, and
aligning to the start of the next word if the field size does not
fit into the space remaining in the current word. A '.align'
directive with an operand of 1 will force the next '.field'
directive to begin packing into a new word. If a label is used, it
points to the word that contains the specified field.
'.global SYMBOL [,...,SYMBOL_N]'
'.def SYMBOL [,...,SYMBOL_N]'
'.ref SYMBOL [,...,SYMBOL_N]'
'.def' nominally identifies a symbol defined in the current file
and available to other files. '.ref' identifies a symbol used in
the current file but defined elsewhere. Both map to the standard
'.global' directive.
'.half VALUE [,...,VALUE_N]'
'.uhalf VALUE [,...,VALUE_N]'
'.short VALUE [,...,VALUE_N]'
'.ushort VALUE [,...,VALUE_N]'
'.int VALUE [,...,VALUE_N]'
'.uint VALUE [,...,VALUE_N]'
'.word VALUE [,...,VALUE_N]'
'.uword VALUE [,...,VALUE_N]'
Place one or more values into consecutive words of the current
section. If a label is used, it points to the word allocated for
the first value encountered.
'.label SYMBOL'
Define a special SYMBOL to refer to the load time address of the
current section program counter.
'.length'
'.width'
Set the page length and width of the output listing file. Ignored.
'.list'
'.nolist'
Control whether the source listing is printed. Ignored.
'.long VALUE [,...,VALUE_N]'
'.ulong VALUE [,...,VALUE_N]'
'.xlong VALUE [,...,VALUE_N]'
Place one or more 32-bit values into consecutive words in the
current section. The most significant word is stored first.
'.long' and '.ulong' align the result on a longword boundary;
'xlong' does not.
'.loop [COUNT]'
'.break [CONDITION]'
'.endloop'
Repeatedly assemble a block of code. '.loop' begins the block, and
'.endloop' marks its termination. COUNT defaults to 1024, and
indicates the number of times the block should be repeated.
'.break' terminates the loop so that assembly begins after the
'.endloop' directive. The optional CONDITION will cause the loop
to terminate only if it evaluates to zero.
'MACRO_NAME .macro [PARAM1][,...PARAM_N]'
'[.mexit]'
'.endm'
See the section on macros for more explanation (*Note
TIC54X-Macros::.
'.mlib "FILENAME" | FILENAME'
Load the macro library FILENAME. FILENAME must be an archived
library (BFD ar-compatible) of text files, expected to contain only
macro definitions. The standard include search path is used.
'.mlist'
'.mnolist'
Control whether to include macro and loop block expansions in the
listing output. Ignored.
'.mmregs'
Define global symbolic names for the 'c54x registers. Supposedly
equivalent to executing '.set' directives for each register with
its memory-mapped value, but in reality is provided only for
compatibility and does nothing.
'.newblock'
This directive resets any TIC54X local labels currently defined.
Normal 'as' local labels are unaffected.
'.option OPTION_LIST'
Set listing options. Ignored.
'.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]'
Designate SECTION_NAME for blocking. Blocking guarantees that a
section will start on a page boundary (128 words) if it would
otherwise cross a page boundary. Only initialized sections may be
designated with this directive. See also *Note TIC54X-Block::.
'.sect "SECTION_NAME"'
Define a named initialized section and make it the current section.
'SYMBOL .set "VALUE"'
'SYMBOL .equ "VALUE"'
Equate a constant VALUE to a SYMBOL, which is placed in the symbol
table. SYMBOL may not be previously defined.
'.space SIZE_IN_BITS'
'.bes SIZE_IN_BITS'
Reserve the given number of bits in the current section and
zero-fill them. If a label is used with '.space', it points to the
*first* word reserved. With '.bes', the label points to the *last*
word reserved.
'.sslist'
'.ssnolist'
Controls the inclusion of subsym replacement in the listing output.
Ignored.
'.string "STRING" [,...,"STRING_N"]'
'.pstring "STRING" [,...,"STRING_N"]'
Place 8-bit characters from STRING into the current section.
'.string' zero-fills the upper 8 bits of each word, while
'.pstring' puts two characters into each word, filling the
most-significant bits first. Unused space is zero-filled. If a
label is used, it points to the first word initialized.
'[STAG] .struct [OFFSET]'
'[NAME_1] element [COUNT_1]'
'[NAME_2] element [COUNT_2]'
'[TNAME] .tag STAGX [TCOUNT]'
'...'
'[NAME_N] element [COUNT_N]'
'[SSIZE] .endstruct'
'LABEL .tag [STAG]'
Assign symbolic offsets to the elements of a structure. STAG
defines a symbol to use to reference the structure. OFFSET
indicates a starting value to use for the first element
encountered; otherwise it defaults to zero. Each element can have
a named offset, NAME, which is a symbol assigned the value of the
element's offset into the structure. If STAG is missing, these
become global symbols. COUNT adjusts the offset that many times,
as if 'element' were an array. 'element' may be one of '.byte',
'.word', '.long', '.float', or any equivalent of those, and the
structure offset is adjusted accordingly. '.field' and '.string'
are also allowed; the size of '.field' is one bit, and '.string' is
considered to be one word in size. Only element descriptors,
structure/union tags, '.align' and conditional assembly directives
are allowed within '.struct'/'.endstruct'. '.align' aligns member
offsets to word boundaries only. SSIZE, if provided, will always
be assigned the size of the structure.
The '.tag' directive, in addition to being used to define a
structure/union element within a structure, may be used to apply a
structure to a symbol. Once applied to LABEL, the individual
structure elements may be applied to LABEL to produce the desired
offsets using LABEL as the structure base.
'.tab'
Set the tab size in the output listing. Ignored.
'[UTAG] .union'
'[NAME_1] element [COUNT_1]'
'[NAME_2] element [COUNT_2]'
'[TNAME] .tag UTAGX[,TCOUNT]'
'...'
'[NAME_N] element [COUNT_N]'
'[USIZE] .endstruct'
'LABEL .tag [UTAG]'
Similar to '.struct', but the offset after each element is reset to
zero, and the USIZE is set to the maximum of all defined elements.
Starting offset for the union is always zero.
'[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
Reserve space for variables in a named, uninitialized section
(similar to .bss). '.usect' allows definitions sections
independent of .bss. SYMBOL points to the first location reserved
by this allocation. The symbol may be used as a variable name.
SIZE is the allocated size in words. BLOCKING_FLAG indicates
whether to block this section on a page boundary (128 words) (*note
TIC54X-Block::). ALIGNMENT FLAG indicates whether the section
should be longword-aligned.
'.var SYM[,..., SYM_N]'
Define a subsym to be a local variable within a macro. See *Note
TIC54X-Macros::.
'.version VERSION'
Set which processor to build instructions for. Though the
following values are accepted, the op is ignored.
'541'
'542'
'543'
'545'
'545LP'
'546LP'
'548'
'549'

File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent
9.43.10 Macros
--------------
Macros do not require explicit dereferencing of arguments (i.e., \ARG).
During macro expansion, the macro parameters are converted to
subsyms. If the number of arguments passed the macro invocation exceeds
the number of parameters defined, the last parameter is assigned the
string equivalent of all remaining arguments. If fewer arguments are
given than parameters, the missing parameters are assigned empty
strings. To include a comma in an argument, you must enclose the
argument in quotes.
The following built-in subsym functions allow examination of the
string value of subsyms (or ordinary strings). The arguments are
strings unless otherwise indicated (subsyms passed as args will be
replaced by the strings they represent).
'$symlen(STR)'
Returns the length of STR.
'$symcmp(STR1,STR2)'
Returns 0 if STR1 == STR2, non-zero otherwise.
'$firstch(STR,CH)'
Returns index of the first occurrence of character constant CH in
STR.
'$lastch(STR,CH)'
Returns index of the last occurrence of character constant CH in
STR.
'$isdefed(SYMBOL)'
Returns zero if the symbol SYMBOL is not in the symbol table,
non-zero otherwise.
'$ismember(SYMBOL,LIST)'
Assign the first member of comma-separated string LIST to SYMBOL;
LIST is reassigned the remainder of the list. Returns zero if LIST
is a null string. Both arguments must be subsyms.
'$iscons(EXPR)'
Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, 4
if a character, 5 if decimal, and zero if not an integer.
'$isname(NAME)'
Returns 1 if NAME is a valid symbol name, zero otherwise.
'$isreg(REG)'
Returns 1 if REG is a valid predefined register name (AR0-AR7
only).
'$structsz(STAG)'
Returns the size of the structure or union represented by STAG.
'$structacc(STAG)'
Returns the reference point of the structure or union represented
by STAG. Always returns zero.

File: as.info, Node: TIC54X-MMRegs, Next: TIC54X-Syntax, Prev: TIC54X-Macros, Up: TIC54X-Dependent
9.43.11 Memory-mapped Registers
-------------------------------
The following symbols are recognized as memory-mapped registers:

File: as.info, Node: TIC54X-Syntax, Prev: TIC54X-MMRegs, Up: TIC54X-Dependent
9.43.12 TIC54X Syntax
---------------------
* Menu:
* TIC54X-Chars:: Special Characters

File: as.info, Node: TIC54X-Chars, Up: TIC54X-Syntax
9.43.12.1 Special Characters
............................
The presence of a ';' appearing anywhere on a line indicates the start
of a comment that extends to the end of that line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
The presence of an asterisk ('*') at the start of a line also
indicates a comment that extends to the end of that line.
The TIC54X assembler does not currently support a line separator
character.

File: as.info, Node: TIC6X-Dependent, Next: TILE-Gx-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies
9.44 TIC6X Dependent Features
=============================
* Menu:
* TIC6X Options:: Options
* TIC6X Syntax:: Syntax
* TIC6X Directives:: Directives

File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent
9.44.1 TIC6X Options
--------------------
'-march=ARCH'
Enable (only) instructions from architecture ARCH. By default, all
instructions are permitted.
The following values of ARCH are accepted: 'c62x', 'c64x', 'c64x+',
'c67x', 'c67x+', 'c674x'.
'-mdsbt'
'-mno-dsbt'
The '-mdsbt' option causes the assembler to generate the
'Tag_ABI_DSBT' attribute with a value of 1, indicating that the
code is using DSBT addressing. The '-mno-dsbt' option, the
default, causes the tag to have a value of 0, indicating that the
code does not use DSBT addressing. The linker will emit a warning
if objects of different type (DSBT and non-DSBT) are linked
together.
'-mpid=no'
'-mpid=near'
'-mpid=far'
The '-mpid=' option causes the assembler to generate the
'Tag_ABI_PID' attribute with a value indicating the form of data
addressing used by the code. '-mpid=no', the default, indicates
position-dependent data addressing, '-mpid=near' indicates
position-independent addressing with GOT accesses using near DP
addressing, and '-mpid=far' indicates position-independent
addressing with GOT accesses using far DP addressing. The linker
will emit a warning if objects built with different settings of
this option are linked together.
'-mpic'
'-mno-pic'
The '-mpic' option causes the assembler to generate the
'Tag_ABI_PIC' attribute with a value of 1, indicating that the code
is using position-independent code addressing, The '-mno-pic'
option, the default, causes the tag to have a value of 0,
indicating position-dependent code addressing. The linker will
emit a warning if objects of different type (position-dependent and
position-independent) are linked together.
'-mbig-endian'
'-mlittle-endian'
Generate code for the specified endianness. The default is
little-endian.

File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent
9.44.2 TIC6X Syntax
-------------------
The presence of a ';' on a line indicates the start of a comment that
extends to the end of the current line. If a '#' or '*' appears as the
first character of a line, the whole line is treated as a comment. Note
that if a line starts with a '#' character then it can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
The '@' character can be used instead of a newline to separate
statements.
Instruction, register and functional unit names are case-insensitive.
'as' requires fully-specified functional unit names, such as '.S1',
'.L1X' or '.D1T2', on all instructions using a functional unit.
For some instructions, there may be syntactic ambiguity between
register or functional unit names and the names of labels or other
symbols. To avoid this, enclose the ambiguous symbol name in
parentheses; register and functional unit names may not be enclosed in
parentheses.

File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependent
9.44.3 TIC6X Directives
-----------------------
Directives controlling the set of instructions accepted by the assembler
have effect for instructions between the directive and any subsequent
directive overriding it.
'.arch ARCH'
This has the same effect as '-march=ARCH'.
'.cantunwind'
Prevents unwinding through the current function. No personality
routine or exception table data is required or permitted.
If this is not specified then frame unwinding information will be
constructed from CFI directives. *note CFI directives::.
'.c6xabi_attribute TAG, VALUE'
Set the C6000 EABI build attribute TAG to VALUE.
The TAG is either an attribute number or one of 'Tag_ISA',
'Tag_ABI_wchar_t', 'Tag_ABI_stack_align_needed',
'Tag_ABI_stack_align_preserved', 'Tag_ABI_DSBT', 'Tag_ABI_PID',
'Tag_ABI_PIC', 'TAG_ABI_array_object_alignment',
'TAG_ABI_array_object_align_expected', 'Tag_ABI_compatibility' and
'Tag_ABI_conformance'. The VALUE is either a 'number', '"string"',
or 'number, "string"' depending on the tag.
'.ehtype SYMBOL'
Output an exception type table reference to SYMBOL.
'.endp'
Marks the end of and exception table or function. If preceeded by
a '.handlerdata' directive then this also switched back to the
previous text section.
'.handlerdata'
Marks the end of the current function, and the start of the
exception table entry for that function. Anything between this
directive and the '.endp' directive will be added to the exception
table entry.
Must be preceded by a CFI block containing a '.cfi_lsda' directive.
'.nocmp'
Disallow use of C64x+ compact instructions in the current text
section.
'.personalityindex INDEX'
Sets the personality routine for the current function to the ABI
specified compact routine number INDEX
'.personality NAME'
Sets the personality routine for the current function to NAME.
'.scomm SYMBOL, SIZE, ALIGN'
Like '.comm', creating a common symbol SYMBOL with size SIZE and
alignment ALIGN, but unlike when using '.comm', this symbol will be
placed into the small BSS section by the linker.

File: as.info, Node: TILE-Gx-Dependent, Next: TILEPro-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies
9.45 TILE-Gx Dependent Features
===============================
* Menu:
* TILE-Gx Options:: TILE-Gx Options
* TILE-Gx Syntax:: TILE-Gx Syntax
* TILE-Gx Directives:: TILE-Gx Directives

File: as.info, Node: TILE-Gx Options, Next: TILE-Gx Syntax, Up: TILE-Gx-Dependent
9.45.1 Options
--------------
The following table lists all available TILE-Gx specific options:
'-m32 | -m64'
Select the word size, either 32 bits or 64 bits.
'-EB | -EL'
Select the endianness, either big-endian (-EB) or little-endian
(-EL).

File: as.info, Node: TILE-Gx Syntax, Next: TILE-Gx Directives, Prev: TILE-Gx Options, Up: TILE-Gx-Dependent
9.45.2 Syntax
-------------
Block comments are delimited by '/*' and '*/'. End of line comments may
be introduced by '#'.
Instructions consist of a leading opcode or macro name followed by
whitespace and an optional comma-separated list of operands:
OPCODE [OPERAND, ...]
Instructions must be separated by a newline or semicolon.
There are two ways to write code: either write naked instructions,
which the assembler is free to combine into VLIW bundles, or specify the
VLIW bundles explicitly.
Bundles are specified using curly braces:
{ ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 }
A bundle can span multiple lines. If you want to put multiple
instructions on a line, whether in a bundle or not, you need to separate
them with semicolons as in this example.
A bundle may contain one or more instructions, up to the limit
specified by the ISA (currently three). If fewer instructions are
specified than the hardware supports in a bundle, the assembler inserts
'fnop' instructions automatically.
The assembler will prefer to preserve the ordering of instructions
within the bundle, putting the first instruction in a lower-numbered
pipeline than the next one, etc. This fact, combined with the optional
use of explicit 'fnop' or 'nop' instructions, allows precise control
over which pipeline executes each instruction.
If the instructions cannot be bundled in the listed order, the
assembler will automatically try to find a valid pipeline assignment.
If there is no way to bundle the instructions together, the assembler
reports an error.
The assembler does not yet auto-bundle (automatically combine
multiple instructions into one bundle), but it reserves the right to do
so in the future. If you want to force an instruction to run by itself,
put it in a bundle explicitly with curly braces and use 'nop'
instructions (not 'fnop') to fill the remaining pipeline slots in that
bundle.
* Menu:
* TILE-Gx Opcodes:: Opcode Naming Conventions.
* TILE-Gx Registers:: Register Naming.
* TILE-Gx Modifiers:: Symbolic Operand Modifiers.

File: as.info, Node: TILE-Gx Opcodes, Next: TILE-Gx Registers, Up: TILE-Gx Syntax
9.45.2.1 Opcode Names
.....................
For a complete list of opcodes and descriptions of their semantics, see
'TILE-Gx Instruction Set Architecture', available upon request at
www.tilera.com.

File: as.info, Node: TILE-Gx Registers, Next: TILE-Gx Modifiers, Prev: TILE-Gx Opcodes, Up: TILE-Gx Syntax
9.45.2.2 Register Names
.......................
General-purpose registers are represented by predefined symbols of the
form 'rN', where N represents a number between '0' and '63'. However,
the following registers have canonical names that must be used instead:
'r54'
sp
'r55'
lr
'r56'
sn
'r57'
idn0
'r58'
idn1
'r59'
udn0
'r60'
udn1
'r61'
udn2
'r62'
udn3
'r63'
zero
The assembler will emit a warning if a numeric name is used instead
of the non-numeric name. The '.no_require_canonical_reg_names'
assembler pseudo-op turns off this warning.
'.require_canonical_reg_names' turns it back on.

File: as.info, Node: TILE-Gx Modifiers, Prev: TILE-Gx Registers, Up: TILE-Gx Syntax
9.45.2.3 Symbolic Operand Modifiers
...................................
The assembler supports several modifiers when using symbol addresses in
TILE-Gx instruction operands. The general syntax is the following:
modifier(symbol)
The following modifiers are supported:
'hw0'
This modifier is used to load bits 0-15 of the symbol's address.
'hw1'
This modifier is used to load bits 16-31 of the symbol's address.
'hw2'
This modifier is used to load bits 32-47 of the symbol's address.
'hw3'
This modifier is used to load bits 48-63 of the symbol's address.
'hw0_last'
This modifier yields the same value as 'hw0', but it also checks
that the value does not overflow.
'hw1_last'
This modifier yields the same value as 'hw1', but it also checks
that the value does not overflow.
'hw2_last'
This modifier yields the same value as 'hw2', but it also checks
that the value does not overflow.
A 48-bit symbolic value is constructed by using the following
idiom:
moveli r0, hw2_last(sym)
shl16insli r0, r0, hw1(sym)
shl16insli r0, r0, hw0(sym)
'hw0_got'
This modifier is used to load bits 0-15 of the symbol's offset in
the GOT entry corresponding to the symbol.
'hw0_last_got'
This modifier yields the same value as 'hw0_got', but it also
checks that the value does not overflow.
'hw1_last_got'
This modifier is used to load bits 16-31 of the symbol's offset in
the GOT entry corresponding to the symbol, and it also checks that
the value does not overflow.
'plt'
This modifier is used for function symbols. It causes a _procedure
linkage table_, an array of code stubs, to be created at the time
the shared object is created or linked against, together with a
global offset table entry. The value is a pc-relative offset to
the corresponding stub code in the procedure linkage table. This
arrangement causes the run-time symbol resolver to be called to
look up and set the value of the symbol the first time the function
is called (at latest; depending environment variables). It is only
safe to leave the symbol unresolved this way if all references are
function calls.
'hw0_plt'
This modifier is used to load bits 0-15 of the pc-relative address
of a plt entry.
'hw1_plt'
This modifier is used to load bits 16-31 of the pc-relative address
of a plt entry.
'hw1_last_plt'
This modifier yields the same value as 'hw1_plt', but it also
checks that the value does not overflow.
'hw2_last_plt'
This modifier is used to load bits 32-47 of the pc-relative address
of a plt entry, and it also checks that the value does not
overflow.
'hw0_tls_gd'
This modifier is used to load bits 0-15 of the offset of the GOT
entry of the symbol's TLS descriptor, to be used for
general-dynamic TLS accesses.
'hw0_last_tls_gd'
This modifier yields the same value as 'hw0_tls_gd', but it also
checks that the value does not overflow.
'hw1_last_tls_gd'
This modifier is used to load bits 16-31 of the offset of the GOT
entry of the symbol's TLS descriptor, to be used for
general-dynamic TLS accesses. It also checks that the value does
not overflow.
'hw0_tls_ie'
This modifier is used to load bits 0-15 of the offset of the GOT
entry containing the offset of the symbol's address from the TCB,
to be used for initial-exec TLS accesses.
'hw0_last_tls_ie'
This modifier yields the same value as 'hw0_tls_ie', but it also
checks that the value does not overflow.
'hw1_last_tls_ie'
This modifier is used to load bits 16-31 of the offset of the GOT
entry containing the offset of the symbol's address from the TCB,
to be used for initial-exec TLS accesses. It also checks that the
value does not overflow.
'hw0_tls_le'
This modifier is used to load bits 0-15 of the offset of the
symbol's address from the TCB, to be used for local-exec TLS
accesses.
'hw0_last_tls_le'
This modifier yields the same value as 'hw0_tls_le', but it also
checks that the value does not overflow.
'hw1_last_tls_le'
This modifier is used to load bits 16-31 of the offset of the
symbol's address from the TCB, to be used for local-exec TLS
accesses. It also checks that the value does not overflow.
'tls_gd_call'
This modifier is used to tag an instrution as the "call" part of a
calling sequence for a TLS GD reference of its operand.
'tls_gd_add'
This modifier is used to tag an instruction as the "add" part of a
calling sequence for a TLS GD reference of its operand.
'tls_ie_load'
This modifier is used to tag an instruction as the "load" part of a
calling sequence for a TLS IE reference of its operand.

File: as.info, Node: TILE-Gx Directives, Prev: TILE-Gx Syntax, Up: TILE-Gx-Dependent
9.45.3 TILE-Gx Directives
-------------------------
'.align EXPRESSION [, EXPRESSION]'
This is the generic .ALIGN directive. The first argument is the
requested alignment in bytes.
'.allow_suspicious_bundles'
Turns on error checking for combinations of instructions in a
bundle that probably indicate a programming error. This is on by
default.
'.no_allow_suspicious_bundles'
Turns off error checking for combinations of instructions in a
bundle that probably indicate a programming error.
'.require_canonical_reg_names'
Require that canonical register names be used, and emit a warning
if the numeric names are used. This is on by default.
'.no_require_canonical_reg_names'
Permit the use of numeric names for registers that have canonical
names.

File: as.info, Node: TILEPro-Dependent, Next: Z80-Dependent, Prev: TILE-Gx-Dependent, Up: Machine Dependencies
9.46 TILEPro Dependent Features
===============================
* Menu:
* TILEPro Options:: TILEPro Options
* TILEPro Syntax:: TILEPro Syntax
* TILEPro Directives:: TILEPro Directives

File: as.info, Node: TILEPro Options, Next: TILEPro Syntax, Up: TILEPro-Dependent
9.46.1 Options
--------------
'as' has no machine-dependent command-line options for TILEPro.

File: as.info, Node: TILEPro Syntax, Next: TILEPro Directives, Prev: TILEPro Options, Up: TILEPro-Dependent
9.46.2 Syntax
-------------
Block comments are delimited by '/*' and '*/'. End of line comments may
be introduced by '#'.
Instructions consist of a leading opcode or macro name followed by
whitespace and an optional comma-separated list of operands:
OPCODE [OPERAND, ...]
Instructions must be separated by a newline or semicolon.
There are two ways to write code: either write naked instructions,
which the assembler is free to combine into VLIW bundles, or specify the
VLIW bundles explicitly.
Bundles are specified using curly braces:
{ ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 }
A bundle can span multiple lines. If you want to put multiple
instructions on a line, whether in a bundle or not, you need to separate
them with semicolons as in this example.
A bundle may contain one or more instructions, up to the limit
specified by the ISA (currently three). If fewer instructions are
specified than the hardware supports in a bundle, the assembler inserts
'fnop' instructions automatically.
The assembler will prefer to preserve the ordering of instructions
within the bundle, putting the first instruction in a lower-numbered
pipeline than the next one, etc. This fact, combined with the optional
use of explicit 'fnop' or 'nop' instructions, allows precise control
over which pipeline executes each instruction.
If the instructions cannot be bundled in the listed order, the
assembler will automatically try to find a valid pipeline assignment.
If there is no way to bundle the instructions together, the assembler
reports an error.
The assembler does not yet auto-bundle (automatically combine
multiple instructions into one bundle), but it reserves the right to do
so in the future. If you want to force an instruction to run by itself,
put it in a bundle explicitly with curly braces and use 'nop'
instructions (not 'fnop') to fill the remaining pipeline slots in that
bundle.
* Menu:
* TILEPro Opcodes:: Opcode Naming Conventions.
* TILEPro Registers:: Register Naming.
* TILEPro Modifiers:: Symbolic Operand Modifiers.

File: as.info, Node: TILEPro Opcodes, Next: TILEPro Registers, Up: TILEPro Syntax
9.46.2.1 Opcode Names
.....................
For a complete list of opcodes and descriptions of their semantics, see
'TILE Processor User Architecture Manual', available upon request at
www.tilera.com.

File: as.info, Node: TILEPro Registers, Next: TILEPro Modifiers, Prev: TILEPro Opcodes, Up: TILEPro Syntax
9.46.2.2 Register Names
.......................
General-purpose registers are represented by predefined symbols of the
form 'rN', where N represents a number between '0' and '63'. However,
the following registers have canonical names that must be used instead:
'r54'
sp
'r55'
lr
'r56'
sn
'r57'
idn0
'r58'
idn1
'r59'
udn0
'r60'
udn1
'r61'
udn2
'r62'
udn3
'r63'
zero
The assembler will emit a warning if a numeric name is used instead
of the canonical name. The '.no_require_canonical_reg_names' assembler
pseudo-op turns off this warning. '.require_canonical_reg_names' turns
it back on.

File: as.info, Node: TILEPro Modifiers, Prev: TILEPro Registers, Up: TILEPro Syntax
9.46.2.3 Symbolic Operand Modifiers
...................................
The assembler supports several modifiers when using symbol addresses in
TILEPro instruction operands. The general syntax is the following:
modifier(symbol)
The following modifiers are supported:
'lo16'
This modifier is used to load the low 16 bits of the symbol's
address, sign-extended to a 32-bit value (sign-extension allows it
to be range-checked against signed 16 bit immediate operands
without complaint).
'hi16'
This modifier is used to load the high 16 bits of the symbol's
address, also sign-extended to a 32-bit value.
'ha16'
'ha16(N)' is identical to 'hi16(N)', except if 'lo16(N)' is
negative it adds one to the 'hi16(N)' value. This way 'lo16' and
'ha16' can be added to create any 32-bit value using 'auli'. For
example, here is how you move an arbitrary 32-bit address into r3:
moveli r3, lo16(sym)
auli r3, r3, ha16(sym)
'got'
This modifier is used to load the offset of the GOT entry
corresponding to the symbol.
'got_lo16'
This modifier is used to load the sign-extended low 16 bits of the
offset of the GOT entry corresponding to the symbol.
'got_hi16'
This modifier is used to load the sign-extended high 16 bits of the
offset of the GOT entry corresponding to the symbol.
'got_ha16'
This modifier is like 'got_hi16', but it adds one if 'got_lo16' of
the input value is negative.
'plt'
This modifier is used for function symbols. It causes a _procedure
linkage table_, an array of code stubs, to be created at the time
the shared object is created or linked against, together with a
global offset table entry. The value is a pc-relative offset to
the corresponding stub code in the procedure linkage table. This
arrangement causes the run-time symbol resolver to be called to
look up and set the value of the symbol the first time the function
is called (at latest; depending environment variables). It is only
safe to leave the symbol unresolved this way if all references are
function calls.
'tls_gd'
This modifier is used to load the offset of the GOT entry of the
symbol's TLS descriptor, to be used for general-dynamic TLS
accesses.
'tls_gd_lo16'
This modifier is used to load the sign-extended low 16 bits of the
offset of the GOT entry of the symbol's TLS descriptor, to be used
for general dynamic TLS accesses.
'tls_gd_hi16'
This modifier is used to load the sign-extended high 16 bits of the
offset of the GOT entry of the symbol's TLS descriptor, to be used
for general dynamic TLS accesses.
'tls_gd_ha16'
This modifier is like 'tls_gd_hi16', but it adds one to the value
if 'tls_gd_lo16' of the input value is negative.
'tls_ie'
This modifier is used to load the offset of the GOT entry
containing the offset of the symbol's address from the TCB, to be
used for initial-exec TLS accesses.
'tls_ie_lo16'
This modifier is used to load the low 16 bits of the offset of the
GOT entry containing the offset of the symbol's address from the
TCB, to be used for initial-exec TLS accesses.
'tls_ie_hi16'
This modifier is used to load the high 16 bits of the offset of the
GOT entry containing the offset of the symbol's address from the
TCB, to be used for initial-exec TLS accesses.
'tls_ie_ha16'
This modifier is like 'tls_ie_hi16', but it adds one to the value
if 'tls_ie_lo16' of the input value is negative.
'tls_le'
This modifier is used to load the offset of the symbol's address
from the TCB, to be used for local-exec TLS accesses.
'tls_le_lo16'
This modifier is used to load the low 16 bits of the offset of the
symbol's address from the TCB, to be used for local-exec TLS
accesses.
'tls_le_hi16'
This modifier is used to load the high 16 bits of the offset of the
symbol's address from the TCB, to be used for local-exec TLS
accesses.
'tls_le_ha16'
This modifier is like 'tls_le_hi16', but it adds one to the value
if 'tls_le_lo16' of the input value is negative.
'tls_gd_call'
This modifier is used to tag an instrution as the "call" part of a
calling sequence for a TLS GD reference of its operand.
'tls_gd_add'
This modifier is used to tag an instruction as the "add" part of a
calling sequence for a TLS GD reference of its operand.
'tls_ie_load'
This modifier is used to tag an instruction as the "load" part of a
calling sequence for a TLS IE reference of its operand.

File: as.info, Node: TILEPro Directives, Prev: TILEPro Syntax, Up: TILEPro-Dependent
9.46.3 TILEPro Directives
-------------------------
'.align EXPRESSION [, EXPRESSION]'
This is the generic .ALIGN directive. The first argument is the
requested alignment in bytes.
'.allow_suspicious_bundles'
Turns on error checking for combinations of instructions in a
bundle that probably indicate a programming error. This is on by
default.
'.no_allow_suspicious_bundles'
Turns off error checking for combinations of instructions in a
bundle that probably indicate a programming error.
'.require_canonical_reg_names'
Require that canonical register names be used, and emit a warning
if the numeric names are used. This is on by default.
'.no_require_canonical_reg_names'
Permit the use of numeric names for registers that have canonical
names.

File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: TILEPro-Dependent, Up: Machine Dependencies
9.47 Z80 Dependent Features
===========================
* Menu:
* Z80 Options:: Options
* Z80 Syntax:: Syntax
* Z80 Floating Point:: Floating Point
* Z80 Directives:: Z80 Machine Directives
* Z80 Opcodes:: Opcodes

File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent
9.47.1 Options
--------------
The Zilog Z80 and Ascii R800 version of 'as' have a few machine
dependent options.
'-z80'
Produce code for the Z80 processor. There are additional options
to request warnings and error messages for undocumented
instructions.
'-ignore-undocumented-instructions'
'-Wnud'
Silently assemble undocumented Z80-instructions that have been
adopted as documented R800-instructions.
'-ignore-unportable-instructions'
'-Wnup'
Silently assemble all undocumented Z80-instructions.
'-warn-undocumented-instructions'
'-Wud'
Issue warnings for undocumented Z80-instructions that work on R800,
do not assemble other undocumented instructions without warning.
'-warn-unportable-instructions'
'-Wup'
Issue warnings for other undocumented Z80-instructions, do not
treat any undocumented instructions as errors.
'-forbid-undocumented-instructions'
'-Fud'
Treat all undocumented z80-instructions as errors.
'-forbid-unportable-instructions'
'-Fup'
Treat undocumented z80-instructions that do not work on R800 as
errors.
'-r800'
Produce code for the R800 processor. The assembler does not
support undocumented instructions for the R800. In line with
common practice, 'as' uses Z80 instruction names for the R800
processor, as far as they exist.

File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent
9.47.2 Syntax
-------------
The assembler syntax closely follows the 'Z80 family CPU User Manual' by
Zilog. In expressions a single '=' may be used as "is equal to"
comparison operator.
Suffices can be used to indicate the radix of integer constants; 'H'
or 'h' for hexadecimal, 'D' or 'd' for decimal, 'Q', 'O', 'q' or 'o' for
octal, and 'B' for binary.
The suffix 'b' denotes a backreference to local label.
* Menu:
* Z80-Chars:: Special Characters
* Z80-Regs:: Register Names
* Z80-Case:: Case Sensitivity

File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax
9.47.2.1 Special Characters
...........................
The semicolon ';' is the line comment character;
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line could also be a
logical line number directive (*note Comments::) or a preprocessor
control command (*note Preprocessing::).
The Z80 assembler does not support a line separator character.
The dollar sign '$' can be used as a prefix for hexadecimal numbers
and as a symbol denoting the current location counter.
A backslash '\' is an ordinary character for the Z80 assembler.
The single quote ''' must be followed by a closing quote. If there
is one character in between, it is a character constant, otherwise it is
a string constant.

File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax
9.47.2.2 Register Names
.......................
The registers are referred to with the letters assigned to them by
Zilog. In addition 'as' recognizes 'ixl' and 'ixh' as the least and
most significant octet in 'ix', and similarly 'iyl' and 'iyh' as parts
of 'iy'.

File: as.info, Node: Z80-Case, Prev: Z80-Regs, Up: Z80 Syntax
9.47.2.3 Case Sensitivity
.........................
Upper and lower case are equivalent in register names, opcodes,
condition codes and assembler directives. The case of letters is
significant in labels and symbol names. The case is also important to
distinguish the suffix 'b' for a backward reference to a local label
from the suffix 'B' for a number in binary notation.

File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent
9.47.3 Floating Point
---------------------
Floating-point numbers are not supported.

File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent
9.47.4 Z80 Assembler Directives
-------------------------------
'as' for the Z80 supports some additional directives for compatibility
with other assemblers.
These are the additional directives in 'as' for the Z80:
'db EXPRESSION|STRING[,EXPRESSION|STRING...]'
'defb EXPRESSION|STRING[,EXPRESSION|STRING...]'
For each STRING the characters are copied to the object file, for
each other EXPRESSION the value is stored in one byte. A warning
is issued in case of an overflow.
'dw EXPRESSION[,EXPRESSION...]'
'defw EXPRESSION[,EXPRESSION...]'
For each EXPRESSION the value is stored in two bytes, ignoring
overflow.
'd24 EXPRESSION[,EXPRESSION...]'
'def24 EXPRESSION[,EXPRESSION...]'
For each EXPRESSION the value is stored in three bytes, ignoring
overflow.
'd32 EXPRESSION[,EXPRESSION...]'
'def32 EXPRESSION[,EXPRESSION...]'
For each EXPRESSION the value is stored in four bytes, ignoring
overflow.
'ds COUNT[, VALUE]'
'defs COUNT[, VALUE]'
Fill COUNT bytes in the object file with VALUE, if VALUE is omitted
it defaults to zero.
'SYMBOL equ EXPRESSION'
'SYMBOL defl EXPRESSION'
These directives set the value of SYMBOL to EXPRESSION. If 'equ'
is used, it is an error if SYMBOL is already defined. Symbols
defined with 'equ' are not protected from redefinition.
'set'
This is a normal instruction on Z80, and not an assembler
directive.
'psect NAME'
A synonym for *Note Section::, no second argument should be given.

File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent
9.47.5 Opcodes
--------------
In line with common practice, Z80 mnemonics are used for both the Z80
and the R800.
In many instructions it is possible to use one of the half index
registers ('ixl','ixh','iyl','iyh') in stead of an 8-bit general purpose
register. This yields instructions that are documented on the R800 and
undocumented on the Z80. Similarly 'in f,(c)' is documented on the R800
and undocumented on the Z80.
The assembler also supports the following undocumented
Z80-instructions, that have not been adopted in the R800 instruction
set:
'out (c),0'
Sends zero to the port pointed to by register c.
'sli M'
Equivalent to 'M = (M<<1)+1', the operand M can be any operand that
is valid for 'sla'. One can use 'sll' as a synonym for 'sli'.
'OP (ix+D), R'
This is equivalent to
ld R, (ix+D)
OPC R
ld (ix+D), R
The operation 'OPC' may be any of 'res B,', 'set B,', 'rl', 'rlc',
'rr', 'rrc', 'sla', 'sli', 'sra' and 'srl', and the register 'R'
may be any of 'a', 'b', 'c', 'd', 'e', 'h' and 'l'.
'OPC (iy+D), R'
As above, but with 'iy' instead of 'ix'.
The web site at <http://www.z80.info> is a good starting place to
find more information on programming the Z80.

File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies
9.48 Z8000 Dependent Features
=============================
The Z8000 as supports both members of the Z8000 family: the unsegmented
Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit
addresses.
When the assembler is in unsegmented mode (specified with the
'unsegm' directive), an address takes up one word (16 bit) sized
register. When the assembler is in segmented mode (specified with the
'segm' directive), a 24-bit address takes up a long (32 bit) register.
*Note Assembler Directives for the Z8000: Z8000 Directives, for a list
of other Z8000 specific assembler directives.
* Menu:
* Z8000 Options:: Command-line options for the Z8000
* Z8000 Syntax:: Assembler syntax for the Z8000
* Z8000 Directives:: Special directives for the Z8000
* Z8000 Opcodes:: Opcodes

File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent
9.48.1 Options
--------------
'-z8001'
Generate segmented code by default.
'-z8002'
Generate unsegmented code by default.

File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent
9.48.2 Syntax
-------------
* Menu:
* Z8000-Chars:: Special Characters
* Z8000-Regs:: Register Names
* Z8000-Addressing:: Addressing Modes

File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax
9.48.2.1 Special Characters
...........................
'!' is the line comment character.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line could also be a
logical line number directive (*note Comments::) or a preprocessor
control command (*note Preprocessing::).
You can use ';' instead of a newline to separate statements.

File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax
9.48.2.2 Register Names
.......................
The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer
to different sized groups of registers by register number, with the
prefix 'r' for 16 bit registers, 'rr' for 32 bit registers and 'rq' for
64 bit registers. You can also refer to the contents of the first eight
(of the sixteen 16 bit registers) by bytes. They are named 'rlN' and
'rhN'.
_byte registers_
rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3
rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7
_word registers_
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
_long word registers_
rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
_quad word registers_
rq0 rq4 rq8 rq12

File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax
9.48.2.3 Addressing Modes
.........................
as understands the following addressing modes for the Z8000:
'rlN'
'rhN'
'rN'
'rrN'
'rqN'
Register direct: 8bit, 16bit, 32bit, and 64bit registers.
'@rN'
'@rrN'
Indirect register: @rrN in segmented mode, @rN in unsegmented mode.
'ADDR'
Direct: the 16 bit or 24 bit address (depending on whether the
assembler is in segmented or unsegmented mode) of the operand is in
the instruction.
'address(rN)'
Indexed: the 16 or 24 bit address is added to the 16 bit register
to produce the final address in memory of the operand.
'rN(#IMM)'
'rrN(#IMM)'
Base Address: the 16 or 24 bit register is added to the 16 bit sign
extended immediate displacement to produce the final address in
memory of the operand.
'rN(rM)'
'rrN(rM)'
Base Index: the 16 or 24 bit register rN or rrN is added to the
sign extended 16 bit index register rM to produce the final address
in memory of the operand.
'#XX'
Immediate data XX.

File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent
9.48.3 Assembler Directives for the Z8000
-----------------------------------------
The Z8000 port of as includes additional assembler directives, for
compatibility with other Z8000 assemblers. These do not begin with '.'
(unlike the ordinary as directives).
'segm'
'.z8001'
Generate code for the segmented Z8001.
'unsegm'
'.z8002'
Generate code for the unsegmented Z8002.
'name'
Synonym for '.file'
'global'
Synonym for '.global'
'wval'
Synonym for '.word'
'lval'
Synonym for '.long'
'bval'
Synonym for '.byte'
'sval'
Assemble a string. 'sval' expects one string literal, delimited by
single quotes. It assembles each byte of the string into
consecutive addresses. You can use the escape sequence '%XX'
(where XX represents a two-digit hexadecimal number) to represent
the character whose ASCII value is XX. Use this feature to
describe single quote and other characters that may not appear in
string literals as themselves. For example, the C statement 'char *a = "he said \"it's 50% off\"";'
is represented in Z8000 assembly language (shown with the assembler
output in hex at the left) as
68652073 sval 'he said %22it%27s 50%25 off%22%00'
61696420
22697427
73203530
25206F66
662200
'rsect'
synonym for '.section'
'block'
synonym for '.space'
'even'
special case of '.align'; aligns output to even byte boundary.

File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent
9.48.4 Opcodes
--------------
For detailed information on the Z8000 machine instruction set, see
'Z8000 Technical Manual'.
The following table summarizes the opcodes and their arguments:
rs 16 bit source register
rd 16 bit destination register
rbs 8 bit source register
rbd 8 bit destination register
rrs 32 bit source register
rrd 32 bit destination register
rqs 64 bit source register
rqd 64 bit destination register
addr 16/24 bit address
imm immediate data
adc rd,rs clrb addr cpsir @rd,@rs,rr,cc
adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc
add rd,@rs clrb rbd dab rbd
add rd,addr com @rd dbjnz rbd,disp7
add rd,addr(rs) com addr dec @rd,imm4m1
add rd,imm16 com addr(rd) dec addr(rd),imm4m1
add rd,rs com rd dec addr,imm4m1
addb rbd,@rs comb @rd dec rd,imm4m1
addb rbd,addr comb addr decb @rd,imm4m1
addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1
addb rbd,imm8 comb rbd decb addr,imm4m1
addb rbd,rbs comflg flags decb rbd,imm4m1
addl rrd,@rs cp @rd,imm16 di i2
addl rrd,addr cp addr(rd),imm16 div rrd,@rs
addl rrd,addr(rs) cp addr,imm16 div rrd,addr
addl rrd,imm32 cp rd,@rs div rrd,addr(rs)
addl rrd,rrs cp rd,addr div rrd,imm16
and rd,@rs cp rd,addr(rs) div rrd,rs
and rd,addr cp rd,imm16 divl rqd,@rs
and rd,addr(rs) cp rd,rs divl rqd,addr
and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs)
and rd,rs cpb addr(rd),imm8 divl rqd,imm32
andb rbd,@rs cpb addr,imm8 divl rqd,rrs
andb rbd,addr cpb rbd,@rs djnz rd,disp7
andb rbd,addr(rs) cpb rbd,addr ei i2
andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs
andb rbd,rbs cpb rbd,imm8 ex rd,addr
bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs)
bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs
bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs
bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr
bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs)
bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs
bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8
bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8
bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8
bitb rbd,rs cpl rrd,@rs ext8f imm8
bpt cpl rrd,addr exts rrd
call @rd cpl rrd,addr(rs) extsb rd
call addr cpl rrd,imm32 extsl rqd
call addr(rd) cpl rrd,rrs halt
calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs
clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16
clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs
clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16
clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1
clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1
inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs)
inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16
incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs
incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs
incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr
incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs)
ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32
indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs
inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd
inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr
iret ldib @rd,@rs,rr neg addr(rd)
jp cc,@rd ldir @rd,@rs,rr neg rd
jp cc,addr ldirb @rd,@rs,rr negb @rd
jp cc,addr(rd) ldk rd,imm4 negb addr
jr cc,disp8 ldl @rd,rrs negb addr(rd)
ld @rd,imm16 ldl addr(rd),rrs negb rbd
ld @rd,rs ldl addr,rrs nop
ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs
ld addr(rd),rs ldl rd(rx),rrs or rd,addr
ld addr,imm16 ldl rrd,@rs or rd,addr(rs)
ld addr,rs ldl rrd,addr or rd,imm16
ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs
ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs
ld rd,@rs ldl rrd,rrs orb rbd,addr
ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs)
ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8
ld rd,imm16 ldm @rd,rs,n orb rbd,rbs
ld rd,rs ldm addr(rd),rs,n out @rd,rs
ld rd,rs(imm16) ldm addr,rs,n out imm16,rs
ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs
lda rd,addr ldm rd,addr(rs),n outb imm16,rbs
lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra
lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba
lda rd,rs(rx) ldps addr outib @rd,@rs,ra
ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra
ldb @rd,imm8 ldr disp16,rs pop @rd,@rs
ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs
ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs
ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs
ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs
ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs
ldb rbd,@rs mbit popl addr,@rs
ldb rbd,addr mreq rd popl rrd,@rs
ldb rbd,addr(rs) mres push @rd,@rs
ldb rbd,imm8 mset push @rd,addr
ldb rbd,rbs mult rrd,@rs push @rd,addr(rs)
ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16
push @rd,rs set addr,imm4 subl rrd,imm32
pushl @rd,@rs set rd,imm4 subl rrd,rrs
pushl @rd,addr set rd,rs tcc cc,rd
pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd
pushl @rd,rrs setb addr(rd),imm4 test @rd
res @rd,imm4 setb addr,imm4 test addr
res addr(rd),imm4 setb rbd,imm4 test addr(rd)
res addr,imm4 setb rbd,rs test rd
res rd,imm4 setflg imm4 testb @rd
res rd,rs sinb rbd,imm16 testb addr
resb @rd,imm4 sinb rd,imm16 testb addr(rd)
resb addr(rd),imm4 sind @rd,@rs,ra testb rbd
resb addr,imm4 sindb @rd,@rs,rba testl @rd
resb rbd,imm4 sinib @rd,@rs,ra testl addr
resb rbd,rs sinibr @rd,@rs,ra testl addr(rd)
resflg imm4 sla rd,imm8 testl rrd
ret cc slab rbd,imm8 trdb @rd,@rs,rba
rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba
rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr
rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr
rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr
rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr
rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr
rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr
rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd
rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr
rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd)
rsvd36 sra rd,imm8 tset rd
rsvd38 srab rbd,imm8 tsetb @rd
rsvd78 sral rrd,imm8 tsetb addr
rsvd7e srl rd,imm8 tsetb addr(rd)
rsvd9d srlb rbd,imm8 tsetb rbd
rsvd9f srll rrd,imm8 xor rd,@rs
rsvdb9 sub rd,@rs xor rd,addr
rsvdbf sub rd,addr xor rd,addr(rs)
sbc rd,rs sub rd,addr(rs) xor rd,imm16
sbcb rbd,rbs sub rd,imm16 xor rd,rs
sc imm8 sub rd,rs xorb rbd,@rs
sda rd,rs subb rbd,@rs xorb rbd,addr
sdab rbd,rs subb rbd,addr xorb rbd,addr(rs)
sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8
sdl rd,rs subb rbd,imm8 xorb rbd,rbs
sdlb rbd,rs subb rbd,rbs xorb rbd,rbs
sdll rrd,rs subl rrd,@rs
set @rd,imm4 subl rrd,addr
set addr(rd),imm4 subl rrd,addr(rs)

File: as.info, Node: Vax-Dependent, Next: V850-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies
9.49 VAX Dependent Features
===========================
* Menu:
* VAX-Opts:: VAX Command-Line Options
* VAX-float:: VAX Floating Point
* VAX-directives:: Vax Machine Directives
* VAX-opcodes:: VAX Opcodes
* VAX-branch:: VAX Branch Improvement
* VAX-operands:: VAX Operands
* VAX-no:: Not Supported on VAX
* VAX-Syntax:: VAX Syntax

File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent
9.49.1 VAX Command-Line Options
-------------------------------
The Vax version of 'as' accepts any of the following options, gives a
warning message that the option was ignored and proceeds. These options
are for compatibility with scripts designed for other people's
assemblers.
'-D (Debug)'
'-S (Symbol Table)'
'-T (Token Trace)'
These are obsolete options used to debug old assemblers.
'-d (Displacement size for JUMPs)'
This option expects a number following the '-d'. Like options that
expect filenames, the number may immediately follow the '-d' (old
standard) or constitute the whole of the command line argument that
follows '-d' (GNU standard).
'-V (Virtualize Interpass Temporary File)'
Some other assemblers use a temporary file. This option commanded
them to keep the information in active memory rather than in a disk
file. 'as' always does this, so this option is redundant.
'-J (JUMPify Longer Branches)'
Many 32-bit computers permit a variety of branch instructions to do
the same job. Some of these instructions are short (and fast) but
have a limited range; others are long (and slow) but can branch
anywhere in virtual memory. Often there are 3 flavors of branch:
short, medium and long. Some other assemblers would emit short and
medium branches, unless told by this option to emit short and long
branches.
'-t (Temporary File Directory)'
Some other assemblers may use a temporary file, and this option
takes a filename being the directory to site the temporary file.
Since 'as' does not use a temporary disk file, this option makes no
difference. '-t' needs exactly one filename.
The Vax version of the assembler accepts additional options when
compiled for VMS:
'-h N'
External symbol or section (used for global variables) names are
not case sensitive on VAX/VMS and always mapped to upper case.
This is contrary to the C language definition which explicitly
distinguishes upper and lower case. To implement a standard
conforming C compiler, names must be changed (mapped) to preserve
the case information. The default mapping is to convert all lower
case characters to uppercase and adding an underscore followed by a
6 digit hex value, representing a 24 digit binary value. The one
digits in the binary value represent which characters are uppercase
in the original symbol name.
The '-h N' option determines how we map names. This takes several
values. No '-h' switch at all allows case hacking as described
above. A value of zero ('-h0') implies names should be upper case,
and inhibits the case hack. A value of 2 ('-h2') implies names
should be all lower case, with no case hack. A value of 3 ('-h3')
implies that case should be preserved. The value 1 is unused. The
'-H' option directs 'as' to display every mapped symbol during
assembly.
Symbols whose names include a dollar sign '$' are exceptions to the
general name mapping. These symbols are normally only used to
reference VMS library names. Such symbols are always mapped to
upper case.
'-+'
The '-+' option causes 'as' to truncate any symbol name larger than
31 characters. The '-+' option also prevents some code following
the '_main' symbol normally added to make the object file
compatible with Vax-11 "C".
'-1'
This option is ignored for backward compatibility with 'as' version
1.x.
'-H'
The '-H' option causes 'as' to print every symbol which was changed
by case mapping.

File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent
9.49.2 VAX Floating Point
-------------------------
Conversion of flonums to floating point is correct, and compatible with
previous assemblers. Rounding is towards zero if the remainder is
exactly half the least significant bit.
'D', 'F', 'G' and 'H' floating point formats are understood.
Immediate floating literals (_e.g._ 'S`$6.9') are rendered
correctly. Again, rounding is towards zero in the boundary case.
The '.float' directive produces 'f' format numbers. The '.double'
directive produces 'd' format numbers.

File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent
9.49.3 Vax Machine Directives
-----------------------------
The Vax version of the assembler supports four directives for generating
Vax floating point constants. They are described in the table below.
'.dfloat'
This expects zero or more flonums, separated by commas, and
assembles Vax 'd' format 64-bit floating point constants.
'.ffloat'
This expects zero or more flonums, separated by commas, and
assembles Vax 'f' format 32-bit floating point constants.
'.gfloat'
This expects zero or more flonums, separated by commas, and
assembles Vax 'g' format 64-bit floating point constants.
'.hfloat'
This expects zero or more flonums, separated by commas, and
assembles Vax 'h' format 128-bit floating point constants.

File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent
9.49.4 VAX Opcodes
------------------
All DEC mnemonics are supported. Beware that 'case...' instructions
have exactly 3 operands. The dispatch table that follows the 'case...'
instruction should be made with '.word' statements. This is compatible
with all unix assemblers we know of.

File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent
9.49.5 VAX Branch Improvement
-----------------------------
Certain pseudo opcodes are permitted. They are for branch instructions.
They expand to the shortest branch instruction that reaches the target.
Generally these mnemonics are made by substituting 'j' for 'b' at the
start of a DEC mnemonic. This feature is included both for
compatibility and to help compilers. If you do not need this feature,
avoid these opcodes. Here are the mnemonics, and the code they can
expand into.
'jbsb'
'Jsb' is already an instruction mnemonic, so we chose 'jbsb'.
(byte displacement)
'bsbb ...'
(word displacement)
'bsbw ...'
(long displacement)
'jsb ...'
'jbr'
'jr'
Unconditional branch.
(byte displacement)
'brb ...'
(word displacement)
'brw ...'
(long displacement)
'jmp ...'
'jCOND'
COND may be any one of the conditional branches 'neq', 'nequ',
'eql', 'eqlu', 'gtr', 'geq', 'lss', 'gtru', 'lequ', 'vc', 'vs',
'gequ', 'cc', 'lssu', 'cs'. COND may also be one of the bit tests
'bs', 'bc', 'bss', 'bcs', 'bsc', 'bcc', 'bssi', 'bcci', 'lbs',
'lbc'. NOTCOND is the opposite condition to COND.
(byte displacement)
'bCOND ...'
(word displacement)
'bNOTCOND foo ; brw ... ; foo:'
(long displacement)
'bNOTCOND foo ; jmp ... ; foo:'
'jacbX'
X may be one of 'b d f g h l w'.
(word displacement)
'OPCODE ...'
(long displacement)
OPCODE ..., foo ;
brb bar ;
foo: jmp ... ;
bar:
'jaobYYY'
YYY may be one of 'lss leq'.
'jsobZZZ'
ZZZ may be one of 'geq gtr'.
(byte displacement)
'OPCODE ...'
(word displacement)
OPCODE ..., foo ;
brb bar ;
foo: brw DESTINATION ;
bar:
(long displacement)
OPCODE ..., foo ;
brb bar ;
foo: jmp DESTINATION ;
bar:
'aobleq'
'aoblss'
'sobgeq'
'sobgtr'
(byte displacement)
'OPCODE ...'
(word displacement)
OPCODE ..., foo ;
brb bar ;
foo: brw DESTINATION ;
bar:
(long displacement)
OPCODE ..., foo ;
brb bar ;
foo: jmp DESTINATION ;
bar:

File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent
9.49.6 VAX Operands
-------------------
The immediate character is '$' for Unix compatibility, not '#' as DEC
writes it.
The indirect character is '*' for Unix compatibility, not '@' as DEC
writes it.
The displacement sizing character is '`' (an accent grave) for Unix
compatibility, not '^' as DEC writes it. The letter preceding '`' may
have either case. 'G' is not understood, but all other letters ('b i l
s w') are understood.
Register names understood are 'r0 r1 r2 ... r15 ap fp sp pc'. Upper
and lower case letters are equivalent.
For instance
tstb *w`$4(r5)
Any expression is permitted in an operand. Operands are comma
separated.

File: as.info, Node: VAX-no, Next: VAX-Syntax, Prev: VAX-operands, Up: Vax-Dependent
9.49.7 Not Supported on VAX
---------------------------
Vax bit fields can not be assembled with 'as'. Someone can add the
required code if they really need it.

File: as.info, Node: VAX-Syntax, Prev: VAX-no, Up: Vax-Dependent
9.49.8 VAX Syntax
-----------------
* Menu:
* VAX-Chars:: Special Characters

File: as.info, Node: VAX-Chars, Up: VAX-Syntax
9.49.8.1 Special Characters
...........................
The presence of a '#' appearing anywhere on a line indicates the start
of a comment that extends to the end of that line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
The ';' character can be used to separate statements on the same
line.

File: as.info, Node: V850-Dependent, Next: XGATE-Dependent, Prev: Vax-Dependent, Up: Machine Dependencies
9.50 v850 Dependent Features
============================
* Menu:
* V850 Options:: Options
* V850 Syntax:: Syntax
* V850 Floating Point:: Floating Point
* V850 Directives:: V850 Machine Directives
* V850 Opcodes:: Opcodes

File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent
9.50.1 Options
--------------
'as' supports the following additional command-line options for the V850
processor family:
'-wsigned_overflow'
Causes warnings to be produced when signed immediate values
overflow the space available for then within their opcodes. By
default this option is disabled as it is possible to receive
spurious warnings due to using exact bit patterns as immediate
constants.
'-wunsigned_overflow'
Causes warnings to be produced when unsigned immediate values
overflow the space available for then within their opcodes. By
default this option is disabled as it is possible to receive
spurious warnings due to using exact bit patterns as immediate
constants.
'-mv850'
Specifies that the assembled code should be marked as being
targeted at the V850 processor. This allows the linker to detect
attempts to link such code with code assembled for other
processors.
'-mv850e'
Specifies that the assembled code should be marked as being
targeted at the V850E processor. This allows the linker to detect
attempts to link such code with code assembled for other
processors.
'-mv850e1'
Specifies that the assembled code should be marked as being
targeted at the V850E1 processor. This allows the linker to detect
attempts to link such code with code assembled for other
processors.
'-mv850any'
Specifies that the assembled code should be marked as being
targeted at the V850 processor but support instructions that are
specific to the extended variants of the process. This allows the
production of binaries that contain target specific code, but which
are also intended to be used in a generic fashion. For example
libgcc.a contains generic routines used by the code produced by GCC
for all versions of the v850 architecture, together with support
routines only used by the V850E architecture.
'-mv850e2'
Specifies that the assembled code should be marked as being
targeted at the V850E2 processor. This allows the linker to detect
attempts to link such code with code assembled for other
processors.
'-mv850e2v3'
Specifies that the assembled code should be marked as being
targeted at the V850E2V3 processor. This allows the linker to
detect attempts to link such code with code assembled for other
processors.
'-mv850e2v4'
This is an alias for '-mv850e3v5'.
'-mv850e3v5'
Specifies that the assembled code should be marked as being
targeted at the V850E3V5 processor. This allows the linker to
detect attempts to link such code with code assembled for other
processors.
'-mrelax'
Enables relaxation. This allows the .longcall and .longjump pseudo
ops to be used in the assembler source code. These ops label
sections of code which are either a long function call or a long
branch. The assembler will then flag these sections of code and
the linker will attempt to relax them.
'-mgcc-abi'
Marks the generated objecy file as supporting the old GCC ABI.
'-mrh850-abi'
Marks the generated objecy file as supporting the RH850 ABI. This
is the default.
'-m8byte-align'
Marks the generated objecy file as supporting a maximum 64-bits of
alignment for variables defined in the source code.
'-m4byte-align'
Marks the generated objecy file as supporting a maximum 32-bits of
alignment for variables defined in the source code. This is the
default.

File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent
9.50.2 Syntax
-------------
* Menu:
* V850-Chars:: Special Characters
* V850-Regs:: Register Names

File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax
9.50.2.1 Special Characters
...........................
'#' is the line comment character. If a '#' appears as the first
character of a line, the whole line is treated as a comment, but in this
case the line can also be a logical line number directive (*note
Comments::) or a preprocessor control command (*note Preprocessing::).
Two dashes ('--') can also be used to start a line comment.
The ';' character can be used to separate statements on the same
line.

File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax
9.50.2.2 Register Names
.......................
'as' supports the following names for registers:
'general register 0'
r0, zero
'general register 1'
r1
'general register 2'
r2, hp
'general register 3'
r3, sp
'general register 4'
r4, gp
'general register 5'
r5, tp
'general register 6'
r6
'general register 7'
r7
'general register 8'
r8
'general register 9'
r9
'general register 10'
r10
'general register 11'
r11
'general register 12'
r12
'general register 13'
r13
'general register 14'
r14
'general register 15'
r15
'general register 16'
r16
'general register 17'
r17
'general register 18'
r18
'general register 19'
r19
'general register 20'
r20
'general register 21'
r21
'general register 22'
r22
'general register 23'
r23
'general register 24'
r24
'general register 25'
r25
'general register 26'
r26
'general register 27'
r27
'general register 28'
r28
'general register 29'
r29
'general register 30'
r30, ep
'general register 31'
r31, lp
'system register 0'
eipc
'system register 1'
eipsw
'system register 2'
fepc
'system register 3'
fepsw
'system register 4'
ecr
'system register 5'
psw
'system register 16'
ctpc
'system register 17'
ctpsw
'system register 18'
dbpc
'system register 19'
dbpsw
'system register 20'
ctbp

File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent
9.50.3 Floating Point
---------------------
The V850 family uses IEEE floating-point numbers.

File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent
9.50.4 V850 Machine Directives
------------------------------
'.offset <EXPRESSION>'
Moves the offset into the current section to the specified amount.
'.section "name", <type>'
This is an extension to the standard .section directive. It sets
the current section to be <type> and creates an alias for this
section called "name".
'.v850'
Specifies that the assembled code should be marked as being
targeted at the V850 processor. This allows the linker to detect
attempts to link such code with code assembled for other
processors.
'.v850e'
Specifies that the assembled code should be marked as being
targeted at the V850E processor. This allows the linker to detect
attempts to link such code with code assembled for other
processors.
'.v850e1'
Specifies that the assembled code should be marked as being
targeted at the V850E1 processor. This allows the linker to detect
attempts to link such code with code assembled for other
processors.
'.v850e2'
Specifies that the assembled code should be marked as being
targeted at the V850E2 processor. This allows the linker to detect
attempts to link such code with code assembled for other
processors.
'.v850e2v3'
Specifies that the assembled code should be marked as being
targeted at the V850E2V3 processor. This allows the linker to
detect attempts to link such code with code assembled for other
processors.
'.v850e2v4'
Specifies that the assembled code should be marked as being
targeted at the V850E3V5 processor. This allows the linker to
detect attempts to link such code with code assembled for other
processors.
'.v850e3v5'
Specifies that the assembled code should be marked as being
targeted at the V850E3V5 processor. This allows the linker to
detect attempts to link such code with code assembled for other
processors.

File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent
9.50.5 Opcodes
--------------
'as' implements all the standard V850 opcodes.
'as' also implements the following pseudo ops:
'hi0()'
Computes the higher 16 bits of the given expression and stores it
into the immediate operand field of the given instruction. For
example:
'mulhi hi0(here - there), r5, r6'
computes the difference between the address of labels 'here' and
'there', takes the upper 16 bits of this difference, shifts it down
16 bits and then multiplies it by the lower 16 bits in register 5,
putting the result into register 6.
'lo()'
Computes the lower 16 bits of the given expression and stores it
into the immediate operand field of the given instruction. For
example:
'addi lo(here - there), r5, r6'
computes the difference between the address of labels 'here' and
'there', takes the lower 16 bits of this difference and adds it to
register 5, putting the result into register 6.
'hi()'
Computes the higher 16 bits of the given expression and then adds
the value of the most significant bit of the lower 16 bits of the
expression and stores the result into the immediate operand field
of the given instruction. For example the following code can be
used to compute the address of the label 'here' and store it into
register 6:
'movhi hi(here), r0, r6' 'movea lo(here), r6, r6'
The reason for this special behaviour is that movea performs a sign
extension on its immediate operand. So for example if the address
of 'here' was 0xFFFFFFFF then without the special behaviour of the
hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6,
then the movea instruction would takes its immediate operand,
0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into
r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). With
the hi() pseudo op adding in the top bit of the lo() pseudo op, the
movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 0x0000),
so that the movea instruction stores 0xFFFFFFFF into r6 - the right
value.
'hilo()'
Computes the 32 bit value of the given expression and stores it
into the immediate operand field of the given instruction (which
must be a mov instruction). For example:
'mov hilo(here), r6'
computes the absolute address of label 'here' and puts the result
into register 6.
'sdaoff()'
Computes the offset of the named variable from the start of the
Small Data Area (whoes address is held in register 4, the GP
register) and stores the result as a 16 bit signed value in the
immediate operand field of the given instruction. For example:
'ld.w sdaoff(_a_variable)[gp],r6'
loads the contents of the location pointed to by the label
'_a_variable' into register 6, provided that the label is located
somewhere within +/- 32K of the address held in the GP register.
[Note the linker assumes that the GP register contains a fixed
address set to the address of the label called '__gp'. This can
either be set up automatically by the linker, or specifically set
by using the '--defsym __gp=<value>' command line option].
'tdaoff()'
Computes the offset of the named variable from the start of the
Tiny Data Area (whoes address is held in register 30, the EP
register) and stores the result as a 4,5, 7 or 8 bit unsigned value
in the immediate operand field of the given instruction. For
example:
'sld.w tdaoff(_a_variable)[ep],r6'
loads the contents of the location pointed to by the label
'_a_variable' into register 6, provided that the label is located
somewhere within +256 bytes of the address held in the EP register.
[Note the linker assumes that the EP register contains a fixed
address set to the address of the label called '__ep'. This can
either be set up automatically by the linker, or specifically set
by using the '--defsym __ep=<value>' command line option].
'zdaoff()'
Computes the offset of the named variable from address 0 and stores
the result as a 16 bit signed value in the immediate operand field
of the given instruction. For example:
'movea zdaoff(_a_variable),zero,r6'
puts the address of the label '_a_variable' into register 6,
assuming that the label is somewhere within the first 32K of
memory. (Strictly speaking it also possible to access the last 32K
of memory as well, as the offsets are signed).
'ctoff()'
Computes the offset of the named variable from the start of the
Call Table Area (whoes address is helg in system register 20, the
CTBP register) and stores the result a 6 or 16 bit unsigned value
in the immediate field of then given instruction or piece of data.
For example:
'callt ctoff(table_func1)'
will put the call the function whoes address is held in the call
table at the location labeled 'table_func1'.
'.longcall name'
Indicates that the following sequence of instructions is a long
call to function 'name'. The linker will attempt to shorten this
call sequence if 'name' is within a 22bit offset of the call. Only
valid if the '-mrelax' command line switch has been enabled.
'.longjump name'
Indicates that the following sequence of instructions is a long
jump to label 'name'. The linker will attempt to shorten this code
sequence if 'name' is within a 22bit offset of the jump. Only
valid if the '-mrelax' command line switch has been enabled.
For information on the V850 instruction set, see 'V850 Family
32-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC.
Ltd.

File: as.info, Node: XGATE-Dependent, Next: XSTORMY16-Dependent, Prev: V850-Dependent, Up: Machine Dependencies
9.51 XGATE Dependent Features
=============================
* Menu:
* XGATE-Opts:: XGATE Options
* XGATE-Syntax:: Syntax
* XGATE-Directives:: Assembler Directives
* XGATE-Float:: Floating Point
* XGATE-opcodes:: Opcodes

File: as.info, Node: XGATE-Opts, Next: XGATE-Syntax, Up: XGATE-Dependent
9.51.1 XGATE Options
--------------------
The Freescale XGATE version of 'as' has a few machine dependent options.
'-mshort'
This option controls the ABI and indicates to use a 16-bit integer
ABI. It has no effect on the assembled instructions. This is the
default.
'-mlong'
This option controls the ABI and indicates to use a 32-bit integer
ABI.
'-mshort-double'
This option controls the ABI and indicates to use a 32-bit float
ABI. This is the default.
'-mlong-double'
This option controls the ABI and indicates to use a 64-bit float
ABI.
'--print-insn-syntax'
You can use the '--print-insn-syntax' option to obtain the syntax
description of the instruction when an error is detected.
'--print-opcodes'
The '--print-opcodes' option prints the list of all the
instructions with their syntax. Once the list is printed 'as'
exits.

File: as.info, Node: XGATE-Syntax, Next: XGATE-Directives, Prev: XGATE-Opts, Up: XGATE-Dependent
9.51.2 Syntax
-------------
In XGATE RISC syntax, the instruction name comes first and it may be
followed by up to three operands. Operands are separated by commas
(','). 'as' will complain if too many operands are specified for a
given instruction. The same will happen if you specified too few
operands.
nop
ldl #23
CMP R1, R2
The presence of a ';' character or a '!' character anywhere on a line
indicates the start of a comment that extends to the end of that line.
A '*' or a '#' character at the start of a line also introduces a
line comment, but these characters do not work elsewhere on the line.
If the first character of the line is a '#' then as well as starting a
comment, the line could also be logical line number directive (*note
Comments::) or a preprocessor control command (*note Preprocessing::).
The XGATE assembler does not currently support a line separator
character.
The following addressing modes are understood for XGATE:
"Inherent"
''
"Immediate 3 Bit Wide"
'#NUMBER'
"Immediate 4 Bit Wide"
'#NUMBER'
"Immediate 8 Bit Wide"
'#NUMBER'
"Monadic Addressing"
'REG'
"Dyadic Addressing"
'REG, REG'
"Triadic Addressing"
'REG, REG, REG'
"Relative Addressing 9 Bit Wide"
'*SYMBOL'
"Relative Addressing 10 Bit Wide"
'*SYMBOL'
"Index Register plus Immediate Offset"
'REG, (REG, #NUMBER)'
"Index Register plus Register Offset"
'REG, REG, REG'
"Index Register plus Register Offset with Post-increment"
'REG, REG, REG+'
"Index Register plus Register Offset with Pre-decrement"
'REG, REG, -REG'
The register can be either 'R0', 'R1', 'R2', 'R3', 'R4', 'R5', 'R6'
or 'R7'.
Convience macro opcodes to deal with 16-bit values have been added.
"Immediate 16 Bit Wide"
'#NUMBER', or '*SYMBOL'
For example:
ldw R1, #1024
ldw R3, timer
ldw R1, (R1, #0)
COM R1
stw R2, (R1, #0)

File: as.info, Node: XGATE-Directives, Next: XGATE-Float, Prev: XGATE-Syntax, Up: XGATE-Dependent
9.51.3 Assembler Directives
---------------------------
The XGATE version of 'as' have the following specific assembler
directives:

File: as.info, Node: XGATE-Float, Next: XGATE-opcodes, Prev: XGATE-Directives, Up: XGATE-Dependent
9.51.4 Floating Point
---------------------
Packed decimal (P) format floating literals are not supported(yet).
The floating point formats generated by directives are these.
'.float'
'Single' precision floating point constants.
'.double'
'Double' precision floating point constants.
'.extend'
'.ldouble'
'Extended' precision ('long double') floating point constants.

File: as.info, Node: XGATE-opcodes, Prev: XGATE-Float, Up: XGATE-Dependent
9.51.5 Opcodes
--------------

File: as.info, Node: XSTORMY16-Dependent, Next: Xtensa-Dependent, Prev: XGATE-Dependent, Up: Machine Dependencies
9.52 XStormy16 Dependent Features
=================================
* Menu:
* XStormy16 Syntax:: Syntax
* XStormy16 Directives:: Machine Directives
* XStormy16 Opcodes:: Pseudo-Opcodes

File: as.info, Node: XStormy16 Syntax, Next: XStormy16 Directives, Up: XSTORMY16-Dependent
9.52.1 Syntax
-------------
* Menu:
* XStormy16-Chars:: Special Characters

File: as.info, Node: XStormy16-Chars, Up: XStormy16 Syntax
9.52.1.1 Special Characters
...........................
'#' is the line comment character. If a '#' appears as the first
character of a line, the whole line is treated as a comment, but in this
case the line can also be a logical line number directive (*note
Comments::) or a preprocessor control command (*note Preprocessing::).
A semicolon (';') can be used to start a comment that extends from
wherever the character appears on the line up to the end of the line.
The '|' character can be used to separate statements on the same
line.

File: as.info, Node: XStormy16 Directives, Next: XStormy16 Opcodes, Prev: XStormy16 Syntax, Up: XSTORMY16-Dependent
9.52.2 XStormy16 Machine Directives
-----------------------------------
'.16bit_pointers'
Like the '--16bit-pointers' command line option this directive
indicates that the assembly code makes use of 16-bit pointers.
'.32bit_pointers'
Like the '--32bit-pointers' command line option this directive
indicates that the assembly code makes use of 32-bit pointers.
'.no_pointers'
Like the '--no-pointers' command line option this directive
indicates that the assembly code does not makes use pointers.

File: as.info, Node: XStormy16 Opcodes, Prev: XStormy16 Directives, Up: XSTORMY16-Dependent
9.52.3 XStormy16 Pseudo-Opcodes
-------------------------------
'as' implements all the standard XStormy16 opcodes.
'as' also implements the following pseudo ops:
'@lo()'
Computes the lower 16 bits of the given expression and stores it
into the immediate operand field of the given instruction. For
example:
'add r6, @lo(here - there)'
computes the difference between the address of labels 'here' and
'there', takes the lower 16 bits of this difference and adds it to
register 6.
'@hi()'
Computes the higher 16 bits of the given expression and stores it
into the immediate operand field of the given instruction. For
example:
'addc r7, @hi(here - there)'
computes the difference between the address of labels 'here' and
'there', takes the upper 16 bits of this difference, shifts it down
16 bits and then adds it, along with the carry bit, to the value in
register 7.

File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: XSTORMY16-Dependent, Up: Machine Dependencies
9.53 Xtensa Dependent Features
==============================
This chapter covers features of the GNU assembler that are specific to
the Xtensa architecture. For details about the Xtensa instruction set,
please consult the 'Xtensa Instruction Set Architecture (ISA) Reference
Manual'.
* Menu:
* Xtensa Options:: Command-line Options.
* Xtensa Syntax:: Assembler Syntax for Xtensa Processors.
* Xtensa Optimizations:: Assembler Optimizations.
* Xtensa Relaxation:: Other Automatic Transformations.
* Xtensa Directives:: Directives for Xtensa Processors.

File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent
9.53.1 Command Line Options
---------------------------
'--text-section-literals | --no-text-section-literals'
Control the treatment of literal pools. The default is
'--no-text-section-literals', which places literals in separate
sections in the output file. This allows the literal pool to be
placed in a data RAM/ROM. With '--text-section-literals', the
literals are interspersed in the text section in order to keep them
as close as possible to their references. This may be necessary
for large assembly files, where the literals would otherwise be out
of range of the 'L32R' instructions in the text section. These
options only affect literals referenced via PC-relative 'L32R'
instructions; literals for absolute mode 'L32R' instructions are
handled separately. *Note literal: Literal Directive.
'--absolute-literals | --no-absolute-literals'
Indicate to the assembler whether 'L32R' instructions use absolute
or PC-relative addressing. If the processor includes the absolute
addressing option, the default is to use absolute 'L32R'
relocations. Otherwise, only the PC-relative 'L32R' relocations
can be used.
'--target-align | --no-target-align'
Enable or disable automatic alignment to reduce branch penalties at
some expense in code size. *Note Automatic Instruction Alignment:
Xtensa Automatic Alignment. This optimization is enabled by
default. Note that the assembler will always align instructions
like 'LOOP' that have fixed alignment requirements.
'--longcalls | --no-longcalls'
Enable or disable transformation of call instructions to allow
calls across a greater range of addresses. *Note Function Call
Relaxation: Xtensa Call Relaxation. This option should be used
when call targets can potentially be out of range. It may degrade
both code size and performance, but the linker can generally
optimize away the unnecessary overhead when a call ends up within
range. The default is '--no-longcalls'.
'--transform | --no-transform'
Enable or disable all assembler transformations of Xtensa
instructions, including both relaxation and optimization. The
default is '--transform'; '--no-transform' should only be used in
the rare cases when the instructions must be exactly as specified
in the assembly source. Using '--no-transform' causes out of range
instruction operands to be errors.
'--rename-section OLDNAME=NEWNAME'
Rename the OLDNAME section to NEWNAME. This option can be used
multiple times to rename multiple sections.
'--trampolines | --no-trampolines'
Enable or disable transformation of jump instructions to allow
jumps across a greater range of addresses. *Note Jump Trampolines:
Xtensa Jump Relaxation. This option should be used when jump
targets can potentially be out of range. In the absence of such
jumps this option does not affect code size or performance. The
default is '--trampolines'.

File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent
9.53.2 Assembler Syntax
-----------------------
Block comments are delimited by '/*' and '*/'. End of line comments may
be introduced with either '#' or '//'.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line could also be a
logical line number directive (*note Comments::) or a preprocessor
control command (*note Preprocessing::).
Instructions consist of a leading opcode or macro name followed by
whitespace and an optional comma-separated list of operands:
OPCODE [OPERAND, ...]
Instructions must be separated by a newline or semicolon (';').
FLIX instructions, which bundle multiple opcodes together in a single
instruction, are specified by enclosing the bundled opcodes inside
braces:
{
[FORMAT]
OPCODE0 [OPERANDS]
OPCODE1 [OPERANDS]
OPCODE2 [OPERANDS]
...
}
The opcodes in a FLIX instruction are listed in the same order as the
corresponding instruction slots in the TIE format declaration.
Directives and labels are not allowed inside the braces of a FLIX
instruction. A particular TIE format name can optionally be specified
immediately after the opening brace, but this is usually unnecessary.
The assembler will automatically search for a format that can encode the
specified opcodes, so the format name need only be specified in rare
cases where there is more than one applicable format and where it
matters which of those formats is used. A FLIX instruction can also be
specified on a single line by separating the opcodes with semicolons:
{ [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... }
If an opcode can only be encoded in a FLIX instruction but is not
specified as part of a FLIX bundle, the assembler will choose the
smallest format where the opcode can be encoded and will fill unused
instruction slots with no-ops.
* Menu:
* Xtensa Opcodes:: Opcode Naming Conventions.
* Xtensa Registers:: Register Naming.

File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax
9.53.2.1 Opcode Names
.....................
See the 'Xtensa Instruction Set Architecture (ISA) Reference Manual' for
a complete list of opcodes and descriptions of their semantics.
If an opcode name is prefixed with an underscore character ('_'),
'as' will not transform that instruction in any way. The underscore
prefix disables both optimization (*note Xtensa Optimizations: Xtensa
Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa
Relaxation.) for that particular instruction. Only use the underscore
prefix when it is essential to select the exact opcode produced by the
assembler. Using this feature unnecessarily makes the code less
efficient by disabling assembler optimization and less flexible by
disabling relaxation.
Note that this special handling of underscore prefixes only applies
to Xtensa opcodes, not to either built-in macros or user-defined macros.
When an underscore prefix is used with a macro (e.g., '_MOV'), it refers
to a different macro. The assembler generally provides built-in macros
both with and without the underscore prefix, where the underscore
versions behave as if the underscore carries through to the instructions
in the macros. For example, '_MOV' may expand to '_MOV.N'.
The underscore prefix only applies to individual instructions, not to
series of instructions. For example, if a series of instructions have
underscore prefixes, the assembler will not transform the individual
instructions, but it may insert other instructions between them (e.g.,
to align a 'LOOP' instruction). To prevent the assembler from modifying
a series of instructions as a whole, use the 'no-transform' directive.
*Note transform: Transform Directive.

File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax
9.53.2.2 Register Names
.......................
The assembly syntax for a register file entry is the "short" name for a
TIE register file followed by the index into that register file. For
example, the general-purpose 'AR' register file has a short name of 'a',
so these registers are named 'a0'...'a15'. As a special feature, 'sp'
is also supported as a synonym for 'a1'. Additional registers may be
added by processor configuration options and by designer-defined TIE
extensions. An initial '$' character is optional in all register names.

File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent
9.53.3 Xtensa Optimizations
---------------------------
The optimizations currently supported by 'as' are generation of density
instructions where appropriate and automatic branch target alignment.
* Menu:
* Density Instructions:: Using Density Instructions.
* Xtensa Automatic Alignment:: Automatic Instruction Alignment.

File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations
9.53.3.1 Using Density Instructions
...................................
The Xtensa instruction set has a code density option that provides
16-bit versions of some of the most commonly used opcodes. Use of these
opcodes can significantly reduce code size. When possible, the
assembler automatically translates instructions from the core Xtensa
instruction set into equivalent instructions from the Xtensa code
density option. This translation can be disabled by using underscore
prefixes (*note Opcode Names: Xtensa Opcodes.), by using the
'--no-transform' command-line option (*note Command Line Options: Xtensa
Options.), or by using the 'no-transform' directive (*note transform:
Transform Directive.).
It is a good idea _not_ to use the density instructions directly.
The assembler will automatically select dense instructions where
possible. If you later need to use an Xtensa processor without the code
density option, the same assembly code will then work without
modification.

File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations
9.53.3.2 Automatic Instruction Alignment
........................................
The Xtensa assembler will automatically align certain instructions, both
to optimize performance and to satisfy architectural requirements.
As an optimization to improve performance, the assembler attempts to
align branch targets so they do not cross instruction fetch boundaries.
(Xtensa processors can be configured with either 32-bit or 64-bit
instruction fetch widths.) An instruction immediately following a call
is treated as a branch target in this context, because it will be the
target of a return from the call. This alignment has the potential to
reduce branch penalties at some expense in code size. This optimization
is enabled by default. You can disable it with the '--no-target-align'
command-line option (*note Command Line Options: Xtensa Options.).
The target alignment optimization is done without adding instructions
that could increase the execution time of the program. If there are
density instructions in the code preceding a target, the assembler can
change the target alignment by widening some of those instructions to
the equivalent 24-bit instructions. Extra bytes of padding can be
inserted immediately following unconditional jump and return
instructions. This approach is usually successful in aligning many, but
not all, branch targets.
The 'LOOP' family of instructions must be aligned such that the first
instruction in the loop body does not cross an instruction fetch
boundary (e.g., with a 32-bit fetch width, a 'LOOP' instruction must be
on either a 1 or 2 mod 4 byte boundary). The assembler knows about this
restriction and inserts the minimal number of 2 or 3 byte no-op
instructions to satisfy it. When no-op instructions are added, any
label immediately preceding the original loop will be moved in order to
refer to the loop instruction, not the newly generated no-op
instruction. To preserve binary compatibility across processors with
different fetch widths, the assembler conservatively assumes a 32-bit
fetch width when aligning 'LOOP' instructions (except if the first
instruction in the loop is a 64-bit instruction).
Previous versions of the assembler automatically aligned 'ENTRY'
instructions to 4-byte boundaries, but that alignment is now the
programmer's responsibility.

File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent
9.53.4 Xtensa Relaxation
------------------------
When an instruction operand is outside the range allowed for that
particular instruction field, 'as' can transform the code to use a
functionally-equivalent instruction or sequence of instructions. This
process is known as "relaxation". This is typically done for branch
instructions because the distance of the branch targets is not known
until assembly-time. The Xtensa assembler offers branch relaxation and
also extends this concept to function calls, 'MOVI' instructions and
other instructions with immediate fields.
* Menu:
* Xtensa Branch Relaxation:: Relaxation of Branches.
* Xtensa Call Relaxation:: Relaxation of Function Calls.
* Xtensa Jump Relaxation:: Relaxation of Jumps.
* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields.

File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation
9.53.4.1 Conditional Branch Relaxation
......................................
When the target of a branch is too far away from the branch itself,
i.e., when the offset from the branch to the target is too large to fit
in the immediate field of the branch instruction, it may be necessary to
replace the branch with a branch around a jump. For example,
beqz a2, L
may result in:
bnez.n a2, M
j L
M:
(The 'BNEZ.N' instruction would be used in this example only if the
density option is available. Otherwise, 'BNEZ' would be used.)
This relaxation works well because the unconditional jump instruction
has a much larger offset range than the various conditional branches.
However, an error will occur if a branch target is beyond the range of a
jump instruction. 'as' cannot relax unconditional jumps. Similarly, an
error will occur if the original input contains an unconditional jump to
a target that is out of range.
Branch relaxation is enabled by default. It can be disabled by using
underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the
'--no-transform' command-line option (*note Command Line Options: Xtensa
Options.), or the 'no-transform' directive (*note transform: Transform
Directive.).

File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Jump Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation
9.53.4.2 Function Call Relaxation
.................................
Function calls may require relaxation because the Xtensa immediate call
instructions ('CALL0', 'CALL4', 'CALL8' and 'CALL12') provide a
PC-relative offset of only 512 Kbytes in either direction. For larger
programs, it may be necessary to use indirect calls ('CALLX0', 'CALLX4',
'CALLX8' and 'CALLX12') where the target address is specified in a
register. The Xtensa assembler can automatically relax immediate call
instructions into indirect call instructions. This relaxation is done
by loading the address of the called function into the callee's return
address register and then using a 'CALLX' instruction. So, for example:
call8 func
might be relaxed to:
.literal .L1, func
l32r a8, .L1
callx8 a8
Because the addresses of targets of function calls are not generally
known until link-time, the assembler must assume the worst and relax all
the calls to functions in other source files, not just those that really
will be out of range. The linker can recognize calls that were
unnecessarily relaxed, and it will remove the overhead introduced by the
assembler for those cases where direct calls are sufficient.
Call relaxation is disabled by default because it can have a negative
effect on both code size and performance, although the linker can
usually eliminate the unnecessary overhead. If a program is too large
and some of the calls are out of range, function call relaxation can be
enabled using the '--longcalls' command-line option or the 'longcalls'
directive (*note longcalls: Longcalls Directive.).

File: as.info, Node: Xtensa Jump Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation
9.53.4.3 Jump Relaxation
........................
Jump instruction may require relaxation because the Xtensa jump
instruction ('J') provide a PC-relative offset of only 128 Kbytes in
either direction. One option is to use jump long ('J.L') instruction,
which depending on jump distance may be assembled as jump ('J') or
indirect jump ('JX'). However it needs a free register. When there's
no spare register it is possible to plant intermediate jump sites
(trampolines) between the jump instruction and its target. These sites
may be located in areas unreachable by normal code execution flow, in
that case they only contain intermediate jumps, or they may be inserted
in the middle of code block, in which case there's an additional jump
from the beginning of the trampoline to the instruction past its end.
So, for example:
j 1f
...
retw
...
mov a10, a2
call8 func
...
1:
...
might be relaxed to:
j .L0_TR_1
...
retw
.L0_TR_1:
j 1f
...
mov a10, a2
call8 func
...
1:
...
or to:
j .L0_TR_1
...
retw
...
mov a10, a2
j .L0_TR_0
.L0_TR_1:
j 1f
.L0_TR_0:
call8 func
...
1:
...
The Xtensa assempler uses trampolines with jump around only when it
cannot find suitable unreachable trampoline. There may be multiple
trampolines between the jump instruction and its target.
This relaxation does not apply to jumps to undefined symbols,
assuming they will reach their targets once resolved.
Jump relaxation is enabled by default because it does not affect code
size or performance while the code itself is small. This relaxation may
be disabled completely with '--no-trampolines' or '--no-transform'
command-line options (*note Command Line Options: Xtensa Options.).

File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Jump Relaxation, Up: Xtensa Relaxation
9.53.4.4 Other Immediate Field Relaxation
.........................................
The assembler normally performs the following other relaxations. They
can be disabled by using underscore prefixes (*note Opcode Names: Xtensa
Opcodes.), the '--no-transform' command-line option (*note Command Line
Options: Xtensa Options.), or the 'no-transform' directive (*note
transform: Transform Directive.).
The 'MOVI' machine instruction can only materialize values in the
range from -2048 to 2047. Values outside this range are best
materialized with 'L32R' instructions. Thus:
movi a0, 100000
is assembled into the following machine code:
.literal .L1, 100000
l32r a0, .L1
The 'L8UI' machine instruction can only be used with immediate
offsets in the range from 0 to 255. The 'L16SI' and 'L16UI' machine
instructions can only be used with offsets from 0 to 510. The 'L32I'
machine instruction can only be used with offsets from 0 to 1020. A
load offset outside these ranges can be materialized with an 'L32R'
instruction if the destination register of the load is different than
the source address register. For example:
l32i a1, a0, 2040
is translated to:
.literal .L1, 2040
l32r a1, .L1
add a1, a0, a1
l32i a1, a1, 0
If the load destination and source address register are the same, an
out-of-range offset causes an error.
The Xtensa 'ADDI' instruction only allows immediate operands in the
range from -128 to 127. There are a number of alternate instruction
sequences for the 'ADDI' operation. First, if the immediate is 0, the
'ADDI' will be turned into a 'MOV.N' instruction (or the equivalent 'OR'
instruction if the code density option is not available). If the 'ADDI'
immediate is outside of the range -128 to 127, but inside the range
-32896 to 32639, an 'ADDMI' instruction or 'ADDMI'/'ADDI' sequence will
be used. Finally, if the immediate is outside of this range and a free
register is available, an 'L32R'/'ADD' sequence will be used with a
literal allocated from the literal pool.
For example:
addi a5, a6, 0
addi a5, a6, 512
addi a5, a6, 513
addi a5, a6, 50000
is assembled into the following:
.literal .L1, 50000
mov.n a5, a6
addmi a5, a6, 0x200
addmi a5, a6, 0x200
addi a5, a5, 1
l32r a5, .L1
add a5, a6, a5

File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent
9.53.5 Directives
-----------------
The Xtensa assembler supports a region-based directive syntax:
.begin DIRECTIVE [OPTIONS]
...
.end DIRECTIVE
All the Xtensa-specific directives that apply to a region of code use
this syntax.
The directive applies to code between the '.begin' and the '.end'.
The state of the option after the '.end' reverts to what it was before
the '.begin'. A nested '.begin'/'.end' region can further change the
state of the directive without having to be aware of its outer state.
For example, consider:
.begin no-transform
L: add a0, a1, a2
.begin transform
M: add a0, a1, a2
.end transform
N: add a0, a1, a2
.end no-transform
The 'ADD' opcodes at 'L' and 'N' in the outer 'no-transform' region
both result in 'ADD' machine instructions, but the assembler selects an
'ADD.N' instruction for the 'ADD' at 'M' in the inner 'transform'
region.
The advantage of this style is that it works well inside macros which
can preserve the context of their callers.
The following directives are available:
* Menu:
* Schedule Directive:: Enable instruction scheduling.
* Longcalls Directive:: Use Indirect Calls for Greater Range.
* Transform Directive:: Disable All Assembler Transformations.
* Literal Directive:: Intermix Literals with Instructions.
* Literal Position Directive:: Specify Inline Literal Pool Locations.
* Literal Prefix Directive:: Specify Literal Section Name Prefix.
* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals.

File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives
9.53.5.1 schedule
.................
The 'schedule' directive is recognized only for compatibility with
Tensilica's assembler.
.begin [no-]schedule
.end [no-]schedule
This directive is ignored and has no effect on 'as'.

File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives
9.53.5.2 longcalls
..................
The 'longcalls' directive enables or disables function call relaxation.
*Note Function Call Relaxation: Xtensa Call Relaxation.
.begin [no-]longcalls
.end [no-]longcalls
Call relaxation is disabled by default unless the '--longcalls'
command-line option is specified. The 'longcalls' directive overrides
the default determined by the command-line options.

File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives
9.53.5.3 transform
..................
This directive enables or disables all assembler transformation,
including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and
optimization (*note Xtensa Optimizations: Xtensa Optimizations.).
.begin [no-]transform
.end [no-]transform
Transformations are enabled by default unless the '--no-transform'
option is used. The 'transform' directive overrides the default
determined by the command-line options. An underscore opcode prefix,
disabling transformation of that opcode, always takes precedence over
both directives and command-line flags.

File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives
9.53.5.4 literal
................
The '.literal' directive is used to define literal pool data, i.e.,
read-only 32-bit data accessed via 'L32R' instructions.
.literal LABEL, VALUE[, VALUE...]
This directive is similar to the standard '.word' directive, except
that the actual location of the literal data is determined by the
assembler and linker, not by the position of the '.literal' directive.
Using this directive gives the assembler freedom to locate the literal
data in the most appropriate place and possibly to combine identical
literals. For example, the code:
entry sp, 40
.literal .L1, sym
l32r a4, .L1
can be used to load a pointer to the symbol 'sym' into register 'a4'.
The value of 'sym' will not be placed between the 'ENTRY' and 'L32R'
instructions; instead, the assembler puts the data in a literal pool.
Literal pools are placed by default in separate literal sections;
however, when using the '--text-section-literals' option (*note Command
Line Options: Xtensa Options.), the literal pools for PC-relative mode
'L32R' instructions are placed in the current section.(1) These text
section literal pools are created automatically before 'ENTRY'
instructions and manually after '.literal_position' directives (*note
literal_position: Literal Position Directive.). If there are no
preceding 'ENTRY' instructions, explicit '.literal_position' directives
must be used to place the text section literal pools; otherwise, 'as'
will report an error.
When literals are placed in separate sections, the literal section
names are derived from the names of the sections where the literals are
defined. The base literal section names are '.literal' for PC-relative
mode 'L32R' instructions and '.lit4' for absolute mode 'L32R'
instructions (*note absolute-literals: Absolute Literals Directive.).
These base names are used for literals defined in the default '.text'
section. For literals defined in other sections or within the scope of
a 'literal_prefix' directive (*note literal_prefix: Literal Prefix
Directive.), the following rules determine the literal section name:
1. If the current section is a member of a section group, the literal
section name includes the group name as a suffix to the base
'.literal' or '.lit4' name, with a period to separate the base name
and group name. The literal section is also made a member of the
group.
2. If the current section name (or 'literal_prefix' value) begins with
"'.gnu.linkonce.KIND.'", the literal section name is formed by
replacing "'.KIND'" with the base '.literal' or '.lit4' name. For
example, for literals defined in a section named
'.gnu.linkonce.t.func', the literal section will be
'.gnu.linkonce.literal.func' or '.gnu.linkonce.lit4.func'.
3. If the current section name (or 'literal_prefix' value) ends with
'.text', the literal section name is formed by replacing that
suffix with the base '.literal' or '.lit4' name. For example, for
literals defined in a section named '.iram0.text', the literal
section will be '.iram0.literal' or '.iram0.lit4'.
4. If none of the preceding conditions apply, the literal section name
is formed by adding the base '.literal' or '.lit4' name as a suffix
to the current section name (or 'literal_prefix' value).
---------- Footnotes ----------
(1) Literals for the '.init' and '.fini' sections are always placed
in separate sections, even when '--text-section-literals' is enabled.

File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives
9.53.5.5 literal_position
.........................
When using '--text-section-literals' to place literals inline in the
section being assembled, the '.literal_position' directive can be used
to mark a potential location for a literal pool.
.literal_position
The '.literal_position' directive is ignored when the
'--text-section-literals' option is not used or when 'L32R' instructions
use the absolute addressing mode.
The assembler will automatically place text section literal pools
before 'ENTRY' instructions, so the '.literal_position' directive is
only needed to specify some other location for a literal pool. You may
need to add an explicit jump instruction to skip over an inline literal
pool.
For example, an interrupt vector does not begin with an 'ENTRY'
instruction so the assembler will be unable to automatically find a good
place to put a literal pool. Moreover, the code for the interrupt
vector must be at a specific starting address, so the literal pool
cannot come before the start of the code. The literal pool for the
vector must be explicitly positioned in the middle of the vector (before
any uses of the literals, due to the negative offsets used by
PC-relative 'L32R' instructions). The '.literal_position' directive can
be used to do this. In the following code, the literal for 'M' will
automatically be aligned correctly and is placed after the unconditional
jump.
.global M
code_start:
j continue
.literal_position
.align 4
continue:
movi a4, M

File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives
9.53.5.6 literal_prefix
.......................
The 'literal_prefix' directive allows you to override the default
literal section names, which are derived from the names of the sections
where the literals are defined.
.begin literal_prefix [NAME]
.end literal_prefix
For literals defined within the delimited region, the literal section
names are derived from the NAME argument instead of the name of the
current section. The rules used to derive the literal section names do
not change. *Note literal: Literal Directive. If the NAME argument is
omitted, the literal sections revert to the defaults. This directive
has no effect when using the '--text-section-literals' option (*note
Command Line Options: Xtensa Options.).

File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives
9.53.5.7 absolute-literals
..........................
The 'absolute-literals' and 'no-absolute-literals' directives control
the absolute vs. PC-relative mode for 'L32R' instructions. These are
relevant only for Xtensa configurations that include the absolute
addressing option for 'L32R' instructions.
.begin [no-]absolute-literals
.end [no-]absolute-literals
These directives do not change the 'L32R' mode--they only cause the
assembler to emit the appropriate kind of relocation for 'L32R'
instructions and to place the literal values in the appropriate section.
To change the 'L32R' mode, the program must write the 'LITBASE' special
register. It is the programmer's responsibility to keep track of the
mode and indicate to the assembler which mode is used in each region of
code.
If the Xtensa configuration includes the absolute 'L32R' addressing
option, the default is to assume absolute 'L32R' addressing unless the
'--no-absolute-literals' command-line option is specified. Otherwise,
the default is to assume PC-relative 'L32R' addressing. The
'absolute-literals' directive can then be used to override the default
determined by the command-line options.

File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top
10 Reporting Bugs
*****************
Your bug reports play an essential role in making 'as' reliable.
Reporting a bug may help you by bringing a solution to your problem,
or it may not. But in any case the principal function of a bug report
is to help the entire community by making the next version of 'as' work
better. Bug reports are your contribution to the maintenance of 'as'.
In order for a bug report to serve its purpose, you must include the
information that enables us to fix the bug.
* Menu:
* Bug Criteria:: Have you found a bug?
* Bug Reporting:: How to report bugs

File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs
10.1 Have You Found a Bug?
==========================
If you are not sure whether you have found a bug, here are some
guidelines:
* If the assembler gets a fatal signal, for any input whatever, that
is a 'as' bug. Reliable assemblers never crash.
* If 'as' produces an error message for valid input, that is a bug.
* If 'as' does not produce an error message for invalid input, that
is a bug. However, you should note that your idea of "invalid
input" might be our idea of "an extension" or "support for
traditional practice".
* If you are an experienced user of assemblers, your suggestions for
improvement of 'as' are welcome in any case.

File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs
10.2 How to Report Bugs
=======================
A number of companies and individuals offer support for GNU products.
If you obtained 'as' from a support organization, we recommend you
contact that organization first.
You can find contact information for many support companies and
individuals in the file 'etc/SERVICE' in the GNU Emacs distribution.
In any event, we also recommend that you send bug reports for 'as' to
<http://www.sourceware.org/bugzilla/>.
The fundamental principle of reporting bugs usefully is this: *report
all the facts*. If you are not sure whether to state a fact or leave it
out, state it!
Often people omit facts because they think they know what causes the
problem and assume that some details do not matter. Thus, you might
assume that the name of a symbol you use in an example does not matter.
Well, probably it does not, but one cannot be sure. Perhaps the bug is
a stray memory reference which happens to fetch from the location where
that name is stored in memory; perhaps, if the name were different, the
contents of that location would fool the assembler into doing the right
thing despite the bug. Play it safe and give a specific, complete
example. That is the easiest thing for you to do, and the most helpful.
Keep in mind that the purpose of a bug report is to enable us to fix
the bug if it is new to us. Therefore, always write your bug reports on
the assumption that the bug has not been reported previously.
Sometimes people give a few sketchy facts and ask, "Does this ring a
bell?" This cannot help us fix a bug, so it is basically useless. We
respond by asking for enough details to enable us to investigate. You
might as well expedite matters by sending them to begin with.
To enable us to fix the bug, you should include all these things:
* The version of 'as'. 'as' announces it if you start it with the
'--version' argument.
Without this, we will not know whether there is any point in
looking for the bug in the current version of 'as'.
* Any patches you may have applied to the 'as' source.
* The type of machine you are using, and the operating system name
and version number.
* What compiler (and its version) was used to compile 'as'--e.g.
"'gcc-2.7'".
* The command arguments you gave the assembler to assemble your
example and observe the bug. To guarantee you will not omit
something important, list them all. A copy of the Makefile (or the
output from make) is sufficient.
If we were to try to guess the arguments, we would probably guess
wrong and then we might not encounter the bug.
* A complete input file that will reproduce the bug. If the bug is
observed when the assembler is invoked via a compiler, send the
assembler source, not the high level language source. Most
compilers will produce the assembler source when run with the '-S'
option. If you are using 'gcc', use the options '-v --save-temps';
this will save the assembler source in a file with an extension of
'.s', and also show you exactly how 'as' is being run.
* A description of what behavior you observe that you believe is
incorrect. For example, "It gets a fatal signal."
Of course, if the bug is that 'as' gets a fatal signal, then we
will certainly notice it. But if the bug is incorrect output, we
might not notice unless it is glaringly wrong. You might as well
not give us a chance to make a mistake.
Even if the problem you experience is a fatal signal, you should
still say so explicitly. Suppose something strange is going on,
such as, your copy of 'as' is out of sync, or you have encountered
a bug in the C library on your system. (This has happened!) Your
copy might crash and ours would not. If you told us to expect a
crash, then when ours fails to crash, we would know that the bug
was not happening for us. If you had not told us to expect a
crash, then we would not be able to draw any conclusion from our
observations.
* If you wish to suggest changes to the 'as' source, send us context
diffs, as generated by 'diff' with the '-u', '-c', or '-p' option.
Always send diffs from the old file to the new file. If you even
discuss something in the 'as' source, refer to it by context, not
by line number.
The line numbers in our development sources will not match those in
your sources. Your line numbers would convey no useful information
to us.
Here are some things that are not necessary:
* A description of the envelope of the bug.
Often people who encounter a bug spend a lot of time investigating
which changes to the input file will make the bug go away and which
changes will not affect it.
This is often time consuming and not very useful, because the way
we will find the bug is by running a single example under the
debugger with breakpoints, not by pure deduction from a series of
examples. We recommend that you save your time for something else.
Of course, if you can find a simpler example to report _instead_ of
the original one, that is a convenience for us. Errors in the
output will be easier to spot, running under the debugger will take
less time, and so on.
However, simplification is not vital; if you do not want to do
this, report the bug anyway and send us the entire test case you
used.
* A patch for the bug.
A patch for the bug does help us if it is a good one. But do not
omit the necessary information, such as the test case, on the
assumption that a patch is all we need. We might see problems with
your patch and decide to fix the problem another way, or we might
not understand it at all.
Sometimes with a program as complicated as 'as' it is very hard to
construct an example that will make the program follow a certain
path through the code. If you do not send us the example, we will
not be able to construct one, so we will not be able to verify that
the bug is fixed.
And if we cannot understand what bug you are trying to fix, or why
your patch should be an improvement, we will not install it. A
test case will help us to understand.
* A guess about what the bug is or what it depends on.
Such guesses are usually wrong. Even we cannot guess right about
such things without first using the debugger to find the facts.

File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top
11 Acknowledgements
*******************
If you have contributed to GAS and your name isn't listed here, it is
not meant as a slight. We just don't know about it. Send mail to the
maintainer, and we'll correct the situation. Currently the maintainer
is Nick Clifton (email address 'nickc@redhat.com').
Dean Elsner wrote the original GNU assembler for the VAX.(1)
Jay Fenlason maintained GAS for a while, adding support for
GDB-specific debug information and the 68k series machines, most of the
preprocessing pass, and extensive changes in 'messages.c',
'input-file.c', 'write.c'.
K. Richard Pixley maintained GAS for a while, adding various
enhancements and many bug fixes, including merging support for several
processors, breaking GAS up to handle multiple object file format back
ends (including heavy rewrite, testing, an integration of the coff and
b.out back ends), adding configuration including heavy testing and
verification of cross assemblers and file splits and renaming, converted
GAS to strictly ANSI C including full prototypes, added support for
m680[34]0 and cpu32, did considerable work on i960 including a COFF port
(including considerable amounts of reverse engineering), a SPARC opcode
file rewrite, DECstation, rs6000, and hp300hpux host ports, updated
"know" assertions and made them work, much other reorganization,
cleanup, and lint.
Ken Raeburn wrote the high-level BFD interface code to replace most
of the code in format-specific I/O modules.
The original VMS support was contributed by David L. Kashtan. Eric
Youngdale has done much work with it since.
The Intel 80386 machine description was written by Eliot Dresselhaus.
Minh Tran-Le at IntelliCorp contributed some AIX 386 support.
The Motorola 88k machine description was contributed by Devon Bowen
of Buffalo University and Torbjorn Granlund of the Swedish Institute of
Computer Science.
Keith Knowles at the Open Software Foundation wrote the original MIPS
back end ('tc-mips.c', 'tc-mips.h'), and contributed Rose format support
(which hasn't been merged in yet). Ralph Campbell worked with the MIPS
code to support a.out format.
Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k,
tc-h8300), and IEEE 695 object file format (obj-ieee), was written by
Steve Chamberlain of Cygnus Support. Steve also modified the COFF back
end to use BFD for some low-level operations, for use with the H8/300
and AMD 29k targets.
John Gilmore built the AMD 29000 support, added '.include' support,
and simplified the configuration of which versions accept which
directives. He updated the 68k machine description so that Motorola's
opcodes always produced fixed-size instructions (e.g., 'jsr'), while
synthetic instructions remained shrinkable ('jbsr'). John fixed many
bugs, including true tested cross-compilation support, and one bug in
relaxation that took a week and required the proverbial one-bit fix.
Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax
for the 68k, completed support for some COFF targets (68k, i386 SVR3,
and SCO Unix), added support for MIPS ECOFF and ELF targets, wrote the
initial RS/6000 and PowerPC assembler, and made a few other minor
patches.
Steve Chamberlain made GAS able to generate listings.
Hewlett-Packard contributed support for the HP9000/300.
Jeff Law wrote GAS and BFD support for the native HPPA object format
(SOM) along with a fairly extensive HPPA testsuite (for both SOM and ELF
object formats). This work was supported by both the Center for
Software Science at the University of Utah and Cygnus Support.
Support for ELF format files has been worked on by Mark Eichin of
Cygnus Support (original, incomplete implementation for SPARC), Pete
Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael
Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn
of Cygnus Support (sparc, and some initial 64-bit support).
Linas Vepstas added GAS support for the ESA/390 "IBM 370"
architecture.
Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote
GAS and BFD support for openVMS/Alpha.
Timothy Wall, Michael Hayes, and Greg Smart contributed to the
various tic* flavors.
David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from
Tensilica, Inc. added support for Xtensa processors.
Several engineers at Cygnus Support have also provided many small bug
fixes and configuration enhancements.
Jon Beniston added support for the Lattice Mico32 architecture.
Many others have contributed large or small bugfixes and
enhancements. If you have contributed significant work and are not
mentioned on this list, and want to be, let us know. Some of the
history has been lost; we are not intentionally leaving anyone out.
---------- Footnotes ----------
(1) Any more details?

File: as.info, Node: GNU Free Documentation License, Next: AS Index, Prev: Acknowledgements, Up: Top
Appendix A GNU Free Documentation License
*****************************************
Version 1.3, 3 November 2008
Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc.
<http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
0. PREAMBLE
The purpose of this License is to make a manual, textbook, or other
functional and useful document "free" in the sense of freedom: to
assure everyone the effective freedom to copy and redistribute it,
with or without modifying it, either commercially or
noncommercially. Secondarily, this License preserves for the
author and publisher a way to get credit for their work, while not
being considered responsible for modifications made by others.
This License is a kind of "copyleft", which means that derivative
works of the document must themselves be free in the same sense.
It complements the GNU General Public License, which is a copyleft
license designed for free software.
We have designed this License in order to use it for manuals for
free software, because free software needs free documentation: a
free program should come with manuals providing the same freedoms
that the software does. But this License is not limited to
software manuals; it can be used for any textual work, regardless
of subject matter or whether it is published as a printed book. We
recommend this License principally for works whose purpose is
instruction or reference.
1. APPLICABILITY AND DEFINITIONS
This License applies to any manual or other work, in any medium,
that contains a notice placed by the copyright holder saying it can
be distributed under the terms of this License. Such a notice
grants a world-wide, royalty-free license, unlimited in duration,
to use that work under the conditions stated herein. The
"Document", below, refers to any such manual or work. Any member
of the public is a licensee, and is addressed as "you". You accept
the license if you copy, modify or distribute the work in a way
requiring permission under copyright law.
A "Modified Version" of the Document means any work containing the
Document or a portion of it, either copied verbatim, or with
modifications and/or translated into another language.
A "Secondary Section" is a named appendix or a front-matter section
of the Document that deals exclusively with the relationship of the
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subject (or to related matters) and contains nothing that could
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is in part a textbook of mathematics, a Secondary Section may not
explain any mathematics.) The relationship could be a matter of
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of legal, commercial, philosophical, ethical or political position
regarding them.
The "Invariant Sections" are certain Secondary Sections whose
titles are designated, as being those of Invariant Sections, in the
notice that says that the Document is released under this License.
If a section does not fit the above definition of Secondary then it
is not allowed to be designated as Invariant. The Document may
contain zero Invariant Sections. If the Document does not identify
any Invariant Sections then there are none.
The "Cover Texts" are certain short passages of text that are
listed, as Front-Cover Texts or Back-Cover Texts, in the notice
that says that the Document is released under this License. A
Front-Cover Text may be at most 5 words, and a Back-Cover Text may
be at most 25 words.
A "Transparent" copy of the Document means a machine-readable copy,
represented in a format whose specification is available to the
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formatters or for automatic translation to a variety of formats
suitable for input to text formatters. A copy made in an otherwise
Transparent file format whose markup, or absence of markup, has
been arranged to thwart or discourage subsequent modification by
readers is not Transparent. An image format is not Transparent if
used for any substantial amount of text. A copy that is not
"Transparent" is called "Opaque".
Examples of suitable formats for Transparent copies include plain
ASCII without markup, Texinfo input format, LaTeX input format,
SGML or XML using a publicly available DTD, and standard-conforming
simple HTML, PostScript or PDF designed for human modification.
Examples of transparent image formats include PNG, XCF and JPG.
Opaque formats include proprietary formats that can be read and
edited only by proprietary word processors, SGML or XML for which
the DTD and/or processing tools are not generally available, and
the machine-generated HTML, PostScript or PDF produced by some word
processors for output purposes only.
The "Title Page" means, for a printed book, the title page itself,
plus such following pages as are needed to hold, legibly, the
material this License requires to appear in the title page. For
works in formats which do not have any title page as such, "Title
Page" means the text near the most prominent appearance of the
work's title, preceding the beginning of the body of the text.
The "publisher" means any person or entity that distributes copies
of the Document to the public.
A section "Entitled XYZ" means a named subunit of the Document
whose title either is precisely XYZ or contains XYZ in parentheses
following text that translates XYZ in another language. (Here XYZ
stands for a specific section name mentioned below, such as
"Acknowledgements", "Dedications", "Endorsements", or "History".)
To "Preserve the Title" of such a section when you modify the
Document means that it remains a section "Entitled XYZ" according
to this definition.
The Document may include Warranty Disclaimers next to the notice
which states that this License applies to the Document. These
Warranty Disclaimers are considered to be included by reference in
this License, but only as regards disclaiming warranties: any other
implication that these Warranty Disclaimers may have is void and
has no effect on the meaning of this License.
2. VERBATIM COPYING
You may copy and distribute the Document in any medium, either
commercially or noncommercially, provided that this License, the
copyright notices, and the license notice saying this License
applies to the Document are reproduced in all copies, and that you
add no other conditions whatsoever to those of this License. You
may not use technical measures to obstruct or control the reading
or further copying of the copies you make or distribute. However,
you may accept compensation in exchange for copies. If you
distribute a large enough number of copies you must also follow the
conditions in section 3.
You may also lend copies, under the same conditions stated above,
and you may publicly display copies.
3. COPYING IN QUANTITY
If you publish printed copies (or copies in media that commonly
have printed covers) of the Document, numbering more than 100, and
the Document's license notice requires Cover Texts, you must
enclose the copies in covers that carry, clearly and legibly, all
these Cover Texts: Front-Cover Texts on the front cover, and
Back-Cover Texts on the back cover. Both covers must also clearly
and legibly identify you as the publisher of these copies. The
front cover must present the full title with all words of the title
equally prominent and visible. You may add other material on the
covers in addition. Copying with changes limited to the covers, as
long as they preserve the title of the Document and satisfy these
conditions, can be treated as verbatim copying in other respects.
If the required texts for either cover are too voluminous to fit
legibly, you should put the first ones listed (as many as fit
reasonably) on the actual cover, and continue the rest onto
adjacent pages.
If you publish or distribute Opaque copies of the Document
numbering more than 100, you must either include a machine-readable
Transparent copy along with each Opaque copy, or state in or with
each Opaque copy a computer-network location from which the general
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network protocols a complete Transparent copy of the Document, free
of added material. If you use the latter option, you must take
reasonably prudent steps, when you begin distribution of Opaque
copies in quantity, to ensure that this Transparent copy will
remain thus accessible at the stated location until at least one
year after the last time you distribute an Opaque copy (directly or
through your agents or retailers) of that edition to the public.
It is requested, but not required, that you contact the authors of
the Document well before redistributing any large number of copies,
to give them a chance to provide you with an updated version of the
Document.
4. MODIFICATIONS
You may copy and distribute a Modified Version of the Document
under the conditions of sections 2 and 3 above, provided that you
release the Modified Version under precisely this License, with the
Modified Version filling the role of the Document, thus licensing
distribution and modification of the Modified Version to whoever
possesses a copy of it. In addition, you must do these things in
the Modified Version:
A. Use in the Title Page (and on the covers, if any) a title
distinct from that of the Document, and from those of previous
versions (which should, if there were any, be listed in the
History section of the Document). You may use the same title
as a previous version if the original publisher of that
version gives permission.
B. List on the Title Page, as authors, one or more persons or
entities responsible for authorship of the modifications in
the Modified Version, together with at least five of the
principal authors of the Document (all of its principal
authors, if it has fewer than five), unless they release you
from this requirement.
C. State on the Title page the name of the publisher of the
Modified Version, as the publisher.
D. Preserve all the copyright notices of the Document.
E. Add an appropriate copyright notice for your modifications
adjacent to the other copyright notices.
F. Include, immediately after the copyright notices, a license
notice giving the public permission to use the Modified
Version under the terms of this License, in the form shown in
the Addendum below.
G. Preserve in that license notice the full lists of Invariant
Sections and required Cover Texts given in the Document's
license notice.
H. Include an unaltered copy of this License.
I. Preserve the section Entitled "History", Preserve its Title,
and add to it an item stating at least the title, year, new
authors, and publisher of the Modified Version as given on the
Title Page. If there is no section Entitled "History" in the
Document, create one stating the title, year, authors, and
publisher of the Document as given on its Title Page, then add
an item describing the Modified Version as stated in the
previous sentence.
J. Preserve the network location, if any, given in the Document
for public access to a Transparent copy of the Document, and
likewise the network locations given in the Document for
previous versions it was based on. These may be placed in the
"History" section. You may omit a network location for a work
that was published at least four years before the Document
itself, or if the original publisher of the version it refers
to gives permission.
K. For any section Entitled "Acknowledgements" or "Dedications",
Preserve the Title of the section, and preserve in the section
all the substance and tone of each of the contributor
acknowledgements and/or dedications given therein.
L. Preserve all the Invariant Sections of the Document, unaltered
in their text and in their titles. Section numbers or the
equivalent are not considered part of the section titles.
M. Delete any section Entitled "Endorsements". Such a section
may not be included in the Modified Version.
N. Do not retitle any existing section to be Entitled
"Endorsements" or to conflict in title with any Invariant
Section.
O. Preserve any Warranty Disclaimers.
If the Modified Version includes new front-matter sections or
appendices that qualify as Secondary Sections and contain no
material copied from the Document, you may at your option designate
some or all of these sections as invariant. To do this, add their
titles to the list of Invariant Sections in the Modified Version's
license notice. These titles must be distinct from any other
section titles.
You may add a section Entitled "Endorsements", provided it contains
nothing but endorsements of your Modified Version by various
parties--for example, statements of peer review or that the text
has been approved by an organization as the authoritative
definition of a standard.
You may add a passage of up to five words as a Front-Cover Text,
and a passage of up to 25 words as a Back-Cover Text, to the end of
the list of Cover Texts in the Modified Version. Only one passage
of Front-Cover Text and one of Back-Cover Text may be added by (or
through arrangements made by) any one entity. If the Document
already includes a cover text for the same cover, previously added
by you or by arrangement made by the same entity you are acting on
behalf of, you may not add another; but you may replace the old
one, on explicit permission from the previous publisher that added
the old one.
The author(s) and publisher(s) of the Document do not by this
License give permission to use their names for publicity for or to
assert or imply endorsement of any Modified Version.
5. COMBINING DOCUMENTS
You may combine the Document with other documents released under
this License, under the terms defined in section 4 above for
modified versions, provided that you include in the combination all
of the Invariant Sections of all of the original documents,
unmodified, and list them all as Invariant Sections of your
combined work in its license notice, and that you preserve all
their Warranty Disclaimers.
The combined work need only contain one copy of this License, and
multiple identical Invariant Sections may be replaced with a single
copy. If there are multiple Invariant Sections with the same name
but different contents, make the title of each such section unique
by adding at the end of it, in parentheses, the name of the
original author or publisher of that section if known, or else a
unique number. Make the same adjustment to the section titles in
the list of Invariant Sections in the license notice of the
combined work.
In the combination, you must combine any sections Entitled
"History" in the various original documents, forming one section
Entitled "History"; likewise combine any sections Entitled
"Acknowledgements", and any sections Entitled "Dedications". You
must delete all sections Entitled "Endorsements."
6. COLLECTIONS OF DOCUMENTS
You may make a collection consisting of the Document and other
documents released under this License, and replace the individual
copies of this License in the various documents with a single copy
that is included in the collection, provided that you follow the
rules of this License for verbatim copying of each of the documents
in all other respects.
You may extract a single document from such a collection, and
distribute it individually under this License, provided you insert
a copy of this License into the extracted document, and follow this
License in all other respects regarding verbatim copying of that
document.
7. AGGREGATION WITH INDEPENDENT WORKS
A compilation of the Document or its derivatives with other
separate and independent documents or works, in or on a volume of a
storage or distribution medium, is called an "aggregate" if the
copyright resulting from the compilation is not used to limit the
legal rights of the compilation's users beyond what the individual
works permit. When the Document is included in an aggregate, this
License does not apply to the other works in the aggregate which
are not themselves derivative works of the Document.
If the Cover Text requirement of section 3 is applicable to these
copies of the Document, then if the Document is less than one half
of the entire aggregate, the Document's Cover Texts may be placed
on covers that bracket the Document within the aggregate, or the
electronic equivalent of covers if the Document is in electronic
form. Otherwise they must appear on printed covers that bracket
the whole aggregate.
8. TRANSLATION
Translation is considered a kind of modification, so you may
distribute translations of the Document under the terms of section
4. Replacing Invariant Sections with translations requires special
permission from their copyright holders, but you may include
translations of some or all Invariant Sections in addition to the
original versions of these Invariant Sections. You may include a
translation of this License, and all the license notices in the
Document, and any Warranty Disclaimers, provided that you also
include the original English version of this License and the
original versions of those notices and disclaimers. In case of a
disagreement between the translation and the original version of
this License or a notice or disclaimer, the original version will
prevail.
If a section in the Document is Entitled "Acknowledgements",
"Dedications", or "History", the requirement (section 4) to
Preserve its Title (section 1) will typically require changing the
actual title.
9. TERMINATION
You may not copy, modify, sublicense, or distribute the Document
except as expressly provided under this License. Any attempt
otherwise to copy, modify, sublicense, or distribute it is void,
and will automatically terminate your rights under this License.
However, if you cease all violation of this License, then your
license from a particular copyright holder is reinstated (a)
provisionally, unless and until the copyright holder explicitly and
finally terminates your license, and (b) permanently, if the
copyright holder fails to notify you of the violation by some
reasonable means prior to 60 days after the cessation.
Moreover, your license from a particular copyright holder is
reinstated permanently if the copyright holder notifies you of the
violation by some reasonable means, this is the first time you have
received notice of violation of this License (for any work) from
that copyright holder, and you cure the violation prior to 30 days
after your receipt of the notice.
Termination of your rights under this section does not terminate
the licenses of parties who have received copies or rights from you
under this License. If your rights have been terminated and not
permanently reinstated, receipt of a copy of some or all of the
same material does not give you any rights to use it.
10. FUTURE REVISIONS OF THIS LICENSE
The Free Software Foundation may publish new, revised versions of
the GNU Free Documentation License from time to time. Such new
versions will be similar in spirit to the present version, but may
differ in detail to address new problems or concerns. See
<http://www.gnu.org/copyleft/>.
Each version of the License is given a distinguishing version
number. If the Document specifies that a particular numbered
version of this License "or any later version" applies to it, you
have the option of following the terms and conditions either of
that specified version or of any later version that has been
published (not as a draft) by the Free Software Foundation. If the
Document does not specify a version number of this License, you may
choose any version ever published (not as a draft) by the Free
Software Foundation. If the Document specifies that a proxy can
decide which future versions of this License can be used, that
proxy's public statement of acceptance of a version permanently
authorizes you to choose that version for the Document.
11. RELICENSING
"Massive Multiauthor Collaboration Site" (or "MMC Site") means any
World Wide Web server that publishes copyrightable works and also
provides prominent facilities for anybody to edit those works. A
public wiki that anybody can edit is an example of such a server.
A "Massive Multiauthor Collaboration" (or "MMC") contained in the
site means any set of copyrightable works thus published on the MMC
site.
"CC-BY-SA" means the Creative Commons Attribution-Share Alike 3.0
license published by Creative Commons Corporation, a not-for-profit
corporation with a principal place of business in San Francisco,
California, as well as future copyleft versions of that license
published by that same organization.
"Incorporate" means to publish or republish a Document, in whole or
in part, as part of another Document.
An MMC is "eligible for relicensing" if it is licensed under this
License, and if all works that were first published under this
License somewhere other than this MMC, and subsequently
incorporated in whole or in part into the MMC, (1) had no cover
texts or invariant sections, and (2) were thus incorporated prior
to November 1, 2008.
The operator of an MMC Site may republish an MMC contained in the
site under CC-BY-SA on the same site at any time before August 1,
2009, provided the MMC is eligible for relicensing.
ADDENDUM: How to use this License for your documents
====================================================
To use this License in a document you have written, include a copy of
the License in the document and put the following copyright and license
notices just after the title page:
Copyright (C) YEAR YOUR NAME.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
or any later version published by the Free Software Foundation;
with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
Texts. A copy of the license is included in the section entitled ``GNU
Free Documentation License''.
If you have Invariant Sections, Front-Cover Texts and Back-Cover
Texts, replace the "with...Texts." line with this:
with the Invariant Sections being LIST THEIR TITLES, with
the Front-Cover Texts being LIST, and with the Back-Cover Texts
being LIST.
If you have Invariant Sections without Cover Texts, or some other
combination of the three, merge those two alternatives to suit the
situation.
If your document contains nontrivial examples of program code, we
recommend releasing these examples in parallel under your choice of free
software license, such as the GNU General Public License, to permit
their use in free software.

File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top
AS Index
********
�[index�]
* Menu:
* #: Comments. (line 33)
* #APP: Preprocessing. (line 26)
* #NO_APP: Preprocessing. (line 26)
* '$' in symbol names: D10V-Chars. (line 46)
* '$' in symbol names <1>: D30V-Chars. (line 70)
* '$' in symbol names <2>: Meta-Chars. (line 10)
* '$' in symbol names <3>: SH-Chars. (line 15)
* '$' in symbol names <4>: SH64-Chars. (line 15)
* '$a': ARM Mapping Symbols. (line 9)
* '$acos' math builtin, TIC54X: TIC54X-Builtins. (line 10)
* '$asin' math builtin, TIC54X: TIC54X-Builtins. (line 13)
* '$atan' math builtin, TIC54X: TIC54X-Builtins. (line 16)
* '$atan2' math builtin, TIC54X: TIC54X-Builtins. (line 19)
* '$ceil' math builtin, TIC54X: TIC54X-Builtins. (line 22)
* '$cos' math builtin, TIC54X: TIC54X-Builtins. (line 28)
* '$cosh' math builtin, TIC54X: TIC54X-Builtins. (line 25)
* '$cvf' math builtin, TIC54X: TIC54X-Builtins. (line 31)
* '$cvi' math builtin, TIC54X: TIC54X-Builtins. (line 34)
* '$d': AArch64 Mapping Symbols.
(line 12)
* '$d' <1>: ARM Mapping Symbols. (line 15)
* '$exp' math builtin, TIC54X: TIC54X-Builtins. (line 37)
* '$fabs' math builtin, TIC54X: TIC54X-Builtins. (line 40)
* '$firstch' subsym builtin, TIC54X: TIC54X-Macros. (line 26)
* '$floor' math builtin, TIC54X: TIC54X-Builtins. (line 43)
* '$fmod' math builtin, TIC54X: TIC54X-Builtins. (line 47)
* '$int' math builtin, TIC54X: TIC54X-Builtins. (line 50)
* '$iscons' subsym builtin, TIC54X: TIC54X-Macros. (line 43)
* '$isdefed' subsym builtin, TIC54X: TIC54X-Macros. (line 34)
* '$ismember' subsym builtin, TIC54X: TIC54X-Macros. (line 38)
* '$isname' subsym builtin, TIC54X: TIC54X-Macros. (line 47)
* '$isreg' subsym builtin, TIC54X: TIC54X-Macros. (line 50)
* '$lastch' subsym builtin, TIC54X: TIC54X-Macros. (line 30)
* '$ldexp' math builtin, TIC54X: TIC54X-Builtins. (line 53)
* '$log' math builtin, TIC54X: TIC54X-Builtins. (line 59)
* '$log10' math builtin, TIC54X: TIC54X-Builtins. (line 56)
* '$max' math builtin, TIC54X: TIC54X-Builtins. (line 62)
* '$min' math builtin, TIC54X: TIC54X-Builtins. (line 65)
* '$pow' math builtin, TIC54X: TIC54X-Builtins. (line 68)
* '$round' math builtin, TIC54X: TIC54X-Builtins. (line 71)
* '$sgn' math builtin, TIC54X: TIC54X-Builtins. (line 74)
* '$sin' math builtin, TIC54X: TIC54X-Builtins. (line 77)
* '$sinh' math builtin, TIC54X: TIC54X-Builtins. (line 80)
* '$sqrt' math builtin, TIC54X: TIC54X-Builtins. (line 83)
* '$structacc' subsym builtin, TIC54X: TIC54X-Macros. (line 57)
* '$structsz' subsym builtin, TIC54X: TIC54X-Macros. (line 54)
* '$symcmp' subsym builtin, TIC54X: TIC54X-Macros. (line 23)
* '$symlen' subsym builtin, TIC54X: TIC54X-Macros. (line 20)
* '$t': ARM Mapping Symbols. (line 12)
* '$tan' math builtin, TIC54X: TIC54X-Builtins. (line 86)
* '$tanh' math builtin, TIC54X: TIC54X-Builtins. (line 89)
* '$trunc' math builtin, TIC54X: TIC54X-Builtins. (line 92)
* '$x': AArch64 Mapping Symbols.
(line 9)
* %gp: RX-Modifiers. (line 6)
* '%gpreg': RX-Modifiers. (line 22)
* '%pidreg': RX-Modifiers. (line 25)
* '-+' option, VAX/VMS: VAX-Opts. (line 71)
* --: Command Line. (line 10)
* '--32' option, i386: i386-Options. (line 8)
* '--32' option, x86-64: i386-Options. (line 8)
* '--64' option, i386: i386-Options. (line 8)
* '--64' option, x86-64: i386-Options. (line 8)
* --absolute-literals: Xtensa Options. (line 20)
* --allow-reg-prefix: SH Options. (line 9)
* --alternate: alternate. (line 6)
* '--base-size-default-16': M68K-Opts. (line 66)
* '--base-size-default-32': M68K-Opts. (line 66)
* --big: SH Options. (line 9)
* '--bitwise-or' option, M680x0: M68K-Opts. (line 59)
* '--disp-size-default-16': M68K-Opts. (line 75)
* '--disp-size-default-32': M68K-Opts. (line 75)
* '--divide' option, i386: i386-Options. (line 24)
* --dsp: SH Options. (line 9)
* '--emulation=crisaout' command line option, CRIS: CRIS-Opts.
(line 9)
* '--emulation=criself' command line option, CRIS: CRIS-Opts. (line 9)
* --enforce-aligned-data: Sparc-Aligned-Data. (line 11)
* --fatal-warnings: W. (line 16)
* --fdpic: SH Options. (line 31)
* '--fix-v4bx' command line option, ARM: ARM Options. (line 177)
* '--fixed-special-register-names' command line option, MMIX: MMIX-Opts.
(line 8)
* '--force-long-branches': M68HC11-Opts. (line 81)
* '--generate-example': M68HC11-Opts. (line 98)
* '--globalize-symbols' command line option, MMIX: MMIX-Opts. (line 12)
* '--gnu-syntax' command line option, MMIX: MMIX-Opts. (line 16)
* --hash-size=NUMBER: Overview. (line 422)
* '--linker-allocated-gregs' command line option, MMIX: MMIX-Opts.
(line 67)
* --listing-cont-lines: listing. (line 34)
* --listing-lhs-width: listing. (line 16)
* --listing-lhs-width2: listing. (line 21)
* --listing-rhs-width: listing. (line 28)
* --little: SH Options. (line 9)
* --longcalls: Xtensa Options. (line 34)
* '--march=ARCHITECTURE' command line option, CRIS: CRIS-Opts.
(line 34)
* --MD: MD. (line 6)
* '--mul-bug-abort' command line option, CRIS: CRIS-Opts. (line 63)
* --no-absolute-literals: Xtensa Options. (line 20)
* '--no-expand' command line option, MMIX: MMIX-Opts. (line 31)
* --no-longcalls: Xtensa Options. (line 34)
* '--no-merge-gregs' command line option, MMIX: MMIX-Opts. (line 36)
* '--no-mul-bug-abort' command line option, CRIS: CRIS-Opts. (line 63)
* '--no-predefined-syms' command line option, MMIX: MMIX-Opts.
(line 22)
* '--no-pushj-stubs' command line option, MMIX: MMIX-Opts. (line 54)
* '--no-stubs' command line option, MMIX: MMIX-Opts. (line 54)
* --no-target-align: Xtensa Options. (line 27)
* --no-text-section-literals: Xtensa Options. (line 7)
* --no-trampolines: Xtensa Options. (line 55)
* --no-transform: Xtensa Options. (line 43)
* '--no-underscore' command line option, CRIS: CRIS-Opts. (line 15)
* --no-warn: W. (line 11)
* '--pcrel': M68K-Opts. (line 87)
* '--pic' command line option, CRIS: CRIS-Opts. (line 27)
* '--print-insn-syntax': M68HC11-Opts. (line 87)
* '--print-insn-syntax' <1>: XGATE-Opts. (line 25)
* '--print-opcodes': M68HC11-Opts. (line 91)
* '--print-opcodes' <1>: XGATE-Opts. (line 29)
* '--register-prefix-optional' option, M680x0: M68K-Opts. (line 46)
* --relax: SH Options. (line 9)
* '--relax' command line option, MMIX: MMIX-Opts. (line 19)
* --rename-section: Xtensa Options. (line 51)
* --renesas: SH Options. (line 9)
* --sectname-subst: Section. (line 70)
* '--short-branches': M68HC11-Opts. (line 67)
* --small: SH Options. (line 9)
* --statistics: statistics. (line 6)
* '--strict-direct-mode': M68HC11-Opts. (line 57)
* --target-align: Xtensa Options. (line 27)
* --text-section-literals: Xtensa Options. (line 7)
* --traditional-format: traditional-format. (line 6)
* --trampolines: Xtensa Options. (line 55)
* --transform: Xtensa Options. (line 43)
* '--underscore' command line option, CRIS: CRIS-Opts. (line 15)
* --warn: W. (line 19)
* '--x32' option, i386: i386-Options. (line 8)
* '--x32' option, x86-64: i386-Options. (line 8)
* '--xgate-ramoffset': M68HC11-Opts. (line 36)
* '-1' option, VAX/VMS: VAX-Opts. (line 77)
* '-32addr' command line option, Alpha: Alpha Options. (line 57)
* -a: a. (line 6)
* '-A' options, i960: Options-i960. (line 6)
* -ac: a. (line 6)
* -ad: a. (line 6)
* -ag: a. (line 6)
* -ah: a. (line 6)
* -al: a. (line 6)
* -Aleon: Sparc-Opts. (line 25)
* -an: a. (line 6)
* -as: a. (line 6)
* -Asparc: Sparc-Opts. (line 25)
* -Asparcfmaf: Sparc-Opts. (line 25)
* -Asparcima: Sparc-Opts. (line 25)
* -Asparclet: Sparc-Opts. (line 25)
* -Asparclite: Sparc-Opts. (line 25)
* -Asparcvis: Sparc-Opts. (line 25)
* -Asparcvis2: Sparc-Opts. (line 25)
* -Asparcvis3: Sparc-Opts. (line 25)
* -Asparcvis3r: Sparc-Opts. (line 25)
* -Av6: Sparc-Opts. (line 25)
* -Av7: Sparc-Opts. (line 25)
* -Av8: Sparc-Opts. (line 25)
* -Av9: Sparc-Opts. (line 25)
* -Av9a: Sparc-Opts. (line 25)
* -Av9b: Sparc-Opts. (line 25)
* -Av9c: Sparc-Opts. (line 25)
* -Av9d: Sparc-Opts. (line 25)
* -Av9e: Sparc-Opts. (line 25)
* -Av9m: Sparc-Opts. (line 25)
* -Av9v: Sparc-Opts. (line 25)
* '-b' option, i960: Options-i960. (line 22)
* '-big' option, M32R: M32R-Opts. (line 35)
* -D: D. (line 6)
* '-D', ignored on VAX: VAX-Opts. (line 11)
* '-d', VAX option: VAX-Opts. (line 16)
* '-eabi=' command line option, ARM: ARM Options. (line 160)
* '-EB' command line option, AArch64: AArch64 Options. (line 6)
* '-EB' command line option, ARC: ARC Options. (line 30)
* '-EB' command line option, ARM: ARM Options. (line 165)
* '-EB' option (MIPS): MIPS Options. (line 13)
* '-EB' option, M32R: M32R-Opts. (line 39)
* '-EB' option, TILE-Gx: TILE-Gx Options. (line 11)
* '-EL' command line option, AArch64: AArch64 Options. (line 10)
* '-EL' command line option, ARC: ARC Options. (line 34)
* '-EL' command line option, ARM: ARM Options. (line 169)
* '-EL' option (MIPS): MIPS Options. (line 13)
* '-EL' option, M32R: M32R-Opts. (line 32)
* '-EL' option, TILE-Gx: TILE-Gx Options. (line 11)
* -f: f. (line 6)
* '-F' command line option, Alpha: Alpha Options. (line 57)
* '-g' command line option, Alpha: Alpha Options. (line 47)
* '-G' command line option, Alpha: Alpha Options. (line 53)
* '-G' option (MIPS): MIPS Options. (line 8)
* '-h' option, VAX/VMS: VAX-Opts. (line 45)
* '-H' option, VAX/VMS: VAX-Opts. (line 81)
* -I PATH: I. (line 6)
* '-ignore-parallel-conflicts' option, M32RX: M32R-Opts. (line 87)
* '-Ip' option, M32RX: M32R-Opts. (line 97)
* '-J', ignored on VAX: VAX-Opts. (line 27)
* -K: K. (line 6)
* '-k' command line option, ARM: ARM Options. (line 173)
* '-KPIC' option, M32R: M32R-Opts. (line 42)
* '-KPIC' option, MIPS: MIPS Options. (line 21)
* -L: L. (line 6)
* '-l' option, M680x0: M68K-Opts. (line 34)
* '-little' option, M32R: M32R-Opts. (line 27)
* -M: M. (line 6)
* -m11/03: PDP-11-Options. (line 140)
* -m11/04: PDP-11-Options. (line 143)
* -m11/05: PDP-11-Options. (line 146)
* -m11/10: PDP-11-Options. (line 146)
* -m11/15: PDP-11-Options. (line 149)
* -m11/20: PDP-11-Options. (line 149)
* -m11/21: PDP-11-Options. (line 152)
* -m11/23: PDP-11-Options. (line 155)
* -m11/24: PDP-11-Options. (line 155)
* -m11/34: PDP-11-Options. (line 158)
* -m11/34a: PDP-11-Options. (line 161)
* -m11/35: PDP-11-Options. (line 164)
* -m11/40: PDP-11-Options. (line 164)
* -m11/44: PDP-11-Options. (line 167)
* -m11/45: PDP-11-Options. (line 170)
* -m11/50: PDP-11-Options. (line 170)
* -m11/53: PDP-11-Options. (line 173)
* -m11/55: PDP-11-Options. (line 170)
* -m11/60: PDP-11-Options. (line 176)
* -m11/70: PDP-11-Options. (line 170)
* -m11/73: PDP-11-Options. (line 173)
* -m11/83: PDP-11-Options. (line 173)
* -m11/84: PDP-11-Options. (line 173)
* -m11/93: PDP-11-Options. (line 173)
* -m11/94: PDP-11-Options. (line 173)
* '-m16c' option, M16C: M32C-Opts. (line 12)
* '-m31' option, s390: s390 Options. (line 8)
* '-m32' option, TILE-Gx: TILE-Gx Options. (line 8)
* '-m32bit-doubles': RX-Opts. (line 9)
* '-m32c' option, M32C: M32C-Opts. (line 9)
* '-m32r' option, M32R: M32R-Opts. (line 21)
* '-m32rx' option, M32R2: M32R-Opts. (line 17)
* '-m32rx' option, M32RX: M32R-Opts. (line 9)
* '-m4byte-align' command line option, V850: V850 Options. (line 90)
* '-m64' option, s390: s390 Options. (line 8)
* '-m64' option, TILE-Gx: TILE-Gx Options. (line 8)
* '-m64bit-doubles': RX-Opts. (line 15)
* '-m68000' and related options: M68K-Opts. (line 99)
* '-m68hc11': M68HC11-Opts. (line 9)
* '-m68hc12': M68HC11-Opts. (line 14)
* '-m68hcs12': M68HC11-Opts. (line 21)
* '-m8byte-align' command line option, V850: V850 Options. (line 86)
* '-mabi=' command line option, AArch64: AArch64 Options. (line 14)
* '-madd-bnd-prefix' option, i386: i386-Options. (line 126)
* '-madd-bnd-prefix' option, x86-64: i386-Options. (line 126)
* -mall: PDP-11-Options. (line 26)
* '-mall-enabled' command line option, LM32: LM32 Options. (line 30)
* -mall-extensions: PDP-11-Options. (line 26)
* '-mall-opcodes' command line option, AVR: AVR Options. (line 108)
* '-mapcs-26' command line option, ARM: ARM Options. (line 132)
* '-mapcs-32' command line option, ARM: ARM Options. (line 132)
* '-mapcs-float' command line option, ARM: ARM Options. (line 146)
* '-mapcs-reentrant' command line option, ARM: ARM Options. (line 151)
* '-march=' command line option, AArch64: AArch64 Options. (line 37)
* '-march=' command line option, ARM: ARM Options. (line 67)
* '-march=' command line option, M680x0: M68K-Opts. (line 8)
* '-march=' command line option, TIC6X: TIC6X Options. (line 6)
* '-march=' option, i386: i386-Options. (line 31)
* '-march=' option, s390: s390 Options. (line 25)
* '-march=' option, x86-64: i386-Options. (line 31)
* '-marc[5|6|7|8]' command line option, ARC: ARC Options. (line 6)
* '-matpcs' command line option, ARM: ARM Options. (line 138)
* '-mavxscalar=' option, i386: i386-Options. (line 84)
* '-mavxscalar=' option, x86-64: i386-Options. (line 84)
* '-mbarrel-shift-enabled' command line option, LM32: LM32 Options.
(line 12)
* '-mbig-endian': RX-Opts. (line 20)
* '-mbig-obj' option, x86-64: i386-Options. (line 131)
* '-mbreak-enabled' command line option, LM32: LM32 Options. (line 27)
* '-mccs' command line option, ARM: ARM Options. (line 186)
* -mcis: PDP-11-Options. (line 32)
* '-mconstant-gp' command line option, IA-64: IA-64 Options. (line 6)
* '-mCPU' command line option, Alpha: Alpha Options. (line 6)
* '-mcpu' option, cpu: TIC54X-Opts. (line 15)
* '-mcpu=': RX-Opts. (line 75)
* '-mcpu=' command line option, AArch64: AArch64 Options. (line 19)
* '-mcpu=' command line option, ARM: ARM Options. (line 6)
* '-mcpu=' command line option, Blackfin: Blackfin Options. (line 6)
* '-mcpu=' command line option, M680x0: M68K-Opts. (line 14)
* -mcsm: PDP-11-Options. (line 43)
* '-mdcache-enabled' command line option, LM32: LM32 Options. (line 24)
* '-mdebug' command line option, Alpha: Alpha Options. (line 25)
* '-mdivide-enabled' command line option, LM32: LM32 Options. (line 9)
* '-mdsbt' command line option, TIC6X: TIC6X Options. (line 13)
* '-me' option, stderr redirect: TIC54X-Opts. (line 20)
* -meis: PDP-11-Options. (line 46)
* '-mepiphany' command line option, Epiphany: Epiphany Options.
(line 9)
* '-mepiphany16' command line option, Epiphany: Epiphany Options.
(line 13)
* '-merrors-to-file' option, stderr redirect: TIC54X-Opts. (line 20)
* '-mesa' option, s390: s390 Options. (line 17)
* '-mevexlig=' option, i386: i386-Options. (line 92)
* '-mevexlig=' option, x86-64: i386-Options. (line 92)
* '-mevexrcig=' option, i386: i386-Options. (line 144)
* '-mevexrcig=' option, x86-64: i386-Options. (line 144)
* '-mevexwig=' option, i386: i386-Options. (line 102)
* '-mevexwig=' option, x86-64: i386-Options. (line 102)
* '-mf' option, far-mode: TIC54X-Opts. (line 8)
* -mf11: PDP-11-Options. (line 122)
* '-mfar-mode' option, far-mode: TIC54X-Opts. (line 8)
* '-mfdpic' command line option, Blackfin: Blackfin Options. (line 19)
* -mfis: PDP-11-Options. (line 51)
* '-mfloat-abi=' command line option, ARM: ARM Options. (line 155)
* -mfp-11: PDP-11-Options. (line 56)
* -mfpp: PDP-11-Options. (line 56)
* -mfpu: PDP-11-Options. (line 56)
* '-mfpu=' command line option, ARM: ARM Options. (line 83)
* '-mgcc-abi': RX-Opts. (line 63)
* '-mgcc-abi' command line option, V850: V850 Options. (line 79)
* '-micache-enabled' command line option, LM32: LM32 Options. (line 21)
* '-mimplicit-it' command line option, ARM: ARM Options. (line 116)
* '-mint-register': RX-Opts. (line 57)
* '-mip2022' option, IP2K: IP2K-Opts. (line 14)
* '-mip2022ext' option, IP2022: IP2K-Opts. (line 9)
* -mj11: PDP-11-Options. (line 126)
* -mka11: PDP-11-Options. (line 92)
* -mkb11: PDP-11-Options. (line 95)
* -mkd11a: PDP-11-Options. (line 98)
* -mkd11b: PDP-11-Options. (line 101)
* -mkd11d: PDP-11-Options. (line 104)
* -mkd11e: PDP-11-Options. (line 107)
* -mkd11f: PDP-11-Options. (line 110)
* -mkd11h: PDP-11-Options. (line 110)
* -mkd11k: PDP-11-Options. (line 114)
* -mkd11q: PDP-11-Options. (line 110)
* -mkd11z: PDP-11-Options. (line 118)
* -mkev11: PDP-11-Options. (line 51)
* -mkev11 <1>: PDP-11-Options. (line 51)
* -mlimited-eis: PDP-11-Options. (line 64)
* '-mlittle-endian': RX-Opts. (line 26)
* '-mlong': M68HC11-Opts. (line 45)
* '-mlong' <1>: XGATE-Opts. (line 13)
* '-mlong-double': M68HC11-Opts. (line 53)
* '-mlong-double' <1>: XGATE-Opts. (line 21)
* '-mm9s12x': M68HC11-Opts. (line 27)
* '-mm9s12xg': M68HC11-Opts. (line 32)
* '-mmcu=' command line option, AVR: AVR Options. (line 6)
* -mmfpt: PDP-11-Options. (line 70)
* -mmicrocode: PDP-11-Options. (line 83)
* '-mmnemonic=' option, i386: i386-Options. (line 109)
* '-mmnemonic=' option, x86-64: i386-Options. (line 109)
* '-mmultiply-enabled' command line option, LM32: LM32 Options.
(line 6)
* -mmutiproc: PDP-11-Options. (line 73)
* -mmxps: PDP-11-Options. (line 77)
* '-mnaked-reg' option, i386: i386-Options. (line 121)
* '-mnaked-reg' option, x86-64: i386-Options. (line 121)
* '-mnan=' command line option, MIPS: MIPS Options. (line 338)
* -mno-cis: PDP-11-Options. (line 32)
* -mno-csm: PDP-11-Options. (line 43)
* '-mno-dsbt' command line option, TIC6X: TIC6X Options. (line 13)
* -mno-eis: PDP-11-Options. (line 46)
* -mno-extensions: PDP-11-Options. (line 29)
* '-mno-fdpic' command line option, Blackfin: Blackfin Options.
(line 22)
* -mno-fis: PDP-11-Options. (line 51)
* -mno-fp-11: PDP-11-Options. (line 56)
* -mno-fpp: PDP-11-Options. (line 56)
* -mno-fpu: PDP-11-Options. (line 56)
* -mno-kev11: PDP-11-Options. (line 51)
* -mno-limited-eis: PDP-11-Options. (line 64)
* -mno-mfpt: PDP-11-Options. (line 70)
* -mno-microcode: PDP-11-Options. (line 83)
* -mno-mutiproc: PDP-11-Options. (line 73)
* -mno-mxps: PDP-11-Options. (line 77)
* -mno-pic: PDP-11-Options. (line 11)
* '-mno-pic' command line option, TIC6X: TIC6X Options. (line 36)
* '-mno-regnames' option, s390: s390 Options. (line 35)
* '-mno-skip-bug' command line option, AVR: AVR Options. (line 111)
* -mno-spl: PDP-11-Options. (line 80)
* -mno-sym32: MIPS Options. (line 280)
* '-mno-verbose-error' command line option, AArch64: AArch64 Options.
(line 57)
* '-mno-wrap' command line option, AVR: AVR Options. (line 114)
* '-mnopic' command line option, Blackfin: Blackfin Options. (line 22)
* '-momit-lock-prefix=' option, i386: i386-Options. (line 135)
* '-momit-lock-prefix=' option, x86-64: i386-Options. (line 135)
* -mpic: PDP-11-Options. (line 11)
* '-mpic' command line option, TIC6X: TIC6X Options. (line 36)
* '-mpid': RX-Opts. (line 50)
* '-mpid=' command line option, TIC6X: TIC6X Options. (line 23)
* '-mregnames' option, s390: s390 Options. (line 32)
* '-mrelax' command line option, V850: V850 Options. (line 72)
* '-mrh850-abi' command line option, V850: V850 Options. (line 82)
* '-mrmw' command line option, AVR: AVR Options. (line 117)
* '-mrx-abi': RX-Opts. (line 69)
* '-mshort': M68HC11-Opts. (line 40)
* '-mshort' <1>: XGATE-Opts. (line 8)
* '-mshort-double': M68HC11-Opts. (line 49)
* '-mshort-double' <1>: XGATE-Opts. (line 17)
* '-msign-extend-enabled' command line option, LM32: LM32 Options.
(line 15)
* '-msmall-data-limit': RX-Opts. (line 42)
* -mspl: PDP-11-Options. (line 80)
* '-msse-check=' option, i386: i386-Options. (line 74)
* '-msse-check=' option, x86-64: i386-Options. (line 74)
* '-msse2avx' option, i386: i386-Options. (line 70)
* '-msse2avx' option, x86-64: i386-Options. (line 70)
* -msym32: MIPS Options. (line 280)
* '-msyntax=' option, i386: i386-Options. (line 115)
* '-msyntax=' option, x86-64: i386-Options. (line 115)
* -mt11: PDP-11-Options. (line 130)
* '-mthumb' command line option, ARM: ARM Options. (line 107)
* '-mthumb-interwork' command line option, ARM: ARM Options. (line 112)
* '-mtune=' option, i386: i386-Options. (line 62)
* '-mtune=' option, x86-64: i386-Options. (line 62)
* '-muse-conventional-section-names': RX-Opts. (line 33)
* '-muse-renesas-section-names': RX-Opts. (line 37)
* '-muser-enabled' command line option, LM32: LM32 Options. (line 18)
* '-mv850' command line option, V850: V850 Options. (line 23)
* '-mv850any' command line option, V850: V850 Options. (line 41)
* '-mv850e' command line option, V850: V850 Options. (line 29)
* '-mv850e1' command line option, V850: V850 Options. (line 35)
* '-mv850e2' command line option, V850: V850 Options. (line 51)
* '-mv850e2v3' command line option, V850: V850 Options. (line 57)
* '-mv850e2v4' command line option, V850: V850 Options. (line 63)
* '-mv850e3v5' command line option, V850: V850 Options. (line 66)
* '-mverbose-error' command line option, AArch64: AArch64 Options.
(line 53)
* '-mvxworks-pic' option, MIPS: MIPS Options. (line 26)
* '-mwarn-areg-zero' option, s390: s390 Options. (line 38)
* '-mwarn-deprecated' command line option, ARM: ARM Options. (line 181)
* '-mzarch' option, s390: s390 Options. (line 17)
* '-m[no-]68851' command line option, M680x0: M68K-Opts. (line 21)
* '-m[no-]68881' command line option, M680x0: M68K-Opts. (line 21)
* '-m[no-]div' command line option, M680x0: M68K-Opts. (line 21)
* '-m[no-]emac' command line option, M680x0: M68K-Opts. (line 21)
* '-m[no-]float' command line option, M680x0: M68K-Opts. (line 21)
* '-m[no-]mac' command line option, M680x0: M68K-Opts. (line 21)
* '-m[no-]usp' command line option, M680x0: M68K-Opts. (line 21)
* '-N' command line option, CRIS: CRIS-Opts. (line 59)
* '-nIp' option, M32RX: M32R-Opts. (line 101)
* '-no-bitinst', M32R2: M32R-Opts. (line 54)
* '-no-ignore-parallel-conflicts' option, M32RX: M32R-Opts. (line 93)
* '-no-mdebug' command line option, Alpha: Alpha Options. (line 25)
* '-no-parallel' option, M32RX: M32R-Opts. (line 51)
* '-no-relax' option, i960: Options-i960. (line 66)
* '-no-warn-explicit-parallel-conflicts' option, M32RX: M32R-Opts.
(line 79)
* '-no-warn-unmatched-high' option, M32R: M32R-Opts. (line 111)
* '-nocpp' ignored (MIPS): MIPS Options. (line 283)
* '-noreplace' command line option, Alpha: Alpha Options. (line 40)
* -o: o. (line 6)
* '-O' option, M32RX: M32R-Opts. (line 59)
* '-parallel' option, M32RX: M32R-Opts. (line 46)
* -R: R. (line 6)
* '-r800' command line option, Z80: Z80 Options. (line 35)
* '-relax' command line option, Alpha: Alpha Options. (line 32)
* '-replace' command line option, Alpha: Alpha Options. (line 40)
* '-S', ignored on VAX: VAX-Opts. (line 11)
* '-T', ignored on VAX: VAX-Opts. (line 11)
* '-t', ignored on VAX: VAX-Opts. (line 36)
* -v: v. (line 6)
* '-V', redundant on VAX: VAX-Opts. (line 22)
* -version: v. (line 6)
* -W: W. (line 11)
* '-warn-explicit-parallel-conflicts' option, M32RX: M32R-Opts.
(line 65)
* '-warn-unmatched-high' option, M32R: M32R-Opts. (line 105)
* '-Wnp' option, M32RX: M32R-Opts. (line 83)
* '-Wnuh' option, M32RX: M32R-Opts. (line 117)
* '-Wp' option, M32RX: M32R-Opts. (line 75)
* '-wsigned_overflow' command line option, V850: V850 Options.
(line 9)
* '-Wuh' option, M32RX: M32R-Opts. (line 114)
* '-wunsigned_overflow' command line option, V850: V850 Options.
(line 16)
* '-x' command line option, MMIX: MMIX-Opts. (line 44)
* '-z80' command line option, Z80: Z80 Options. (line 8)
* '-z8001' command line option, Z8000: Z8000 Options. (line 6)
* '-z8002' command line option, Z8000: Z8000 Options. (line 9)
* '.' (symbol): Dot. (line 6)
* '.2byte' directive, ARM: ARM Directives. (line 6)
* '.4byte' directive, ARM: ARM Directives. (line 6)
* '.8byte' directive, ARM: ARM Directives. (line 6)
* '.align' directive, ARM: ARM Directives. (line 11)
* '.align' directive, TILE-Gx: TILE-Gx Directives. (line 6)
* '.align' directive, TILEPro: TILEPro Directives. (line 6)
* '.allow_suspicious_bundles' directive, TILE-Gx: TILE-Gx Directives.
(line 10)
* '.allow_suspicious_bundles' directive, TILEPro: TILEPro Directives.
(line 10)
* '.arch' directive, AArch64: AArch64 Directives. (line 6)
* '.arch' directive, ARM: ARM Directives. (line 18)
* '.arch' directive, TIC6X: TIC6X Directives. (line 10)
* '.arch_extension' directive, AArch64: AArch64 Directives. (line 13)
* '.arch_extension' directive, ARM: ARM Directives. (line 25)
* '.arm' directive, ARM: ARM Directives. (line 33)
* '.big' directive, M32RX: M32R-Directives. (line 88)
* '.bss' directive, AArch64: AArch64 Directives. (line 21)
* '.bss' directive, ARM: ARM Directives. (line 36)
* '.c6xabi_attribute' directive, TIC6X: TIC6X Directives. (line 20)
* '.cantunwind' directive, ARM: ARM Directives. (line 39)
* '.cantunwind' directive, TIC6X: TIC6X Directives. (line 13)
* '.code' directive, ARM: ARM Directives. (line 43)
* '.cpu' directive, ARM: ARM Directives. (line 47)
* '.dn' and '.qn' directives, ARM: ARM Directives. (line 54)
* '.eabi_attribute' directive, ARM: ARM Directives. (line 78)
* '.ehtype' directive, TIC6X: TIC6X Directives. (line 31)
* '.endp' directive, TIC6X: TIC6X Directives. (line 34)
* '.even' directive, ARM: ARM Directives. (line 106)
* '.extend' directive, ARM: ARM Directives. (line 109)
* '.fnend' directive, ARM: ARM Directives. (line 115)
* '.fnstart' directive, ARM: ARM Directives. (line 123)
* '.force_thumb' directive, ARM: ARM Directives. (line 126)
* '.fpu' directive, ARM: ARM Directives. (line 130)
* '.global': MIPS insn. (line 12)
* '.gnu_attribute 4, N' directive, MIPS: MIPS FP ABI History. (line 6)
* '.gnu_attribute Tag_GNU_MIPS_ABI_FP, N' directive, MIPS: MIPS FP ABI History.
(line 6)
* '.handlerdata' directive, ARM: ARM Directives. (line 134)
* '.handlerdata' directive, TIC6X: TIC6X Directives. (line 39)
* '.insn': MIPS insn. (line 6)
* '.insn' directive, s390: s390 Directives. (line 11)
* '.inst' directive, ARM: ARM Directives. (line 143)
* '.ldouble' directive, ARM: ARM Directives. (line 109)
* '.little' directive, M32RX: M32R-Directives. (line 82)
* '.long' directive, s390: s390 Directives. (line 16)
* '.ltorg' directive, AArch64: AArch64 Directives. (line 24)
* '.ltorg' directive, ARM: ARM Directives. (line 153)
* '.ltorg' directive, s390: s390 Directives. (line 79)
* '.m32r' directive, M32R: M32R-Directives. (line 66)
* '.m32r2' directive, M32R2: M32R-Directives. (line 77)
* '.m32rx' directive, M32RX: M32R-Directives. (line 72)
* '.machine' directive, s390: s390 Directives. (line 84)
* '.machinemode' directive, s390: s390 Directives. (line 93)
* '.module': MIPS assembly options.
(line 6)
* '.module fp=NN' directive, MIPS: MIPS FP ABI Selection.
(line 6)
* '.movsp' directive, ARM: ARM Directives. (line 167)
* '.nan' directive, MIPS: MIPS NaN Encodings. (line 6)
* '.nocmp' directive, TIC6X: TIC6X Directives. (line 47)
* '.no_pointers' directive, XStormy16: XStormy16 Directives.
(line 14)
* .o: Object. (line 6)
* '.object_arch' directive, ARM: ARM Directives. (line 172)
* '.packed' directive, ARM: ARM Directives. (line 178)
* '.pad' directive, ARM: ARM Directives. (line 183)
* '.param' on HPPA: HPPA Directives. (line 19)
* '.personality' directive, ARM: ARM Directives. (line 188)
* '.personality' directive, TIC6X: TIC6X Directives. (line 55)
* '.personalityindex' directive, ARM: ARM Directives. (line 191)
* '.personalityindex' directive, TIC6X: TIC6X Directives. (line 51)
* '.pool' directive, AArch64: AArch64 Directives. (line 38)
* '.pool' directive, ARM: ARM Directives. (line 195)
* '.quad' directive, s390: s390 Directives. (line 16)
* '.req' directive, AArch64: AArch64 Directives. (line 41)
* '.req' directive, ARM: ARM Directives. (line 198)
* '.require_canonical_reg_names' directive, TILE-Gx: TILE-Gx Directives.
(line 19)
* '.require_canonical_reg_names' directive, TILEPro: TILEPro Directives.
(line 19)
* '.save' directive, ARM: ARM Directives. (line 203)
* '.scomm' directive, TIC6X: TIC6X Directives. (line 58)
* '.secrel32' directive, ARM: ARM Directives. (line 241)
* '.set arch=CPU': MIPS ISA. (line 18)
* '.set at': MIPS Macros. (line 41)
* '.set at=REG': MIPS Macros. (line 35)
* '.set autoextend': MIPS autoextend. (line 6)
* '.set doublefloat': MIPS Floating-Point. (line 12)
* '.set dsp': MIPS ASE Instruction Generation Overrides.
(line 21)
* '.set dspr2': MIPS ASE Instruction Generation Overrides.
(line 26)
* '.set hardfloat': MIPS Floating-Point. (line 6)
* '.set insn32': MIPS assembly options.
(line 18)
* '.set macro': MIPS Macros. (line 30)
* '.set mcu': MIPS ASE Instruction Generation Overrides.
(line 36)
* '.set mdmx': MIPS ASE Instruction Generation Overrides.
(line 16)
* '.set mips3d': MIPS ASE Instruction Generation Overrides.
(line 6)
* '.set mipsN': MIPS ISA. (line 6)
* '.set msa': MIPS ASE Instruction Generation Overrides.
(line 41)
* '.set mt': MIPS ASE Instruction Generation Overrides.
(line 31)
* '.set noat': MIPS Macros. (line 41)
* '.set noautoextend': MIPS autoextend. (line 6)
* '.set nodsp': MIPS ASE Instruction Generation Overrides.
(line 21)
* '.set nodspr2': MIPS ASE Instruction Generation Overrides.
(line 26)
* '.set noinsn32': MIPS assembly options.
(line 18)
* '.set nomacro': MIPS Macros. (line 30)
* '.set nomcu': MIPS ASE Instruction Generation Overrides.
(line 36)
* '.set nomdmx': MIPS ASE Instruction Generation Overrides.
(line 16)
* '.set nomips3d': MIPS ASE Instruction Generation Overrides.
(line 6)
* '.set nomsa': MIPS ASE Instruction Generation Overrides.
(line 41)
* '.set nomt': MIPS ASE Instruction Generation Overrides.
(line 31)
* '.set nosmartmips': MIPS ASE Instruction Generation Overrides.
(line 11)
* '.set nosym32': MIPS Symbol Sizes. (line 6)
* '.set novirt': MIPS ASE Instruction Generation Overrides.
(line 46)
* '.set noxpa': MIPS ASE Instruction Generation Overrides.
(line 51)
* '.set pop': MIPS Option Stack. (line 6)
* '.set push': MIPS Option Stack. (line 6)
* '.set singlefloat': MIPS Floating-Point. (line 12)
* '.set smartmips': MIPS ASE Instruction Generation Overrides.
(line 11)
* '.set softfloat': MIPS Floating-Point. (line 6)
* '.set sym32': MIPS Symbol Sizes. (line 6)
* '.set virt': MIPS ASE Instruction Generation Overrides.
(line 46)
* '.set xpa': MIPS ASE Instruction Generation Overrides.
(line 51)
* '.setfp' directive, ARM: ARM Directives. (line 227)
* '.short' directive, s390: s390 Directives. (line 16)
* '.syntax' directive, ARM: ARM Directives. (line 246)
* '.thumb' directive, ARM: ARM Directives. (line 250)
* '.thumb_func' directive, ARM: ARM Directives. (line 253)
* '.thumb_set' directive, ARM: ARM Directives. (line 264)
* '.tlsdescseq' directive, ARM: ARM Directives. (line 271)
* '.unreq' directive, AArch64: AArch64 Directives. (line 46)
* '.unreq' directive, ARM: ARM Directives. (line 276)
* '.unwind_raw' directive, ARM: ARM Directives. (line 287)
* '.v850' directive, V850: V850 Directives. (line 14)
* '.v850e' directive, V850: V850 Directives. (line 20)
* '.v850e1' directive, V850: V850 Directives. (line 26)
* '.v850e2' directive, V850: V850 Directives. (line 32)
* '.v850e2v3' directive, V850: V850 Directives. (line 38)
* '.v850e2v4' directive, V850: V850 Directives. (line 44)
* '.v850e3v5' directive, V850: V850 Directives. (line 50)
* '.vsave' directive, ARM: ARM Directives. (line 294)
* .z8001: Z8000 Directives. (line 11)
* .z8002: Z8000 Directives. (line 15)
* 16-bit code, i386: i386-16bit. (line 6)
* '16bit_pointers' directive, XStormy16: XStormy16 Directives.
(line 6)
* '16byte' directive, Nios II: Nios II Directives. (line 28)
* '2byte' directive, ARC: ARC Directives. (line 9)
* '2byte' directive, Nios II: Nios II Directives. (line 19)
* '32bit_pointers' directive, XStormy16: XStormy16 Directives.
(line 10)
* '3byte' directive, ARC: ARC Directives. (line 12)
* 3DNow!, i386: i386-SIMD. (line 6)
* 3DNow!, x86-64: i386-SIMD. (line 6)
* 430 support: MSP430-Dependent. (line 6)
* '4byte' directive, ARC: ARC Directives. (line 15)
* '4byte' directive, Nios II: Nios II Directives. (line 22)
* '8byte' directive, Nios II: Nios II Directives. (line 25)
* ':' (label): Statements. (line 31)
* '@hi' pseudo-op, XStormy16: XStormy16 Opcodes. (line 21)
* '@lo' pseudo-op, XStormy16: XStormy16 Opcodes. (line 10)
* @word modifier, D10V: D10V-Word. (line 6)
* '\"' (doublequote character): Strings. (line 43)
* '\b' (backspace character): Strings. (line 15)
* '\DDD' (octal character code): Strings. (line 30)
* '\f' (formfeed character): Strings. (line 18)
* '\n' (newline character): Strings. (line 21)
* '\r' (carriage return character): Strings. (line 24)
* '\t' (tab): Strings. (line 27)
* '\XD...' (hex character code): Strings. (line 36)
* '\\' ('\' character): Strings. (line 40)
* _ opcode prefix: Xtensa Opcodes. (line 9)
* a.out: Object. (line 6)
* 'a.out' symbol attributes: a.out Symbols. (line 6)
* AArch64 floating point (IEEE): AArch64 Floating Point.
(line 6)
* AArch64 immediate character: AArch64-Chars. (line 13)
* AArch64 line comment character: AArch64-Chars. (line 6)
* AArch64 line separator: AArch64-Chars. (line 10)
* AArch64 machine directives: AArch64 Directives. (line 6)
* AArch64 opcodes: AArch64 Opcodes. (line 6)
* AArch64 options (none): AArch64 Options. (line 6)
* AArch64 register names: AArch64-Regs. (line 6)
* AArch64 relocations: AArch64-Relocations. (line 6)
* AArch64 support: AArch64-Dependent. (line 6)
* ABI options, SH64: SH64 Options. (line 25)
* 'abort' directive: Abort. (line 6)
* 'ABORT' directive: ABORT (COFF). (line 6)
* absolute section: Ld Sections. (line 29)
* 'absolute-literals' directive: Absolute Literals Directive.
(line 6)
* 'ADDI' instructions, relaxation: Xtensa Immediate Relaxation.
(line 43)
* addition, permitted arguments: Infix Ops. (line 45)
* addresses: Expressions. (line 6)
* addresses, format of: Secs Background. (line 65)
* addressing modes, D10V: D10V-Addressing. (line 6)
* addressing modes, D30V: D30V-Addressing. (line 6)
* addressing modes, H8/300: H8/300-Addressing. (line 6)
* addressing modes, M680x0: M68K-Syntax. (line 21)
* addressing modes, M68HC11: M68HC11-Syntax. (line 29)
* addressing modes, SH: SH-Addressing. (line 6)
* addressing modes, SH64: SH64-Addressing. (line 6)
* addressing modes, XGATE: XGATE-Syntax. (line 28)
* addressing modes, Z8000: Z8000-Addressing. (line 6)
* 'ADR reg,<label>' pseudo op, ARM: ARM Opcodes. (line 25)
* 'ADRL reg,<label>' pseudo op, ARM: ARM Opcodes. (line 35)
* ADRP, ADD, LDR/STR group relocations, AArch64: AArch64-Relocations.
(line 14)
* advancing location counter: Org. (line 6)
* 'align' directive: Align. (line 6)
* 'align' directive, Nios II: Nios II Directives. (line 6)
* 'align' directive, SPARC: Sparc-Directives. (line 9)
* 'align' directive, TIC54X: TIC54X-Directives. (line 6)
* aligned instruction bundle: Bundle directives. (line 6)
* alignment for NEON instructions: ARM-Neon-Alignment. (line 6)
* alignment of branch targets: Xtensa Automatic Alignment.
(line 6)
* alignment of 'LOOP' instructions: Xtensa Automatic Alignment.
(line 6)
* Alpha floating point (IEEE): Alpha Floating Point.
(line 6)
* Alpha line comment character: Alpha-Chars. (line 6)
* Alpha line separator: Alpha-Chars. (line 11)
* Alpha notes: Alpha Notes. (line 6)
* Alpha options: Alpha Options. (line 6)
* Alpha registers: Alpha-Regs. (line 6)
* Alpha relocations: Alpha-Relocs. (line 6)
* Alpha support: Alpha-Dependent. (line 6)
* Alpha Syntax: Alpha Options. (line 60)
* Alpha-only directives: Alpha Directives. (line 9)
* Altera Nios II support: NiosII-Dependent. (line 6)
* altered difference tables: Word. (line 12)
* alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6)
* ARC floating point (IEEE): ARC Floating Point. (line 6)
* ARC line comment character: ARC-Chars. (line 6)
* ARC line separator: ARC-Chars. (line 12)
* ARC machine directives: ARC Directives. (line 6)
* ARC opcodes: ARC Opcodes. (line 6)
* ARC options (none): ARC Options. (line 6)
* ARC register names: ARC-Regs. (line 6)
* ARC support: ARC-Dependent. (line 6)
* 'arc5' arc5, ARC: ARC Options. (line 10)
* 'arc6' arc6, ARC: ARC Options. (line 13)
* 'arc7' arc7, ARC: ARC Options. (line 21)
* 'arc8' arc8, ARC: ARC Options. (line 24)
* arch directive, i386: i386-Arch. (line 6)
* 'arch' directive, M680x0: M68K-Directives. (line 22)
* 'arch' directive, MSP 430: MSP430 Directives. (line 18)
* arch directive, x86-64: i386-Arch. (line 6)
* architecture options, i960: Options-i960. (line 6)
* architecture options, IP2022: IP2K-Opts. (line 9)
* architecture options, IP2K: IP2K-Opts. (line 14)
* architecture options, M16C: M32C-Opts. (line 12)
* architecture options, M32C: M32C-Opts. (line 9)
* architecture options, M32R: M32R-Opts. (line 21)
* architecture options, M32R2: M32R-Opts. (line 17)
* architecture options, M32RX: M32R-Opts. (line 9)
* architecture options, M680x0: M68K-Opts. (line 99)
* Architecture variant option, CRIS: CRIS-Opts. (line 34)
* architectures, Meta: Meta Options. (line 6)
* architectures, PowerPC: PowerPC-Opts. (line 6)
* architectures, SCORE: SCORE-Opts. (line 6)
* architectures, SPARC: Sparc-Opts. (line 6)
* arguments for addition: Infix Ops. (line 45)
* arguments for subtraction: Infix Ops. (line 50)
* arguments in expressions: Arguments. (line 6)
* arithmetic functions: Operators. (line 6)
* arithmetic operands: Arguments. (line 6)
* ARM data relocations: ARM-Relocations. (line 6)
* ARM floating point (IEEE): ARM Floating Point. (line 6)
* ARM identifiers: ARM-Chars. (line 19)
* ARM immediate character: ARM-Chars. (line 17)
* ARM line comment character: ARM-Chars. (line 6)
* ARM line separator: ARM-Chars. (line 14)
* ARM machine directives: ARM Directives. (line 6)
* ARM opcodes: ARM Opcodes. (line 6)
* ARM options (none): ARM Options. (line 6)
* ARM register names: ARM-Regs. (line 6)
* ARM support: ARM-Dependent. (line 6)
* 'ascii' directive: Ascii. (line 6)
* 'asciz' directive: Asciz. (line 6)
* 'asg' directive, TIC54X: TIC54X-Directives. (line 18)
* assembler bugs, reporting: Bug Reporting. (line 6)
* assembler crash: Bug Criteria. (line 9)
* assembler directive .3byte, RX: RX-Directives. (line 9)
* assembler directive .arch, CRIS: CRIS-Pseudos. (line 50)
* assembler directive .dword, CRIS: CRIS-Pseudos. (line 12)
* assembler directive .far, M68HC11: M68HC11-Directives. (line 20)
* assembler directive .fetchalign, RX: RX-Directives. (line 13)
* assembler directive .interrupt, M68HC11: M68HC11-Directives.
(line 26)
* assembler directive .mode, M68HC11: M68HC11-Directives. (line 16)
* assembler directive .relax, M68HC11: M68HC11-Directives. (line 10)
* assembler directive .syntax, CRIS: CRIS-Pseudos. (line 18)
* assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31)
* assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 137)
* assembler directive BYTE, MMIX: MMIX-Pseudos. (line 101)
* assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 137)
* assembler directive GREG, MMIX: MMIX-Pseudos. (line 53)
* assembler directive IS, MMIX: MMIX-Pseudos. (line 44)
* assembler directive LOC, MMIX: MMIX-Pseudos. (line 7)
* assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 29)
* assembler directive OCTA, MMIX: MMIX-Pseudos. (line 113)
* assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 125)
* assembler directive TETRA, MMIX: MMIX-Pseudos. (line 113)
* assembler directive WYDE, MMIX: MMIX-Pseudos. (line 113)
* assembler directives, CRIS: CRIS-Pseudos. (line 6)
* assembler directives, M68HC11: M68HC11-Directives. (line 6)
* assembler directives, M68HC12: M68HC11-Directives. (line 6)
* assembler directives, MMIX: MMIX-Pseudos. (line 6)
* assembler directives, RL78: RL78-Directives. (line 6)
* assembler directives, RX: RX-Directives. (line 6)
* assembler directives, XGATE: XGATE-Directives. (line 6)
* assembler internal logic error: As Sections. (line 13)
* assembler version: v. (line 6)
* assembler, and linker: Secs Background. (line 10)
* assembly listings, enabling: a. (line 6)
* assigning values to symbols: Setting Symbols. (line 6)
* assigning values to symbols <1>: Equ. (line 6)
* 'at' register, MIPS: MIPS Macros. (line 35)
* 'atmp' directive, i860: Directives-i860. (line 16)
* attributes, symbol: Symbol Attributes. (line 6)
* att_syntax pseudo op, i386: i386-Variations. (line 6)
* att_syntax pseudo op, x86-64: i386-Variations. (line 6)
* auxiliary attributes, COFF symbols: COFF Symbols. (line 19)
* auxiliary symbol information, COFF: Dim. (line 6)
* AVR line comment character: AVR-Chars. (line 6)
* AVR line separator: AVR-Chars. (line 14)
* AVR modifiers: AVR-Modifiers. (line 6)
* AVR opcode summary: AVR Opcodes. (line 6)
* AVR options (none): AVR Options. (line 6)
* AVR register names: AVR-Regs. (line 6)
* AVR support: AVR-Dependent. (line 6)
* 'A_DIR' environment variable, TIC54X: TIC54X-Env. (line 6)
* backslash ('\\'): Strings. (line 40)
* backspace ('\b'): Strings. (line 15)
* 'balign' directive: Balign. (line 6)
* 'balignl' directive: Balign. (line 27)
* 'balignw' directive: Balign. (line 27)
* 'bes' directive, TIC54X: TIC54X-Directives. (line 194)
* big endian output, MIPS: Overview. (line 748)
* big endian output, PJ: Overview. (line 655)
* big-endian output, MIPS: MIPS Options. (line 13)
* big-endian output, TIC6X: TIC6X Options. (line 46)
* bignums: Bignums. (line 6)
* binary constants, TIC54X: TIC54X-Constants. (line 8)
* binary files, including: Incbin. (line 6)
* binary integers: Integers. (line 6)
* bit names, IA-64: IA-64-Bits. (line 6)
* bitfields, not supported on VAX: VAX-no. (line 6)
* Blackfin directives: Blackfin Directives. (line 6)
* Blackfin options (none): Blackfin Options. (line 6)
* Blackfin support: Blackfin-Dependent. (line 6)
* Blackfin syntax: Blackfin Syntax. (line 6)
* block: Z8000 Directives. (line 54)
* BMI, i386: i386-BMI. (line 6)
* BMI, x86-64: i386-BMI. (line 6)
* branch improvement, M680x0: M68K-Branch. (line 6)
* branch improvement, M68HC11: M68HC11-Branch. (line 6)
* branch improvement, VAX: VAX-branch. (line 6)
* branch instructions, relaxation: Xtensa Branch Relaxation.
(line 6)
* branch recording, i960: Options-i960. (line 22)
* branch statistics table, i960: Options-i960. (line 40)
* branch target alignment: Xtensa Automatic Alignment.
(line 6)
* 'break' directive, TIC54X: TIC54X-Directives. (line 141)
* BSD syntax: PDP-11-Syntax. (line 6)
* 'bss' directive, i960: Directives-i960. (line 6)
* 'bss' directive, TIC54X: TIC54X-Directives. (line 27)
* bss section: Ld Sections. (line 20)
* bss section <1>: bss. (line 6)
* bug criteria: Bug Criteria. (line 6)
* bug reports: Bug Reporting. (line 6)
* bugs in assembler: Reporting Bugs. (line 6)
* Built-in symbols, CRIS: CRIS-Symbols. (line 6)
* builtin math functions, TIC54X: TIC54X-Builtins. (line 6)
* builtin subsym functions, TIC54X: TIC54X-Macros. (line 16)
* bundle: Bundle directives. (line 6)
* bundle-locked: Bundle directives. (line 36)
* 'bundle_align_mode' directive: Bundle directives. (line 6)
* 'bundle_lock' directive: Bundle directives. (line 28)
* 'bundle_unlock' directive: Bundle directives. (line 28)
* bus lock prefixes, i386: i386-Prefixes. (line 36)
* bval: Z8000 Directives. (line 30)
* 'byte' directive: Byte. (line 6)
* 'byte' directive, TIC54X: TIC54X-Directives. (line 34)
* 'C54XDSP_DIR' environment variable, TIC54X: TIC54X-Env. (line 6)
* 'call' directive, Nios II: Nios II Relocations. (line 38)
* call instructions, i386: i386-Mnemonics. (line 55)
* call instructions, relaxation: Xtensa Call Relaxation.
(line 6)
* call instructions, x86-64: i386-Mnemonics. (line 55)
* 'callj', i960 pseudo-opcode: callj-i960. (line 6)
* 'call_hiadj' directive, Nios II: Nios II Relocations. (line 38)
* 'call_lo' directive, Nios II: Nios II Relocations. (line 38)
* carriage return ('\r'): Strings. (line 24)
* case sensitivity, Z80: Z80-Case. (line 6)
* 'cfi_endproc' directive: CFI directives. (line 26)
* 'cfi_sections' directive: CFI directives. (line 6)
* 'cfi_startproc' directive: CFI directives. (line 16)
* 'char' directive, TIC54X: TIC54X-Directives. (line 34)
* character constant, Z80: Z80-Chars. (line 20)
* character constants: Characters. (line 6)
* character escape codes: Strings. (line 15)
* character escapes, Z80: Z80-Chars. (line 18)
* character, single: Chars. (line 6)
* characters used in symbols: Symbol Intro. (line 6)
* 'clink' directive, TIC54X: TIC54X-Directives. (line 43)
* 'code16' directive, i386: i386-16bit. (line 6)
* 'code16gcc' directive, i386: i386-16bit. (line 6)
* 'code32' directive, i386: i386-16bit. (line 6)
* 'code64' directive, i386: i386-16bit. (line 6)
* 'code64' directive, x86-64: i386-16bit. (line 6)
* COFF auxiliary symbol information: Dim. (line 6)
* COFF structure debugging: Tag. (line 6)
* COFF symbol attributes: COFF Symbols. (line 6)
* COFF symbol descriptor: Desc. (line 6)
* COFF symbol storage class: Scl. (line 6)
* COFF symbol type: Type. (line 11)
* COFF symbols, debugging: Def. (line 6)
* COFF value attribute: Val. (line 6)
* COMDAT: Linkonce. (line 6)
* 'comm' directive: Comm. (line 6)
* command line conventions: Command Line. (line 6)
* command line options, V850: V850 Options. (line 9)
* command-line options ignored, VAX: VAX-Opts. (line 6)
* comment character, XStormy16: XStormy16-Chars. (line 11)
* comments: Comments. (line 6)
* comments, M680x0: M68K-Chars. (line 6)
* comments, removed by preprocessor: Preprocessing. (line 11)
* 'common' directive, SPARC: Sparc-Directives. (line 12)
* common sections: Linkonce. (line 6)
* common variable storage: bss. (line 6)
* compare and jump expansions, i960: Compare-and-branch-i960.
(line 13)
* compare/branch instructions, i960: Compare-and-branch-i960.
(line 6)
* comparison expressions: Infix Ops. (line 56)
* conditional assembly: If. (line 6)
* constant, single character: Chars. (line 6)
* constants: Constants. (line 6)
* constants, bignum: Bignums. (line 6)
* constants, character: Characters. (line 6)
* constants, converted by preprocessor: Preprocessing. (line 14)
* constants, floating point: Flonums. (line 6)
* constants, integer: Integers. (line 6)
* constants, number: Numbers. (line 6)
* constants, Sparc: Sparc-Constants. (line 6)
* constants, string: Strings. (line 6)
* constants, TIC54X: TIC54X-Constants. (line 6)
* conversion instructions, i386: i386-Mnemonics. (line 36)
* conversion instructions, x86-64: i386-Mnemonics. (line 36)
* coprocessor wait, i386: i386-Prefixes. (line 40)
* 'copy' directive, TIC54X: TIC54X-Directives. (line 52)
* 'cpu' directive, M680x0: M68K-Directives. (line 30)
* 'cpu' directive, MSP 430: MSP430 Directives. (line 22)
* CR16 line comment character: CR16-Chars. (line 6)
* CR16 line separator: CR16-Chars. (line 12)
* CR16 Operand Qualifiers: CR16 Operand Qualifiers.
(line 6)
* CR16 support: CR16-Dependent. (line 6)
* crash of assembler: Bug Criteria. (line 9)
* CRIS '--emulation=crisaout' command line option: CRIS-Opts. (line 9)
* CRIS '--emulation=criself' command line option: CRIS-Opts. (line 9)
* CRIS '--march=ARCHITECTURE' command line option: CRIS-Opts. (line 34)
* CRIS '--mul-bug-abort' command line option: CRIS-Opts. (line 63)
* CRIS '--no-mul-bug-abort' command line option: CRIS-Opts. (line 63)
* CRIS '--no-underscore' command line option: CRIS-Opts. (line 15)
* CRIS '--pic' command line option: CRIS-Opts. (line 27)
* CRIS '--underscore' command line option: CRIS-Opts. (line 15)
* CRIS '-N' command line option: CRIS-Opts. (line 59)
* CRIS architecture variant option: CRIS-Opts. (line 34)
* CRIS assembler directive .arch: CRIS-Pseudos. (line 50)
* CRIS assembler directive .dword: CRIS-Pseudos. (line 12)
* CRIS assembler directive .syntax: CRIS-Pseudos. (line 18)
* CRIS assembler directives: CRIS-Pseudos. (line 6)
* CRIS built-in symbols: CRIS-Symbols. (line 6)
* CRIS instruction expansion: CRIS-Expand. (line 6)
* CRIS line comment characters: CRIS-Chars. (line 6)
* CRIS options: CRIS-Opts. (line 6)
* CRIS position-independent code: CRIS-Opts. (line 27)
* CRIS pseudo-op .arch: CRIS-Pseudos. (line 50)
* CRIS pseudo-op .dword: CRIS-Pseudos. (line 12)
* CRIS pseudo-op .syntax: CRIS-Pseudos. (line 18)
* CRIS pseudo-ops: CRIS-Pseudos. (line 6)
* CRIS register names: CRIS-Regs. (line 6)
* CRIS support: CRIS-Dependent. (line 6)
* CRIS symbols in position-independent code: CRIS-Pic. (line 6)
* 'ctbp' register, V850: V850-Regs. (line 90)
* 'ctoff' pseudo-op, V850: V850 Opcodes. (line 110)
* 'ctpc' register, V850: V850-Regs. (line 82)
* 'ctpsw' register, V850: V850-Regs. (line 84)
* current address: Dot. (line 6)
* current address, advancing: Org. (line 6)
* 'c_mode' directive, TIC54X: TIC54X-Directives. (line 49)
* D10V @word modifier: D10V-Word. (line 6)
* D10V addressing modes: D10V-Addressing. (line 6)
* D10V floating point: D10V-Float. (line 6)
* D10V line comment character: D10V-Chars. (line 6)
* D10V opcode summary: D10V-Opcodes. (line 6)
* D10V optimization: Overview. (line 521)
* D10V options: D10V-Opts. (line 6)
* D10V registers: D10V-Regs. (line 6)
* D10V size modifiers: D10V-Size. (line 6)
* D10V sub-instruction ordering: D10V-Chars. (line 14)
* D10V sub-instructions: D10V-Subs. (line 6)
* D10V support: D10V-Dependent. (line 6)
* D10V syntax: D10V-Syntax. (line 6)
* D30V addressing modes: D30V-Addressing. (line 6)
* D30V floating point: D30V-Float. (line 6)
* D30V Guarded Execution: D30V-Guarded. (line 6)
* D30V line comment character: D30V-Chars. (line 6)
* D30V nops: Overview. (line 529)
* D30V nops after 32-bit multiply: Overview. (line 532)
* D30V opcode summary: D30V-Opcodes. (line 6)
* D30V optimization: Overview. (line 526)
* D30V options: D30V-Opts. (line 6)
* D30V registers: D30V-Regs. (line 6)
* D30V size modifiers: D30V-Size. (line 6)
* D30V sub-instruction ordering: D30V-Chars. (line 14)
* D30V sub-instructions: D30V-Subs. (line 6)
* D30V support: D30V-Dependent. (line 6)
* D30V syntax: D30V-Syntax. (line 6)
* data alignment on SPARC: Sparc-Aligned-Data. (line 6)
* data and text sections, joining: R. (line 6)
* 'data' directive: Data. (line 6)
* 'data' directive, TIC54X: TIC54X-Directives. (line 59)
* data relocations, ARM: ARM-Relocations. (line 6)
* data section: Ld Sections. (line 9)
* 'data1' directive, M680x0: M68K-Directives. (line 9)
* 'data2' directive, M680x0: M68K-Directives. (line 12)
* datalabel, SH64: SH64-Addressing. (line 16)
* 'dbpc' register, V850: V850-Regs. (line 86)
* 'dbpsw' register, V850: V850-Regs. (line 88)
* debuggers, and symbol order: Symbols. (line 10)
* debugging COFF symbols: Def. (line 6)
* DEC syntax: PDP-11-Syntax. (line 6)
* decimal integers: Integers. (line 12)
* 'def' directive: Def. (line 6)
* 'def' directive, TIC54X: TIC54X-Directives. (line 101)
* density instructions: Density Instructions.
(line 6)
* dependency tracking: MD. (line 6)
* deprecated directives: Deprecated. (line 6)
* 'desc' directive: Desc. (line 6)
* descriptor, of 'a.out' symbol: Symbol Desc. (line 6)
* 'dfloat' directive, VAX: VAX-directives. (line 9)
* difference tables altered: Word. (line 12)
* difference tables, warning: K. (line 6)
* differences, mmixal: MMIX-mmixal. (line 6)
* 'dim' directive: Dim. (line 6)
* directives and instructions: Statements. (line 20)
* directives for PowerPC: PowerPC-Pseudo. (line 6)
* directives for SCORE: SCORE-Pseudo. (line 6)
* directives, Blackfin: Blackfin Directives. (line 6)
* directives, M32R: M32R-Directives. (line 6)
* directives, M680x0: M68K-Directives. (line 6)
* directives, machine independent: Pseudo Ops. (line 6)
* directives, Xtensa: Xtensa Directives. (line 6)
* directives, Z8000: Z8000 Directives. (line 6)
* Disable floating-point instructions: MIPS Floating-Point. (line 6)
* Disable single-precision floating-point operations: MIPS Floating-Point.
(line 12)
* displacement sizing character, VAX: VAX-operands. (line 12)
* dollar local symbols: Symbol Names. (line 109)
* dot (symbol): Dot. (line 6)
* 'double' directive: Double. (line 6)
* 'double' directive, i386: i386-Float. (line 14)
* 'double' directive, M680x0: M68K-Float. (line 14)
* 'double' directive, M68HC11: M68HC11-Float. (line 14)
* 'double' directive, RX: RX-Float. (line 11)
* 'double' directive, TIC54X: TIC54X-Directives. (line 62)
* 'double' directive, VAX: VAX-float. (line 15)
* 'double' directive, x86-64: i386-Float. (line 14)
* 'double' directive, XGATE: XGATE-Float. (line 13)
* doublequote ('\"'): Strings. (line 43)
* 'drlist' directive, TIC54X: TIC54X-Directives. (line 71)
* 'drnolist' directive, TIC54X: TIC54X-Directives. (line 71)
* 'dual' directive, i860: Directives-i860. (line 6)
* 'dword' directive, Nios II: Nios II Directives. (line 16)
* 'EB' command line option, Nios II: Nios II Options. (line 22)
* 'ecr' register, V850: V850-Regs. (line 78)
* eight-byte integer: Quad. (line 9)
* 'eipc' register, V850: V850-Regs. (line 70)
* 'eipsw' register, V850: V850-Regs. (line 72)
* 'eject' directive: Eject. (line 6)
* 'EL' command line option, Nios II: Nios II Options. (line 25)
* ELF symbol type: Type. (line 22)
* 'else' directive: Else. (line 6)
* 'elseif' directive: Elseif. (line 6)
* empty expressions: Empty Exprs. (line 6)
* 'emsg' directive, TIC54X: TIC54X-Directives. (line 75)
* emulation: Overview. (line 930)
* encoding options, i386: i386-Mnemonics. (line 31)
* encoding options, x86-64: i386-Mnemonics. (line 31)
* 'end' directive: End. (line 6)
* 'enddual' directive, i860: Directives-i860. (line 11)
* 'endef' directive: Endef. (line 6)
* 'endfunc' directive: Endfunc. (line 6)
* endianness, MIPS: Overview. (line 748)
* endianness, PJ: Overview. (line 655)
* 'endif' directive: Endif. (line 6)
* 'endloop' directive, TIC54X: TIC54X-Directives. (line 141)
* 'endm' directive: Macro. (line 137)
* 'endm' directive, TIC54X: TIC54X-Directives. (line 151)
* 'endstruct' directive, TIC54X: TIC54X-Directives. (line 214)
* 'endunion' directive, TIC54X: TIC54X-Directives. (line 248)
* environment settings, TIC54X: TIC54X-Env. (line 6)
* EOF, newline must precede: Statements. (line 14)
* 'ep' register, V850: V850-Regs. (line 66)
* Epiphany line comment character: Epiphany-Chars. (line 6)
* Epiphany line separator: Epiphany-Chars. (line 14)
* Epiphany options: Epiphany Options. (line 6)
* Epiphany support: Epiphany-Dependent. (line 6)
* 'equ' directive: Equ. (line 6)
* 'equ' directive, TIC54X: TIC54X-Directives. (line 189)
* 'equiv' directive: Equiv. (line 6)
* 'eqv' directive: Eqv. (line 6)
* 'err' directive: Err. (line 6)
* error directive: Error. (line 6)
* error messages: Errors. (line 6)
* error on valid input: Bug Criteria. (line 12)
* errors, caused by warnings: W. (line 16)
* errors, continuing after: Z. (line 6)
* ESA/390 floating point (IEEE): ESA/390 Floating Point.
(line 6)
* ESA/390 support: ESA/390-Dependent. (line 6)
* ESA/390 Syntax: ESA/390 Options. (line 7)
* ESA/390-only directives: ESA/390 Directives. (line 12)
* escape codes, character: Strings. (line 15)
* 'eval' directive, TIC54X: TIC54X-Directives. (line 22)
* even: Z8000 Directives. (line 57)
* 'even' directive, M680x0: M68K-Directives. (line 15)
* 'even' directive, TIC54X: TIC54X-Directives. (line 6)
* 'exitm' directive: Macro. (line 140)
* expr (internal section): As Sections. (line 17)
* expression arguments: Arguments. (line 6)
* expressions: Expressions. (line 6)
* expressions, comparison: Infix Ops. (line 56)
* expressions, empty: Empty Exprs. (line 6)
* expressions, integer: Integer Exprs. (line 6)
* 'extAuxRegister' directive, ARC: ARC Directives. (line 18)
* 'extCondCode' directive, ARC: ARC Directives. (line 38)
* 'extCoreRegister' directive, ARC: ARC Directives. (line 50)
* 'extend' directive M680x0: M68K-Float. (line 17)
* 'extend' directive M68HC11: M68HC11-Float. (line 17)
* 'extend' directive XGATE: XGATE-Float. (line 16)
* 'extended' directive, i960: Directives-i960. (line 13)
* 'extern' directive: Extern. (line 6)
* 'extInstruction' directive, ARC: ARC Directives. (line 72)
* 'fail' directive: Fail. (line 6)
* 'far_mode' directive, TIC54X: TIC54X-Directives. (line 80)
* faster processing ('-f'): f. (line 6)
* fatal signal: Bug Criteria. (line 9)
* 'fclist' directive, TIC54X: TIC54X-Directives. (line 85)
* 'fcnolist' directive, TIC54X: TIC54X-Directives. (line 85)
* 'fepc' register, V850: V850-Regs. (line 74)
* 'fepsw' register, V850: V850-Regs. (line 76)
* 'ffloat' directive, VAX: VAX-directives. (line 13)
* 'field' directive, TIC54X: TIC54X-Directives. (line 89)
* 'file' directive: File. (line 6)
* 'file' directive, MSP 430: MSP430 Directives. (line 6)
* file name, logical: File. (line 13)
* files, including: Include. (line 6)
* files, input: Input Files. (line 6)
* 'fill' directive: Fill. (line 6)
* filling memory: Skip. (line 6)
* filling memory <1>: Space. (line 6)
* FLIX syntax: Xtensa Syntax. (line 6)
* 'float' directive: Float. (line 6)
* 'float' directive, i386: i386-Float. (line 14)
* 'float' directive, M680x0: M68K-Float. (line 11)
* 'float' directive, M68HC11: M68HC11-Float. (line 11)
* 'float' directive, RX: RX-Float. (line 8)
* 'float' directive, TIC54X: TIC54X-Directives. (line 62)
* 'float' directive, VAX: VAX-float. (line 15)
* 'float' directive, x86-64: i386-Float. (line 14)
* 'float' directive, XGATE: XGATE-Float. (line 10)
* floating point numbers: Flonums. (line 6)
* floating point numbers (double): Double. (line 6)
* floating point numbers (single): Float. (line 6)
* floating point numbers (single) <1>: Single. (line 6)
* floating point, AArch64 (IEEE): AArch64 Floating Point.
(line 6)
* floating point, Alpha (IEEE): Alpha Floating Point.
(line 6)
* floating point, ARC (IEEE): ARC Floating Point. (line 6)
* floating point, ARM (IEEE): ARM Floating Point. (line 6)
* floating point, D10V: D10V-Float. (line 6)
* floating point, D30V: D30V-Float. (line 6)
* floating point, ESA/390 (IEEE): ESA/390 Floating Point.
(line 6)
* floating point, H8/300 (IEEE): H8/300 Floating Point.
(line 6)
* floating point, HPPA (IEEE): HPPA Floating Point. (line 6)
* floating point, i386: i386-Float. (line 6)
* floating point, i960 (IEEE): Floating Point-i960. (line 6)
* floating point, M680x0: M68K-Float. (line 6)
* floating point, M68HC11: M68HC11-Float. (line 6)
* floating point, MSP 430 (IEEE): MSP430 Floating Point.
(line 6)
* floating point, RX: RX-Float. (line 6)
* floating point, s390: s390 Floating Point. (line 6)
* floating point, SH (IEEE): SH Floating Point. (line 6)
* floating point, SPARC (IEEE): Sparc-Float. (line 6)
* floating point, V850 (IEEE): V850 Floating Point. (line 6)
* floating point, VAX: VAX-float. (line 6)
* floating point, x86-64: i386-Float. (line 6)
* floating point, XGATE: XGATE-Float. (line 6)
* floating point, Z80: Z80 Floating Point. (line 6)
* flonums: Flonums. (line 6)
* format of error messages: Errors. (line 24)
* format of warning messages: Errors. (line 12)
* formfeed ('\f'): Strings. (line 18)
* 'func' directive: Func. (line 6)
* functions, in expressions: Operators. (line 6)
* 'gbr960', i960 postprocessor: Options-i960. (line 40)
* 'gfloat' directive, VAX: VAX-directives. (line 17)
* global: Z8000 Directives. (line 21)
* 'global' directive: Global. (line 6)
* 'global' directive, TIC54X: TIC54X-Directives. (line 101)
* 'got' directive, Nios II: Nios II Relocations. (line 38)
* 'gotoff' directive, Nios II: Nios II Relocations. (line 38)
* 'gotoff_hiadj' directive, Nios II: Nios II Relocations. (line 38)
* 'gotoff_lo' directive, Nios II: Nios II Relocations. (line 38)
* 'got_hiadj' directive, Nios II: Nios II Relocations. (line 38)
* 'got_lo' directive, Nios II: Nios II Relocations. (line 38)
* 'gp' register, MIPS: MIPS Small Data. (line 6)
* 'gp' register, V850: V850-Regs. (line 14)
* 'gprel' directive, Nios II: Nios II Relocations. (line 26)
* grouping data: Sub-Sections. (line 6)
* H8/300 addressing modes: H8/300-Addressing. (line 6)
* H8/300 floating point (IEEE): H8/300 Floating Point.
(line 6)
* H8/300 line comment character: H8/300-Chars. (line 6)
* H8/300 line separator: H8/300-Chars. (line 8)
* H8/300 machine directives (none): H8/300 Directives. (line 6)
* H8/300 opcode summary: H8/300 Opcodes. (line 6)
* H8/300 options: H8/300 Options. (line 6)
* H8/300 registers: H8/300-Regs. (line 6)
* H8/300 size suffixes: H8/300 Opcodes. (line 160)
* H8/300 support: H8/300-Dependent. (line 6)
* H8/300H, assembling for: H8/300 Directives. (line 8)
* 'half' directive, ARC: ARC Directives. (line 144)
* 'half' directive, Nios II: Nios II Directives. (line 10)
* 'half' directive, SPARC: Sparc-Directives. (line 17)
* 'half' directive, TIC54X: TIC54X-Directives. (line 109)
* hex character code ('\XD...'): Strings. (line 36)
* hexadecimal integers: Integers. (line 15)
* hexadecimal prefix, Z80: Z80-Chars. (line 15)
* 'hfloat' directive, VAX: VAX-directives. (line 21)
* 'hi' directive, Nios II: Nios II Relocations. (line 20)
* 'hi' pseudo-op, V850: V850 Opcodes. (line 33)
* 'hi0' pseudo-op, V850: V850 Opcodes. (line 10)
* 'hiadj' directive, Nios II: Nios II Relocations. (line 6)
* 'hidden' directive: Hidden. (line 6)
* 'high' directive, M32R: M32R-Directives. (line 18)
* 'hilo' pseudo-op, V850: V850 Opcodes. (line 55)
* HPPA directives not supported: HPPA Directives. (line 11)
* HPPA floating point (IEEE): HPPA Floating Point. (line 6)
* HPPA Syntax: HPPA Options. (line 7)
* HPPA-only directives: HPPA Directives. (line 24)
* 'hword' directive: hword. (line 6)
* i370 support: ESA/390-Dependent. (line 6)
* i386 16-bit code: i386-16bit. (line 6)
* i386 arch directive: i386-Arch. (line 6)
* i386 att_syntax pseudo op: i386-Variations. (line 6)
* i386 conversion instructions: i386-Mnemonics. (line 36)
* i386 floating point: i386-Float. (line 6)
* i386 immediate operands: i386-Variations. (line 15)
* i386 instruction naming: i386-Mnemonics. (line 6)
* i386 instruction prefixes: i386-Prefixes. (line 6)
* i386 intel_syntax pseudo op: i386-Variations. (line 6)
* i386 jump optimization: i386-Jumps. (line 6)
* i386 jump, call, return: i386-Variations. (line 40)
* i386 jump/call operands: i386-Variations. (line 15)
* i386 line comment character: i386-Chars. (line 6)
* i386 line separator: i386-Chars. (line 18)
* i386 memory references: i386-Memory. (line 6)
* i386 mnemonic compatibility: i386-Mnemonics. (line 61)
* i386 'mul', 'imul' instructions: i386-Notes. (line 6)
* i386 options: i386-Options. (line 6)
* i386 register operands: i386-Variations. (line 15)
* i386 registers: i386-Regs. (line 6)
* i386 sections: i386-Variations. (line 46)
* i386 size suffixes: i386-Variations. (line 28)
* i386 source, destination operands: i386-Variations. (line 21)
* i386 support: i386-Dependent. (line 6)
* i386 syntax compatibility: i386-Variations. (line 6)
* i80386 support: i386-Dependent. (line 6)
* i860 line comment character: i860-Chars. (line 6)
* i860 line separator: i860-Chars. (line 14)
* i860 machine directives: Directives-i860. (line 6)
* i860 opcodes: Opcodes for i860. (line 6)
* i860 support: i860-Dependent. (line 6)
* i960 architecture options: Options-i960. (line 6)
* i960 branch recording: Options-i960. (line 22)
* i960 'callj' pseudo-opcode: callj-i960. (line 6)
* i960 compare and jump expansions: Compare-and-branch-i960.
(line 13)
* i960 compare/branch instructions: Compare-and-branch-i960.
(line 6)
* i960 floating point (IEEE): Floating Point-i960. (line 6)
* i960 line comment character: i960-Chars. (line 6)
* i960 line separator: i960-Chars. (line 14)
* i960 machine directives: Directives-i960. (line 6)
* i960 opcodes: Opcodes for i960. (line 6)
* i960 options: Options-i960. (line 6)
* i960 support: i960-Dependent. (line 6)
* IA-64 line comment character: IA-64-Chars. (line 6)
* IA-64 line separator: IA-64-Chars. (line 8)
* IA-64 options: IA-64 Options. (line 6)
* IA-64 Processor-status-Register bit names: IA-64-Bits. (line 6)
* IA-64 registers: IA-64-Regs. (line 6)
* IA-64 relocations: IA-64-Relocs. (line 6)
* IA-64 support: IA-64-Dependent. (line 6)
* IA-64 Syntax: IA-64 Options. (line 85)
* 'ident' directive: Ident. (line 6)
* identifiers, ARM: ARM-Chars. (line 19)
* identifiers, MSP 430: MSP430-Chars. (line 17)
* 'if' directive: If. (line 6)
* 'ifb' directive: If. (line 21)
* 'ifc' directive: If. (line 25)
* 'ifdef' directive: If. (line 16)
* 'ifeq' directive: If. (line 33)
* 'ifeqs' directive: If. (line 36)
* 'ifge' directive: If. (line 40)
* 'ifgt' directive: If. (line 44)
* 'ifle' directive: If. (line 48)
* 'iflt' directive: If. (line 52)
* 'ifnb' directive: If. (line 56)
* 'ifnc' directive: If. (line 61)
* 'ifndef' directive: If. (line 65)
* 'ifne' directive: If. (line 72)
* 'ifnes' directive: If. (line 76)
* 'ifnotdef' directive: If. (line 65)
* immediate character, AArch64: AArch64-Chars. (line 13)
* immediate character, ARM: ARM-Chars. (line 17)
* immediate character, M680x0: M68K-Chars. (line 13)
* immediate character, VAX: VAX-operands. (line 6)
* immediate fields, relaxation: Xtensa Immediate Relaxation.
(line 6)
* immediate operands, i386: i386-Variations. (line 15)
* immediate operands, x86-64: i386-Variations. (line 15)
* 'imul' instruction, i386: i386-Notes. (line 6)
* 'imul' instruction, x86-64: i386-Notes. (line 6)
* 'incbin' directive: Incbin. (line 6)
* 'include' directive: Include. (line 6)
* 'include' directive search path: I. (line 6)
* indirect character, VAX: VAX-operands. (line 9)
* infix operators: Infix Ops. (line 6)
* inhibiting interrupts, i386: i386-Prefixes. (line 36)
* input: Input Files. (line 6)
* input file linenumbers: Input Files. (line 35)
* instruction aliases, s390: s390 Aliases. (line 6)
* instruction bundle: Bundle directives. (line 6)
* instruction expansion, CRIS: CRIS-Expand. (line 6)
* instruction expansion, MMIX: MMIX-Expand. (line 6)
* instruction formats, s390: s390 Formats. (line 6)
* instruction marker, s390: s390 Instruction Marker.
(line 6)
* instruction mnemonics, s390: s390 Mnemonics. (line 6)
* instruction naming, i386: i386-Mnemonics. (line 6)
* instruction naming, x86-64: i386-Mnemonics. (line 6)
* instruction operand modifier, s390: s390 Operand Modifier.
(line 6)
* instruction operands, s390: s390 Operands. (line 6)
* instruction prefixes, i386: i386-Prefixes. (line 6)
* instruction set, M680x0: M68K-opcodes. (line 6)
* instruction set, M68HC11: M68HC11-opcodes. (line 6)
* instruction set, XGATE: XGATE-opcodes. (line 5)
* instruction summary, AVR: AVR Opcodes. (line 6)
* instruction summary, D10V: D10V-Opcodes. (line 6)
* instruction summary, D30V: D30V-Opcodes. (line 6)
* instruction summary, H8/300: H8/300 Opcodes. (line 6)
* instruction summary, LM32: LM32 Opcodes. (line 6)
* instruction summary, SH: SH Opcodes. (line 6)
* instruction summary, SH64: SH64 Opcodes. (line 6)
* instruction summary, Z8000: Z8000 Opcodes. (line 6)
* instruction syntax, s390: s390 Syntax. (line 6)
* instructions and directives: Statements. (line 20)
* 'int' directive: Int. (line 6)
* 'int' directive, H8/300: H8/300 Directives. (line 6)
* 'int' directive, i386: i386-Float. (line 21)
* 'int' directive, TIC54X: TIC54X-Directives. (line 109)
* 'int' directive, x86-64: i386-Float. (line 21)
* integer expressions: Integer Exprs. (line 6)
* integer, 16-byte: Octa. (line 6)
* integer, 8-byte: Quad. (line 9)
* integers: Integers. (line 6)
* integers, 16-bit: hword. (line 6)
* integers, 32-bit: Int. (line 6)
* integers, binary: Integers. (line 6)
* integers, decimal: Integers. (line 12)
* integers, hexadecimal: Integers. (line 15)
* integers, octal: Integers. (line 9)
* integers, one byte: Byte. (line 6)
* intel_syntax pseudo op, i386: i386-Variations. (line 6)
* intel_syntax pseudo op, x86-64: i386-Variations. (line 6)
* internal assembler sections: As Sections. (line 6)
* 'internal' directive: Internal. (line 6)
* invalid input: Bug Criteria. (line 14)
* invocation summary: Overview. (line 6)
* IP2K architecture options: IP2K-Opts. (line 9)
* IP2K architecture options <1>: IP2K-Opts. (line 14)
* IP2K line comment character: IP2K-Chars. (line 6)
* IP2K line separator: IP2K-Chars. (line 14)
* IP2K options: IP2K-Opts. (line 6)
* IP2K support: IP2K-Dependent. (line 6)
* 'irp' directive: Irp. (line 6)
* 'irpc' directive: Irpc. (line 6)
* ISA options, SH64: SH64 Options. (line 6)
* joining text and data sections: R. (line 6)
* jump instructions, i386: i386-Mnemonics. (line 55)
* jump instructions, relaxation: Xtensa Jump Relaxation.
(line 6)
* jump instructions, x86-64: i386-Mnemonics. (line 55)
* jump optimization, i386: i386-Jumps. (line 6)
* jump optimization, x86-64: i386-Jumps. (line 6)
* jump/call operands, i386: i386-Variations. (line 15)
* jump/call operands, x86-64: i386-Variations. (line 15)
* 'L16SI' instructions, relaxation: Xtensa Immediate Relaxation.
(line 23)
* 'L16UI' instructions, relaxation: Xtensa Immediate Relaxation.
(line 23)
* 'L32I' instructions, relaxation: Xtensa Immediate Relaxation.
(line 23)
* 'L8UI' instructions, relaxation: Xtensa Immediate Relaxation.
(line 23)
* label (':'): Statements. (line 31)
* 'label' directive, TIC54X: TIC54X-Directives. (line 121)
* labels: Labels. (line 6)
* 'lcomm' directive: Lcomm. (line 6)
* 'lcomm' directive, COFF: i386-Directives. (line 6)
* ld: Object. (line 15)
* 'ldouble' directive M680x0: M68K-Float. (line 17)
* 'ldouble' directive M68HC11: M68HC11-Float. (line 17)
* 'ldouble' directive XGATE: XGATE-Float. (line 16)
* 'ldouble' directive, TIC54X: TIC54X-Directives. (line 62)
* 'LDR reg,=<expr>' pseudo op, AArch64: AArch64 Opcodes. (line 9)
* 'LDR reg,=<label>' pseudo op, ARM: ARM Opcodes. (line 15)
* 'leafproc' directive, i960: Directives-i960. (line 18)
* 'length' directive, TIC54X: TIC54X-Directives. (line 125)
* length of symbols: Symbol Intro. (line 14)
* 'lflags' directive (ignored): Lflags. (line 6)
* line comment character: Comments. (line 19)
* line comment character, AArch64: AArch64-Chars. (line 6)
* line comment character, Alpha: Alpha-Chars. (line 6)
* line comment character, ARC: ARC-Chars. (line 6)
* line comment character, ARM: ARM-Chars. (line 6)
* line comment character, AVR: AVR-Chars. (line 6)
* line comment character, CR16: CR16-Chars. (line 6)
* line comment character, D10V: D10V-Chars. (line 6)
* line comment character, D30V: D30V-Chars. (line 6)
* line comment character, Epiphany: Epiphany-Chars. (line 6)
* line comment character, H8/300: H8/300-Chars. (line 6)
* line comment character, i386: i386-Chars. (line 6)
* line comment character, i860: i860-Chars. (line 6)
* line comment character, i960: i960-Chars. (line 6)
* line comment character, IA-64: IA-64-Chars. (line 6)
* line comment character, IP2K: IP2K-Chars. (line 6)
* line comment character, LM32: LM32-Chars. (line 6)
* line comment character, M32C: M32C-Chars. (line 6)
* line comment character, M680x0: M68K-Chars. (line 6)
* line comment character, M68HC11: M68HC11-Syntax. (line 17)
* line comment character, Meta: Meta-Chars. (line 6)
* line comment character, MicroBlaze: MicroBlaze-Chars. (line 6)
* line comment character, MIPS: MIPS-Chars. (line 6)
* line comment character, MSP 430: MSP430-Chars. (line 6)
* line comment character, Nios II: Nios II Chars. (line 6)
* line comment character, NS32K: NS32K-Chars. (line 6)
* line comment character, PJ: PJ-Chars. (line 6)
* line comment character, PowerPC: PowerPC-Chars. (line 6)
* line comment character, RL78: RL78-Chars. (line 6)
* line comment character, RX: RX-Chars. (line 6)
* line comment character, s390: s390 Characters. (line 6)
* line comment character, SCORE: SCORE-Chars. (line 6)
* line comment character, SH: SH-Chars. (line 6)
* line comment character, SH64: SH64-Chars. (line 6)
* line comment character, Sparc: Sparc-Chars. (line 6)
* line comment character, TIC54X: TIC54X-Chars. (line 6)
* line comment character, TIC6X: TIC6X Syntax. (line 6)
* line comment character, V850: V850-Chars. (line 6)
* line comment character, VAX: VAX-Chars. (line 6)
* line comment character, XGATE: XGATE-Syntax. (line 16)
* line comment character, XStormy16: XStormy16-Chars. (line 6)
* line comment character, Z80: Z80-Chars. (line 6)
* line comment character, Z8000: Z8000-Chars. (line 6)
* line comment characters, CRIS: CRIS-Chars. (line 6)
* line comment characters, MMIX: MMIX-Chars. (line 6)
* 'line' directive: Line. (line 6)
* 'line' directive, MSP 430: MSP430 Directives. (line 14)
* line numbers, in input files: Input Files. (line 35)
* line numbers, in warnings/errors: Errors. (line 16)
* line separator character: Statements. (line 6)
* line separator character, Nios II: Nios II Chars. (line 6)
* line separator, AArch64: AArch64-Chars. (line 10)
* line separator, Alpha: Alpha-Chars. (line 11)
* line separator, ARC: ARC-Chars. (line 12)
* line separator, ARM: ARM-Chars. (line 14)
* line separator, AVR: AVR-Chars. (line 14)
* line separator, CR16: CR16-Chars. (line 12)
* line separator, Epiphany: Epiphany-Chars. (line 14)
* line separator, H8/300: H8/300-Chars. (line 8)
* line separator, i386: i386-Chars. (line 18)
* line separator, i860: i860-Chars. (line 14)
* line separator, i960: i960-Chars. (line 14)
* line separator, IA-64: IA-64-Chars. (line 8)
* line separator, IP2K: IP2K-Chars. (line 14)
* line separator, LM32: LM32-Chars. (line 12)
* line separator, M32C: M32C-Chars. (line 14)
* line separator, M680x0: M68K-Chars. (line 20)
* line separator, M68HC11: M68HC11-Syntax. (line 26)
* line separator, Meta: Meta-Chars. (line 8)
* line separator, MicroBlaze: MicroBlaze-Chars. (line 14)
* line separator, MIPS: MIPS-Chars. (line 14)
* line separator, MSP 430: MSP430-Chars. (line 14)
* line separator, NS32K: NS32K-Chars. (line 18)
* line separator, PJ: PJ-Chars. (line 14)
* line separator, PowerPC: PowerPC-Chars. (line 18)
* line separator, RL78: RL78-Chars. (line 14)
* line separator, RX: RX-Chars. (line 14)
* line separator, s390: s390 Characters. (line 13)
* line separator, SCORE: SCORE-Chars. (line 14)
* line separator, SH: SH-Chars. (line 8)
* line separator, SH64: SH64-Chars. (line 13)
* line separator, Sparc: Sparc-Chars. (line 14)
* line separator, TIC54X: TIC54X-Chars. (line 17)
* line separator, TIC6X: TIC6X Syntax. (line 13)
* line separator, V850: V850-Chars. (line 13)
* line separator, VAX: VAX-Chars. (line 14)
* line separator, XGATE: XGATE-Syntax. (line 25)
* line separator, XStormy16: XStormy16-Chars. (line 14)
* line separator, Z80: Z80-Chars. (line 13)
* line separator, Z8000: Z8000-Chars. (line 13)
* lines starting with '#': Comments. (line 33)
* linker: Object. (line 15)
* linker, and assembler: Secs Background. (line 10)
* 'linkonce' directive: Linkonce. (line 6)
* 'list' directive: List. (line 6)
* 'list' directive, TIC54X: TIC54X-Directives. (line 129)
* listing control, turning off: Nolist. (line 6)
* listing control, turning on: List. (line 6)
* listing control: new page: Eject. (line 6)
* listing control: paper size: Psize. (line 6)
* listing control: subtitle: Sbttl. (line 6)
* listing control: title line: Title. (line 6)
* listings, enabling: a. (line 6)
* 'literal' directive: Literal Directive. (line 6)
* literal pool entries, s390: s390 Literal Pool Entries.
(line 6)
* 'literal_position' directive: Literal Position Directive.
(line 6)
* 'literal_prefix' directive: Literal Prefix Directive.
(line 6)
* little endian output, MIPS: Overview. (line 751)
* little endian output, PJ: Overview. (line 658)
* little-endian output, MIPS: MIPS Options. (line 13)
* little-endian output, TIC6X: TIC6X Options. (line 46)
* LM32 line comment character: LM32-Chars. (line 6)
* LM32 line separator: LM32-Chars. (line 12)
* LM32 modifiers: LM32-Modifiers. (line 6)
* LM32 opcode summary: LM32 Opcodes. (line 6)
* LM32 options (none): LM32 Options. (line 6)
* LM32 register names: LM32-Regs. (line 6)
* LM32 support: LM32-Dependent. (line 6)
* 'ln' directive: Ln. (line 6)
* 'lo' directive, Nios II: Nios II Relocations. (line 23)
* 'lo' pseudo-op, V850: V850 Opcodes. (line 22)
* 'loc' directive: Loc. (line 6)
* local common symbols: Lcomm. (line 6)
* 'local' directive: Local. (line 6)
* local labels: Symbol Names. (line 40)
* local symbol names: Symbol Names. (line 27)
* local symbols, retaining in output: L. (line 6)
* location counter: Dot. (line 6)
* location counter, advancing: Org. (line 6)
* location counter, Z80: Z80-Chars. (line 15)
* 'loc_mark_labels' directive: Loc_mark_labels. (line 6)
* logical file name: File. (line 13)
* logical line number: Line. (line 6)
* logical line numbers: Comments. (line 33)
* 'long' directive: Long. (line 6)
* 'long' directive, ARC: ARC Directives. (line 147)
* 'long' directive, i386: i386-Float. (line 21)
* 'long' directive, TIC54X: TIC54X-Directives. (line 133)
* 'long' directive, x86-64: i386-Float. (line 21)
* 'longcall' pseudo-op, V850: V850 Opcodes. (line 122)
* 'longcalls' directive: Longcalls Directive. (line 6)
* 'longjump' pseudo-op, V850: V850 Opcodes. (line 128)
* 'loop' directive, TIC54X: TIC54X-Directives. (line 141)
* 'LOOP' instructions, alignment: Xtensa Automatic Alignment.
(line 6)
* 'low' directive, M32R: M32R-Directives. (line 9)
* 'lp' register, V850: V850-Regs. (line 68)
* lval: Z8000 Directives. (line 27)
* LWP, i386: i386-LWP. (line 6)
* LWP, x86-64: i386-LWP. (line 6)
* M16C architecture option: M32C-Opts. (line 12)
* M32C architecture option: M32C-Opts. (line 9)
* M32C line comment character: M32C-Chars. (line 6)
* M32C line separator: M32C-Chars. (line 14)
* M32C modifiers: M32C-Modifiers. (line 6)
* M32C options: M32C-Opts. (line 6)
* M32C support: M32C-Dependent. (line 6)
* M32R architecture options: M32R-Opts. (line 9)
* M32R architecture options <1>: M32R-Opts. (line 17)
* M32R architecture options <2>: M32R-Opts. (line 21)
* M32R directives: M32R-Directives. (line 6)
* M32R options: M32R-Opts. (line 6)
* M32R support: M32R-Dependent. (line 6)
* M32R warnings: M32R-Warnings. (line 6)
* M680x0 addressing modes: M68K-Syntax. (line 21)
* M680x0 architecture options: M68K-Opts. (line 99)
* M680x0 branch improvement: M68K-Branch. (line 6)
* M680x0 directives: M68K-Directives. (line 6)
* M680x0 floating point: M68K-Float. (line 6)
* M680x0 immediate character: M68K-Chars. (line 13)
* M680x0 line comment character: M68K-Chars. (line 6)
* M680x0 line separator: M68K-Chars. (line 20)
* M680x0 opcodes: M68K-opcodes. (line 6)
* M680x0 options: M68K-Opts. (line 6)
* M680x0 pseudo-opcodes: M68K-Branch. (line 6)
* M680x0 size modifiers: M68K-Syntax. (line 8)
* M680x0 support: M68K-Dependent. (line 6)
* M680x0 syntax: M68K-Syntax. (line 8)
* M68HC11 addressing modes: M68HC11-Syntax. (line 29)
* M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6)
* M68HC11 assembler directive .far: M68HC11-Directives. (line 20)
* M68HC11 assembler directive .interrupt: M68HC11-Directives. (line 26)
* M68HC11 assembler directive .mode: M68HC11-Directives. (line 16)
* M68HC11 assembler directive .relax: M68HC11-Directives. (line 10)
* M68HC11 assembler directive .xrefb: M68HC11-Directives. (line 31)
* M68HC11 assembler directives: M68HC11-Directives. (line 6)
* M68HC11 branch improvement: M68HC11-Branch. (line 6)
* M68HC11 floating point: M68HC11-Float. (line 6)
* M68HC11 line comment character: M68HC11-Syntax. (line 17)
* M68HC11 line separator: M68HC11-Syntax. (line 26)
* M68HC11 modifiers: M68HC11-Modifiers. (line 6)
* M68HC11 opcodes: M68HC11-opcodes. (line 6)
* M68HC11 options: M68HC11-Opts. (line 6)
* M68HC11 pseudo-opcodes: M68HC11-Branch. (line 6)
* M68HC11 syntax: M68HC11-Syntax. (line 6)
* M68HC12 assembler directives: M68HC11-Directives. (line 6)
* machine dependencies: Machine Dependencies.
(line 6)
* machine directives, AArch64: AArch64 Directives. (line 6)
* machine directives, ARC: ARC Directives. (line 6)
* machine directives, ARM: ARM Directives. (line 6)
* machine directives, H8/300 (none): H8/300 Directives. (line 6)
* machine directives, i860: Directives-i860. (line 6)
* machine directives, i960: Directives-i960. (line 6)
* machine directives, MSP 430: MSP430 Directives. (line 6)
* machine directives, Nios II: Nios II Directives. (line 6)
* machine directives, SH: SH Directives. (line 6)
* machine directives, SH64: SH64 Directives. (line 9)
* machine directives, SPARC: Sparc-Directives. (line 6)
* machine directives, TIC54X: TIC54X-Directives. (line 6)
* machine directives, TIC6X: TIC6X Directives. (line 6)
* machine directives, TILE-Gx: TILE-Gx Directives. (line 6)
* machine directives, TILEPro: TILEPro Directives. (line 6)
* machine directives, V850: V850 Directives. (line 6)
* machine directives, VAX: VAX-directives. (line 6)
* machine directives, x86: i386-Directives. (line 6)
* machine directives, XStormy16: XStormy16 Directives.
(line 6)
* machine independent directives: Pseudo Ops. (line 6)
* machine instructions (not covered): Manual. (line 14)
* machine relocations, Nios II: Nios II Relocations. (line 6)
* machine-independent syntax: Syntax. (line 6)
* 'macro' directive: Macro. (line 28)
* 'macro' directive, TIC54X: TIC54X-Directives. (line 151)
* macros: Macro. (line 6)
* macros, count executed: Macro. (line 142)
* Macros, MSP 430: MSP430-Macros. (line 6)
* macros, TIC54X: TIC54X-Macros. (line 6)
* make rules: MD. (line 6)
* manual, structure and purpose: Manual. (line 6)
* math builtins, TIC54X: TIC54X-Builtins. (line 6)
* Maximum number of continuation lines: listing. (line 34)
* memory references, i386: i386-Memory. (line 6)
* memory references, x86-64: i386-Memory. (line 6)
* memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6)
* merging text and data sections: R. (line 6)
* messages from assembler: Errors. (line 6)
* Meta architectures: Meta Options. (line 6)
* Meta line comment character: Meta-Chars. (line 6)
* Meta line separator: Meta-Chars. (line 8)
* Meta options: Meta Options. (line 6)
* Meta registers: Meta-Regs. (line 6)
* Meta support: Meta-Dependent. (line 6)
* MicroBlaze architectures: MicroBlaze-Dependent.
(line 6)
* MicroBlaze directives: MicroBlaze Directives.
(line 6)
* MicroBlaze line comment character: MicroBlaze-Chars. (line 6)
* MicroBlaze line separator: MicroBlaze-Chars. (line 14)
* MicroBlaze support: MicroBlaze-Dependent.
(line 12)
* minus, permitted arguments: Infix Ops. (line 50)
* MIPS 32-bit microMIPS instruction generation override: MIPS assembly options.
(line 18)
* MIPS architecture options: MIPS Options. (line 29)
* MIPS big-endian output: MIPS Options. (line 13)
* MIPS CPU override: MIPS ISA. (line 18)
* MIPS directives to override command line options: MIPS assembly options.
(line 6)
* MIPS DSP Release 1 instruction generation override: MIPS ASE Instruction Generation Overrides.
(line 21)
* MIPS DSP Release 2 instruction generation override: MIPS ASE Instruction Generation Overrides.
(line 26)
* MIPS endianness: Overview. (line 748)
* MIPS eXtended Physical Address (XPA) instruction generation override: MIPS ASE Instruction Generation Overrides.
(line 51)
* MIPS IEEE 754 NaN data encoding selection: MIPS NaN Encodings.
(line 6)
* MIPS ISA: Overview. (line 754)
* MIPS ISA override: MIPS ISA. (line 6)
* MIPS line comment character: MIPS-Chars. (line 6)
* MIPS line separator: MIPS-Chars. (line 14)
* MIPS little-endian output: MIPS Options. (line 13)
* MIPS MCU instruction generation override: MIPS ASE Instruction Generation Overrides.
(line 36)
* MIPS MDMX instruction generation override: MIPS ASE Instruction Generation Overrides.
(line 16)
* MIPS MIPS-3D instruction generation override: MIPS ASE Instruction Generation Overrides.
(line 6)
* MIPS MT instruction generation override: MIPS ASE Instruction Generation Overrides.
(line 31)
* MIPS option stack: MIPS Option Stack. (line 6)
* MIPS processor: MIPS-Dependent. (line 6)
* MIPS SIMD Architecture instruction generation override: MIPS ASE Instruction Generation Overrides.
(line 41)
* MIT: M68K-Syntax. (line 6)
* 'mlib' directive, TIC54X: TIC54X-Directives. (line 157)
* 'mlist' directive, TIC54X: TIC54X-Directives. (line 162)
* MMIX assembler directive BSPEC: MMIX-Pseudos. (line 137)
* MMIX assembler directive BYTE: MMIX-Pseudos. (line 101)
* MMIX assembler directive ESPEC: MMIX-Pseudos. (line 137)
* MMIX assembler directive GREG: MMIX-Pseudos. (line 53)
* MMIX assembler directive IS: MMIX-Pseudos. (line 44)
* MMIX assembler directive LOC: MMIX-Pseudos. (line 7)
* MMIX assembler directive LOCAL: MMIX-Pseudos. (line 29)
* MMIX assembler directive OCTA: MMIX-Pseudos. (line 113)
* MMIX assembler directive PREFIX: MMIX-Pseudos. (line 125)
* MMIX assembler directive TETRA: MMIX-Pseudos. (line 113)
* MMIX assembler directive WYDE: MMIX-Pseudos. (line 113)
* MMIX assembler directives: MMIX-Pseudos. (line 6)
* MMIX line comment characters: MMIX-Chars. (line 6)
* MMIX options: MMIX-Opts. (line 6)
* MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 137)
* MMIX pseudo-op BYTE: MMIX-Pseudos. (line 101)
* MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 137)
* MMIX pseudo-op GREG: MMIX-Pseudos. (line 53)
* MMIX pseudo-op IS: MMIX-Pseudos. (line 44)
* MMIX pseudo-op LOC: MMIX-Pseudos. (line 7)
* MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 29)
* MMIX pseudo-op OCTA: MMIX-Pseudos. (line 113)
* MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 125)
* MMIX pseudo-op TETRA: MMIX-Pseudos. (line 113)
* MMIX pseudo-op WYDE: MMIX-Pseudos. (line 113)
* MMIX pseudo-ops: MMIX-Pseudos. (line 6)
* MMIX register names: MMIX-Regs. (line 6)
* MMIX support: MMIX-Dependent. (line 6)
* mmixal differences: MMIX-mmixal. (line 6)
* 'mmregs' directive, TIC54X: TIC54X-Directives. (line 167)
* 'mmsg' directive, TIC54X: TIC54X-Directives. (line 75)
* MMX, i386: i386-SIMD. (line 6)
* MMX, x86-64: i386-SIMD. (line 6)
* mnemonic compatibility, i386: i386-Mnemonics. (line 61)
* mnemonic suffixes, i386: i386-Variations. (line 28)
* mnemonic suffixes, x86-64: i386-Variations. (line 28)
* mnemonics for opcodes, VAX: VAX-opcodes. (line 6)
* mnemonics, AVR: AVR Opcodes. (line 6)
* mnemonics, D10V: D10V-Opcodes. (line 6)
* mnemonics, D30V: D30V-Opcodes. (line 6)
* mnemonics, H8/300: H8/300 Opcodes. (line 6)
* mnemonics, LM32: LM32 Opcodes. (line 6)
* mnemonics, SH: SH Opcodes. (line 6)
* mnemonics, SH64: SH64 Opcodes. (line 6)
* mnemonics, Z8000: Z8000 Opcodes. (line 6)
* 'mnolist' directive, TIC54X: TIC54X-Directives. (line 162)
* modifiers, M32C: M32C-Modifiers. (line 6)
* Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6)
* 'MOVI' instructions, relaxation: Xtensa Immediate Relaxation.
(line 12)
* MOVN, MOVZ and MOVK group relocations, AArch64: AArch64-Relocations.
(line 6)
* MOVW and MOVT relocations, ARM: ARM-Relocations. (line 21)
* MRI compatibility mode: M. (line 6)
* 'mri' directive: MRI. (line 6)
* MRI mode, temporarily: MRI. (line 6)
* MSP 430 floating point (IEEE): MSP430 Floating Point.
(line 6)
* MSP 430 identifiers: MSP430-Chars. (line 17)
* MSP 430 line comment character: MSP430-Chars. (line 6)
* MSP 430 line separator: MSP430-Chars. (line 14)
* MSP 430 machine directives: MSP430 Directives. (line 6)
* MSP 430 macros: MSP430-Macros. (line 6)
* MSP 430 opcodes: MSP430 Opcodes. (line 6)
* MSP 430 options (none): MSP430 Options. (line 6)
* MSP 430 profiling capability: MSP430 Profiling Capability.
(line 6)
* MSP 430 register names: MSP430-Regs. (line 6)
* MSP 430 support: MSP430-Dependent. (line 6)
* MSP430 Assembler Extensions: MSP430-Ext. (line 6)
* 'mul' instruction, i386: i386-Notes. (line 6)
* 'mul' instruction, x86-64: i386-Notes. (line 6)
* N32K support: NS32K-Dependent. (line 6)
* name: Z8000 Directives. (line 18)
* named section: Section. (line 6)
* named sections: Ld Sections. (line 8)
* names, symbol: Symbol Names. (line 6)
* naming object file: o. (line 6)
* NDS32 options: NDS32 Options. (line 6)
* NDS32 processor: NDS32-Dependent. (line 6)
* new page, in listings: Eject. (line 6)
* 'newblock' directive, TIC54X: TIC54X-Directives. (line 173)
* newline ('\n'): Strings. (line 21)
* newline, required at file end: Statements. (line 14)
* Nios II line comment character: Nios II Chars. (line 6)
* Nios II line separator character: Nios II Chars. (line 6)
* Nios II machine directives: Nios II Directives. (line 6)
* Nios II machine relocations: Nios II Relocations. (line 6)
* Nios II opcodes: Nios II Opcodes. (line 6)
* Nios II options: Nios II Options. (line 6)
* Nios II support: NiosII-Dependent. (line 6)
* Nios support: NiosII-Dependent. (line 6)
* 'no-absolute-literals' directive: Absolute Literals Directive.
(line 6)
* 'no-longcalls' directive: Longcalls Directive. (line 6)
* 'no-relax' command line option, Nios II: Nios II Options. (line 19)
* 'no-schedule' directive: Schedule Directive. (line 6)
* 'no-transform' directive: Transform Directive. (line 6)
* 'nolist' directive: Nolist. (line 6)
* 'nolist' directive, TIC54X: TIC54X-Directives. (line 129)
* 'NOP' pseudo op, ARM: ARM Opcodes. (line 9)
* notes for Alpha: Alpha Notes. (line 6)
* NS32K line comment character: NS32K-Chars. (line 6)
* NS32K line separator: NS32K-Chars. (line 18)
* null-terminated strings: Asciz. (line 6)
* number constants: Numbers. (line 6)
* number of macros executed: Macro. (line 142)
* numbered subsections: Sub-Sections. (line 6)
* numbers, 16-bit: hword. (line 6)
* numeric values: Expressions. (line 6)
* 'nword' directive, SPARC: Sparc-Directives. (line 20)
* object attributes: Object Attributes. (line 6)
* object file: Object. (line 6)
* object file format: Object Formats. (line 6)
* object file name: o. (line 6)
* object file, after errors: Z. (line 6)
* obsolescent directives: Deprecated. (line 6)
* 'octa' directive: Octa. (line 6)
* octal character code ('\DDD'): Strings. (line 30)
* octal integers: Integers. (line 9)
* 'offset' directive: Offset. (line 6)
* 'offset' directive, V850: V850 Directives. (line 6)
* opcode mnemonics, VAX: VAX-opcodes. (line 6)
* opcode names, TILE-Gx: TILE-Gx Opcodes. (line 6)
* opcode names, TILEPro: TILEPro Opcodes. (line 6)
* opcode names, Xtensa: Xtensa Opcodes. (line 6)
* opcode summary, AVR: AVR Opcodes. (line 6)
* opcode summary, D10V: D10V-Opcodes. (line 6)
* opcode summary, D30V: D30V-Opcodes. (line 6)
* opcode summary, H8/300: H8/300 Opcodes. (line 6)
* opcode summary, LM32: LM32 Opcodes. (line 6)
* opcode summary, SH: SH Opcodes. (line 6)
* opcode summary, SH64: SH64 Opcodes. (line 6)
* opcode summary, Z8000: Z8000 Opcodes. (line 6)
* opcodes for AArch64: AArch64 Opcodes. (line 6)
* opcodes for ARC: ARC Opcodes. (line 6)
* opcodes for ARM: ARM Opcodes. (line 6)
* opcodes for MSP 430: MSP430 Opcodes. (line 6)
* opcodes for Nios II: Nios II Opcodes. (line 6)
* opcodes for V850: V850 Opcodes. (line 6)
* opcodes, i860: Opcodes for i860. (line 6)
* opcodes, i960: Opcodes for i960. (line 6)
* opcodes, M680x0: M68K-opcodes. (line 6)
* opcodes, M68HC11: M68HC11-opcodes. (line 6)
* operand delimiters, i386: i386-Variations. (line 15)
* operand delimiters, x86-64: i386-Variations. (line 15)
* operand notation, VAX: VAX-operands. (line 6)
* operands in expressions: Arguments. (line 6)
* operator precedence: Infix Ops. (line 11)
* operators, in expressions: Operators. (line 6)
* operators, permitted arguments: Infix Ops. (line 6)
* optimization, D10V: Overview. (line 521)
* optimization, D30V: Overview. (line 526)
* optimizations: Xtensa Optimizations.
(line 6)
* 'option' directive, ARC: ARC Directives. (line 150)
* 'option' directive, TIC54X: TIC54X-Directives. (line 177)
* option summary: Overview. (line 6)
* options for AArch64 (none): AArch64 Options. (line 6)
* options for Alpha: Alpha Options. (line 6)
* options for ARC (none): ARC Options. (line 6)
* options for ARM (none): ARM Options. (line 6)
* options for AVR (none): AVR Options. (line 6)
* options for Blackfin (none): Blackfin Options. (line 6)
* options for i386: i386-Options. (line 6)
* options for IA-64: IA-64 Options. (line 6)
* options for LM32 (none): LM32 Options. (line 6)
* options for Meta: Meta Options. (line 6)
* options for MSP430 (none): MSP430 Options. (line 6)
* options for NDS32: NDS32 Options. (line 6)
* options for Nios II: Nios II Options. (line 6)
* options for PDP-11: PDP-11-Options. (line 6)
* options for PowerPC: PowerPC-Opts. (line 6)
* options for s390: s390 Options. (line 6)
* options for SCORE: SCORE-Opts. (line 6)
* options for SPARC: Sparc-Opts. (line 6)
* options for TIC6X: TIC6X Options. (line 6)
* options for V850 (none): V850 Options. (line 6)
* options for VAX/VMS: VAX-Opts. (line 42)
* options for x86-64: i386-Options. (line 6)
* options for Z80: Z80 Options. (line 6)
* options, all versions of assembler: Invoking. (line 6)
* options, command line: Command Line. (line 13)
* options, CRIS: CRIS-Opts. (line 6)
* options, D10V: D10V-Opts. (line 6)
* options, D30V: D30V-Opts. (line 6)
* options, Epiphany: Epiphany Options. (line 6)
* options, H8/300: H8/300 Options. (line 6)
* options, i960: Options-i960. (line 6)
* options, IP2K: IP2K-Opts. (line 6)
* options, M32C: M32C-Opts. (line 6)
* options, M32R: M32R-Opts. (line 6)
* options, M680x0: M68K-Opts. (line 6)
* options, M68HC11: M68HC11-Opts. (line 6)
* options, MMIX: MMIX-Opts. (line 6)
* options, PJ: PJ Options. (line 6)
* options, RL78: RL78-Opts. (line 6)
* options, RX: RX-Opts. (line 6)
* options, SH: SH Options. (line 6)
* options, SH64: SH64 Options. (line 6)
* options, TIC54X: TIC54X-Opts. (line 6)
* options, XGATE: XGATE-Opts. (line 6)
* options, Z8000: Z8000 Options. (line 6)
* 'org' directive: Org. (line 6)
* other attribute, of 'a.out' symbol: Symbol Other. (line 6)
* output file: Object. (line 6)
* 'p2align' directive: P2align. (line 6)
* 'p2alignl' directive: P2align. (line 28)
* 'p2alignw' directive: P2align. (line 28)
* padding the location counter: Align. (line 6)
* padding the location counter given a power of two: P2align. (line 6)
* padding the location counter given number of bytes: Balign. (line 6)
* page, in listings: Eject. (line 6)
* paper size, for listings: Psize. (line 6)
* paths for '.include': I. (line 6)
* patterns, writing in memory: Fill. (line 6)
* PDP-11 comments: PDP-11-Syntax. (line 16)
* PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13)
* PDP-11 general-purpose register syntax: PDP-11-Syntax. (line 10)
* PDP-11 instruction naming: PDP-11-Mnemonics. (line 6)
* PDP-11 line separator: PDP-11-Syntax. (line 19)
* PDP-11 support: PDP-11-Dependent. (line 6)
* PDP-11 syntax: PDP-11-Syntax. (line 6)
* PIC code generation for ARM: ARM Options. (line 173)
* PIC code generation for M32R: M32R-Opts. (line 42)
* PIC selection, MIPS: MIPS Options. (line 21)
* PJ endianness: Overview. (line 655)
* PJ line comment character: PJ-Chars. (line 6)
* PJ line separator: PJ-Chars. (line 14)
* PJ options: PJ Options. (line 6)
* PJ support: PJ-Dependent. (line 6)
* plus, permitted arguments: Infix Ops. (line 45)
* 'popsection' directive: PopSection. (line 6)
* Position-independent code, CRIS: CRIS-Opts. (line 27)
* Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6)
* PowerPC architectures: PowerPC-Opts. (line 6)
* PowerPC directives: PowerPC-Pseudo. (line 6)
* PowerPC line comment character: PowerPC-Chars. (line 6)
* PowerPC line separator: PowerPC-Chars. (line 18)
* PowerPC options: PowerPC-Opts. (line 6)
* PowerPC support: PPC-Dependent. (line 6)
* precedence of operators: Infix Ops. (line 11)
* precision, floating point: Flonums. (line 6)
* prefix operators: Prefix Ops. (line 6)
* prefixes, i386: i386-Prefixes. (line 6)
* preprocessing: Preprocessing. (line 6)
* preprocessing, turning on and off: Preprocessing. (line 26)
* 'previous' directive: Previous. (line 6)
* primary attributes, COFF symbols: COFF Symbols. (line 13)
* 'print' directive: Print. (line 6)
* 'proc' directive, SPARC: Sparc-Directives. (line 25)
* 'profiler' directive, MSP 430: MSP430 Directives. (line 26)
* profiling capability for MSP 430: MSP430 Profiling Capability.
(line 6)
* 'protected' directive: Protected. (line 6)
* pseudo-op .arch, CRIS: CRIS-Pseudos. (line 50)
* pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12)
* pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 18)
* pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 137)
* pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 101)
* pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 137)
* pseudo-op GREG, MMIX: MMIX-Pseudos. (line 53)
* pseudo-op IS, MMIX: MMIX-Pseudos. (line 44)
* pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7)
* pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 29)
* pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 113)
* pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 125)
* pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 113)
* pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 113)
* pseudo-opcodes for XStormy16: XStormy16 Opcodes. (line 6)
* pseudo-opcodes, M680x0: M68K-Branch. (line 6)
* pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6)
* pseudo-ops for branch, VAX: VAX-branch. (line 6)
* pseudo-ops, CRIS: CRIS-Pseudos. (line 6)
* pseudo-ops, machine independent: Pseudo Ops. (line 6)
* pseudo-ops, MMIX: MMIX-Pseudos. (line 6)
* 'psize' directive: Psize. (line 6)
* PSR bits: IA-64-Bits. (line 6)
* 'pstring' directive, TIC54X: TIC54X-Directives. (line 206)
* 'psw' register, V850: V850-Regs. (line 80)
* 'purgem' directive: Purgem. (line 6)
* purpose of GNU assembler: GNU Assembler. (line 12)
* 'pushsection' directive: PushSection. (line 6)
* 'quad' directive: Quad. (line 6)
* 'quad' directive, i386: i386-Float. (line 21)
* 'quad' directive, x86-64: i386-Float. (line 21)
* real-mode code, i386: i386-16bit. (line 6)
* 'ref' directive, TIC54X: TIC54X-Directives. (line 101)
* 'refsym' directive, MSP 430: MSP430 Directives. (line 30)
* 'register' directive, SPARC: Sparc-Directives. (line 29)
* register names, AArch64: AArch64-Regs. (line 6)
* register names, Alpha: Alpha-Regs. (line 6)
* register names, ARC: ARC-Regs. (line 6)
* register names, ARM: ARM-Regs. (line 6)
* register names, AVR: AVR-Regs. (line 6)
* register names, CRIS: CRIS-Regs. (line 6)
* register names, H8/300: H8/300-Regs. (line 6)
* register names, IA-64: IA-64-Regs. (line 6)
* register names, LM32: LM32-Regs. (line 6)
* register names, MMIX: MMIX-Regs. (line 6)
* register names, MSP 430: MSP430-Regs. (line 6)
* register names, Sparc: Sparc-Regs. (line 6)
* register names, TILE-Gx: TILE-Gx Registers. (line 6)
* register names, TILEPro: TILEPro Registers. (line 6)
* register names, V850: V850-Regs. (line 6)
* register names, VAX: VAX-operands. (line 17)
* register names, Xtensa: Xtensa Registers. (line 6)
* register names, Z80: Z80-Regs. (line 6)
* register naming, s390: s390 Register. (line 6)
* register operands, i386: i386-Variations. (line 15)
* register operands, x86-64: i386-Variations. (line 15)
* registers, D10V: D10V-Regs. (line 6)
* registers, D30V: D30V-Regs. (line 6)
* registers, i386: i386-Regs. (line 6)
* registers, Meta: Meta-Regs. (line 6)
* registers, SH: SH-Regs. (line 6)
* registers, SH64: SH64-Regs. (line 6)
* registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6)
* registers, x86-64: i386-Regs. (line 6)
* registers, Z8000: Z8000-Regs. (line 6)
* 'relax-all' command line option, Nios II: Nios II Options. (line 13)
* 'relax-section' command line option, Nios II: Nios II Options.
(line 6)
* relaxation: Xtensa Relaxation. (line 6)
* relaxation of 'ADDI' instructions: Xtensa Immediate Relaxation.
(line 43)
* relaxation of branch instructions: Xtensa Branch Relaxation.
(line 6)
* relaxation of call instructions: Xtensa Call Relaxation.
(line 6)
* relaxation of immediate fields: Xtensa Immediate Relaxation.
(line 6)
* relaxation of jump instructions: Xtensa Jump Relaxation.
(line 6)
* relaxation of 'L16SI' instructions: Xtensa Immediate Relaxation.
(line 23)
* relaxation of 'L16UI' instructions: Xtensa Immediate Relaxation.
(line 23)
* relaxation of 'L32I' instructions: Xtensa Immediate Relaxation.
(line 23)
* relaxation of 'L8UI' instructions: Xtensa Immediate Relaxation.
(line 23)
* relaxation of 'MOVI' instructions: Xtensa Immediate Relaxation.
(line 12)
* 'reloc' directive: Reloc. (line 6)
* relocation: Sections. (line 6)
* relocation example: Ld Sections. (line 40)
* relocations, AArch64: AArch64-Relocations. (line 6)
* relocations, Alpha: Alpha-Relocs. (line 6)
* relocations, Sparc: Sparc-Relocs. (line 6)
* repeat prefixes, i386: i386-Prefixes. (line 44)
* reporting bugs in assembler: Reporting Bugs. (line 6)
* 'rept' directive: Rept. (line 6)
* 'reserve' directive, SPARC: Sparc-Directives. (line 39)
* return instructions, i386: i386-Variations. (line 40)
* return instructions, x86-64: i386-Variations. (line 40)
* REX prefixes, i386: i386-Prefixes. (line 46)
* RL78 assembler directives: RL78-Directives. (line 6)
* RL78 line comment character: RL78-Chars. (line 6)
* RL78 line separator: RL78-Chars. (line 14)
* RL78 modifiers: RL78-Modifiers. (line 6)
* RL78 options: RL78-Opts. (line 6)
* RL78 support: RL78-Dependent. (line 6)
* rsect: Z8000 Directives. (line 51)
* RX assembler directive .3byte: RX-Directives. (line 9)
* RX assembler directive .fetchalign: RX-Directives. (line 13)
* RX assembler directives: RX-Directives. (line 6)
* RX floating point: RX-Float. (line 6)
* RX line comment character: RX-Chars. (line 6)
* RX line separator: RX-Chars. (line 14)
* RX modifiers: RX-Modifiers. (line 6)
* RX options: RX-Opts. (line 6)
* RX support: RX-Dependent. (line 6)
* s390 floating point: s390 Floating Point. (line 6)
* s390 instruction aliases: s390 Aliases. (line 6)
* s390 instruction formats: s390 Formats. (line 6)
* s390 instruction marker: s390 Instruction Marker.
(line 6)
* s390 instruction mnemonics: s390 Mnemonics. (line 6)
* s390 instruction operand modifier: s390 Operand Modifier.
(line 6)
* s390 instruction operands: s390 Operands. (line 6)
* s390 instruction syntax: s390 Syntax. (line 6)
* s390 line comment character: s390 Characters. (line 6)
* s390 line separator: s390 Characters. (line 13)
* s390 literal pool entries: s390 Literal Pool Entries.
(line 6)
* s390 options: s390 Options. (line 6)
* s390 register naming: s390 Register. (line 6)
* s390 support: S/390-Dependent. (line 6)
* 'sblock' directive, TIC54X: TIC54X-Directives. (line 180)
* 'sbttl' directive: Sbttl. (line 6)
* 'schedule' directive: Schedule Directive. (line 6)
* 'scl' directive: Scl. (line 6)
* SCORE architectures: SCORE-Opts. (line 6)
* SCORE directives: SCORE-Pseudo. (line 6)
* SCORE line comment character: SCORE-Chars. (line 6)
* SCORE line separator: SCORE-Chars. (line 14)
* SCORE options: SCORE-Opts. (line 6)
* SCORE processor: SCORE-Dependent. (line 6)
* 'sdaoff' pseudo-op, V850: V850 Opcodes. (line 65)
* search path for '.include': I. (line 6)
* 'sect' directive, TIC54X: TIC54X-Directives. (line 186)
* 'section' directive (COFF version): Section. (line 16)
* 'section' directive (ELF version): Section. (line 66)
* 'section' directive, V850: V850 Directives. (line 9)
* section name substitution: Section. (line 70)
* section override prefixes, i386: i386-Prefixes. (line 23)
* Section Stack: PopSection. (line 6)
* Section Stack <1>: Previous. (line 6)
* Section Stack <2>: PushSection. (line 6)
* Section Stack <3>: Section. (line 61)
* Section Stack <4>: SubSection. (line 6)
* section-relative addressing: Secs Background. (line 65)
* sections: Sections. (line 6)
* sections in messages, internal: As Sections. (line 6)
* sections, i386: i386-Variations. (line 46)
* sections, named: Ld Sections. (line 8)
* sections, x86-64: i386-Variations. (line 46)
* 'seg' directive, SPARC: Sparc-Directives. (line 44)
* segm: Z8000 Directives. (line 10)
* 'set at' directive, Nios II: Nios II Directives. (line 35)
* 'set break' directive, Nios II: Nios II Directives. (line 43)
* 'set' directive: Set. (line 6)
* 'set' directive, Nios II: Nios II Directives. (line 57)
* 'set' directive, TIC54X: TIC54X-Directives. (line 189)
* 'set noat' directive, Nios II: Nios II Directives. (line 31)
* 'set nobreak' directive, Nios II: Nios II Directives. (line 39)
* 'set norelax' directive, Nios II: Nios II Directives. (line 46)
* 'set relaxall' directive, Nios II: Nios II Directives. (line 53)
* 'set relaxsection' directive, Nios II: Nios II Directives. (line 49)
* SH addressing modes: SH-Addressing. (line 6)
* SH floating point (IEEE): SH Floating Point. (line 6)
* SH line comment character: SH-Chars. (line 6)
* SH line separator: SH-Chars. (line 8)
* SH machine directives: SH Directives. (line 6)
* SH opcode summary: SH Opcodes. (line 6)
* SH options: SH Options. (line 6)
* SH registers: SH-Regs. (line 6)
* SH support: SH-Dependent. (line 6)
* SH64 ABI options: SH64 Options. (line 25)
* SH64 addressing modes: SH64-Addressing. (line 6)
* SH64 ISA options: SH64 Options. (line 6)
* SH64 line comment character: SH64-Chars. (line 6)
* SH64 line separator: SH64-Chars. (line 13)
* SH64 machine directives: SH64 Directives. (line 9)
* SH64 opcode summary: SH64 Opcodes. (line 6)
* SH64 options: SH64 Options. (line 6)
* SH64 registers: SH64-Regs. (line 6)
* SH64 support: SH64-Dependent. (line 6)
* 'shigh' directive, M32R: M32R-Directives. (line 26)
* 'short' directive: Short. (line 6)
* 'short' directive, ARC: ARC Directives. (line 159)
* 'short' directive, TIC54X: TIC54X-Directives. (line 109)
* SIMD, i386: i386-SIMD. (line 6)
* SIMD, x86-64: i386-SIMD. (line 6)
* single character constant: Chars. (line 6)
* 'single' directive: Single. (line 6)
* 'single' directive, i386: i386-Float. (line 14)
* 'single' directive, x86-64: i386-Float. (line 14)
* single quote, Z80: Z80-Chars. (line 20)
* sixteen bit integers: hword. (line 6)
* sixteen byte integer: Octa. (line 6)
* 'size' directive (COFF version): Size. (line 11)
* 'size' directive (ELF version): Size. (line 19)
* size modifiers, D10V: D10V-Size. (line 6)
* size modifiers, D30V: D30V-Size. (line 6)
* size modifiers, M680x0: M68K-Syntax. (line 8)
* size prefixes, i386: i386-Prefixes. (line 27)
* size suffixes, H8/300: H8/300 Opcodes. (line 160)
* size, translations, Sparc: Sparc-Size-Translations.
(line 6)
* sizes operands, i386: i386-Variations. (line 28)
* sizes operands, x86-64: i386-Variations. (line 28)
* 'skip' directive: Skip. (line 6)
* 'skip' directive, M680x0: M68K-Directives. (line 19)
* 'skip' directive, SPARC: Sparc-Directives. (line 48)
* 'sleb128' directive: Sleb128. (line 6)
* small data, MIPS: MIPS Small Data. (line 6)
* SmartMIPS instruction generation override: MIPS ASE Instruction Generation Overrides.
(line 11)
* SOM symbol attributes: SOM Symbols. (line 6)
* source program: Input Files. (line 6)
* source, destination operands; i386: i386-Variations. (line 21)
* source, destination operands; x86-64: i386-Variations. (line 21)
* sp register: Xtensa Registers. (line 6)
* 'sp' register, V850: V850-Regs. (line 12)
* 'space' directive: Space. (line 6)
* 'space' directive, TIC54X: TIC54X-Directives. (line 194)
* space used, maximum for assembly: statistics. (line 6)
* SPARC architectures: Sparc-Opts. (line 6)
* Sparc constants: Sparc-Constants. (line 6)
* SPARC data alignment: Sparc-Aligned-Data. (line 6)
* SPARC floating point (IEEE): Sparc-Float. (line 6)
* Sparc line comment character: Sparc-Chars. (line 6)
* Sparc line separator: Sparc-Chars. (line 14)
* SPARC machine directives: Sparc-Directives. (line 6)
* SPARC options: Sparc-Opts. (line 6)
* Sparc registers: Sparc-Regs. (line 6)
* Sparc relocations: Sparc-Relocs. (line 6)
* Sparc size translations: Sparc-Size-Translations.
(line 6)
* SPARC support: Sparc-Dependent. (line 6)
* SPARC syntax: Sparc-Aligned-Data. (line 21)
* special characters, M680x0: M68K-Chars. (line 6)
* special purpose registers, MSP 430: MSP430-Regs. (line 11)
* 'sslist' directive, TIC54X: TIC54X-Directives. (line 201)
* 'ssnolist' directive, TIC54X: TIC54X-Directives. (line 201)
* 'stabd' directive: Stab. (line 38)
* 'stabn' directive: Stab. (line 49)
* 'stabs' directive: Stab. (line 52)
* 'stabX' directives: Stab. (line 6)
* standard assembler sections: Secs Background. (line 27)
* standard input, as input file: Command Line. (line 10)
* statement separator character: Statements. (line 6)
* statement separator, AArch64: AArch64-Chars. (line 10)
* statement separator, Alpha: Alpha-Chars. (line 11)
* statement separator, ARC: ARC-Chars. (line 12)
* statement separator, ARM: ARM-Chars. (line 14)
* statement separator, AVR: AVR-Chars. (line 14)
* statement separator, CR16: CR16-Chars. (line 12)
* statement separator, Epiphany: Epiphany-Chars. (line 14)
* statement separator, H8/300: H8/300-Chars. (line 8)
* statement separator, i386: i386-Chars. (line 18)
* statement separator, i860: i860-Chars. (line 14)
* statement separator, i960: i960-Chars. (line 14)
* statement separator, IA-64: IA-64-Chars. (line 8)
* statement separator, IP2K: IP2K-Chars. (line 14)
* statement separator, LM32: LM32-Chars. (line 12)
* statement separator, M32C: M32C-Chars. (line 14)
* statement separator, M68HC11: M68HC11-Syntax. (line 26)
* statement separator, Meta: Meta-Chars. (line 8)
* statement separator, MicroBlaze: MicroBlaze-Chars. (line 14)
* statement separator, MIPS: MIPS-Chars. (line 14)
* statement separator, MSP 430: MSP430-Chars. (line 14)
* statement separator, NS32K: NS32K-Chars. (line 18)
* statement separator, PJ: PJ-Chars. (line 14)
* statement separator, PowerPC: PowerPC-Chars. (line 18)
* statement separator, RL78: RL78-Chars. (line 14)
* statement separator, RX: RX-Chars. (line 14)
* statement separator, s390: s390 Characters. (line 13)
* statement separator, SCORE: SCORE-Chars. (line 14)
* statement separator, SH: SH-Chars. (line 8)
* statement separator, SH64: SH64-Chars. (line 13)
* statement separator, Sparc: Sparc-Chars. (line 14)
* statement separator, TIC54X: TIC54X-Chars. (line 17)
* statement separator, TIC6X: TIC6X Syntax. (line 13)
* statement separator, V850: V850-Chars. (line 13)
* statement separator, VAX: VAX-Chars. (line 14)
* statement separator, XGATE: XGATE-Syntax. (line 25)
* statement separator, XStormy16: XStormy16-Chars. (line 14)
* statement separator, Z80: Z80-Chars. (line 13)
* statement separator, Z8000: Z8000-Chars. (line 13)
* statements, structure of: Statements. (line 6)
* statistics, about assembly: statistics. (line 6)
* stopping the assembly: Abort. (line 6)
* string constants: Strings. (line 6)
* 'string' directive: String. (line 8)
* 'string' directive on HPPA: HPPA Directives. (line 137)
* 'string' directive, TIC54X: TIC54X-Directives. (line 206)
* string literals: Ascii. (line 6)
* string, copying to object file: String. (line 8)
* 'string16' directive: String. (line 8)
* string16, copying to object file: String. (line 8)
* 'string32' directive: String. (line 8)
* string32, copying to object file: String. (line 8)
* 'string64' directive: String. (line 8)
* string64, copying to object file: String. (line 8)
* 'string8' directive: String. (line 8)
* string8, copying to object file: String. (line 8)
* 'struct' directive: Struct. (line 6)
* 'struct' directive, TIC54X: TIC54X-Directives. (line 214)
* structure debugging, COFF: Tag. (line 6)
* sub-instruction ordering, D10V: D10V-Chars. (line 14)
* sub-instruction ordering, D30V: D30V-Chars. (line 14)
* sub-instructions, D10V: D10V-Subs. (line 6)
* sub-instructions, D30V: D30V-Subs. (line 6)
* subexpressions: Arguments. (line 24)
* 'subsection' directive: SubSection. (line 6)
* subsym builtins, TIC54X: TIC54X-Macros. (line 16)
* subtitles for listings: Sbttl. (line 6)
* subtraction, permitted arguments: Infix Ops. (line 50)
* summary of options: Overview. (line 6)
* support: HPPA-Dependent. (line 6)
* supporting files, including: Include. (line 6)
* suppressing warnings: W. (line 11)
* sval: Z8000 Directives. (line 33)
* symbol attributes: Symbol Attributes. (line 6)
* symbol attributes, 'a.out': a.out Symbols. (line 6)
* symbol attributes, COFF: COFF Symbols. (line 6)
* symbol attributes, SOM: SOM Symbols. (line 6)
* symbol descriptor, COFF: Desc. (line 6)
* symbol modifiers: AVR-Modifiers. (line 12)
* symbol modifiers <1>: LM32-Modifiers. (line 12)
* symbol modifiers <2>: M32C-Modifiers. (line 11)
* symbol modifiers <3>: M68HC11-Modifiers. (line 12)
* symbol modifiers, TILE-Gx: TILE-Gx Modifiers. (line 6)
* symbol modifiers, TILEPro: TILEPro Modifiers. (line 6)
* symbol names: Symbol Names. (line 6)
* symbol names, '$' in: D10V-Chars. (line 46)
* symbol names, '$' in <1>: D30V-Chars. (line 70)
* symbol names, '$' in <2>: Meta-Chars. (line 10)
* symbol names, '$' in <3>: SH-Chars. (line 15)
* symbol names, '$' in <4>: SH64-Chars. (line 15)
* symbol names, local: Symbol Names. (line 27)
* symbol names, temporary: Symbol Names. (line 40)
* symbol storage class (COFF): Scl. (line 6)
* symbol type: Symbol Type. (line 6)
* symbol type, COFF: Type. (line 11)
* symbol type, ELF: Type. (line 22)
* symbol value: Symbol Value. (line 6)
* symbol value, setting: Set. (line 6)
* symbol values, assigning: Setting Symbols. (line 6)
* symbol versioning: Symver. (line 6)
* symbol, common: Comm. (line 6)
* symbol, making visible to linker: Global. (line 6)
* symbolic debuggers, information for: Stab. (line 6)
* symbols: Symbols. (line 6)
* Symbols in position-independent code, CRIS: CRIS-Pic. (line 6)
* symbols with uppercase, VAX/VMS: VAX-Opts. (line 42)
* symbols, assigning values to: Equ. (line 6)
* Symbols, built-in, CRIS: CRIS-Symbols. (line 6)
* Symbols, CRIS, built-in: CRIS-Symbols. (line 6)
* symbols, local common: Lcomm. (line 6)
* 'symver' directive: Symver. (line 6)
* syntax compatibility, i386: i386-Variations. (line 6)
* syntax compatibility, x86-64: i386-Variations. (line 6)
* syntax, AVR: AVR-Modifiers. (line 6)
* syntax, Blackfin: Blackfin Syntax. (line 6)
* syntax, D10V: D10V-Syntax. (line 6)
* syntax, D30V: D30V-Syntax. (line 6)
* syntax, LM32: LM32-Modifiers. (line 6)
* syntax, M680x0: M68K-Syntax. (line 8)
* syntax, M68HC11: M68HC11-Syntax. (line 6)
* syntax, M68HC11 <1>: M68HC11-Modifiers. (line 6)
* syntax, machine-independent: Syntax. (line 6)
* syntax, RL78: RL78-Modifiers. (line 6)
* syntax, RX: RX-Modifiers. (line 6)
* syntax, SPARC: Sparc-Aligned-Data. (line 20)
* syntax, TILE-Gx: TILE-Gx Syntax. (line 6)
* syntax, TILEPro: TILEPro Syntax. (line 6)
* syntax, XGATE: XGATE-Syntax. (line 6)
* syntax, Xtensa assembler: Xtensa Syntax. (line 6)
* 'sysproc' directive, i960: Directives-i960. (line 37)
* tab ('\t'): Strings. (line 27)
* 'tab' directive, TIC54X: TIC54X-Directives. (line 245)
* 'tag' directive: Tag. (line 6)
* 'tag' directive, TIC54X: TIC54X-Directives. (line 214)
* 'tag' directive, TIC54X <1>: TIC54X-Directives. (line 248)
* TBM, i386: i386-TBM. (line 6)
* TBM, x86-64: i386-TBM. (line 6)
* 'tdaoff' pseudo-op, V850: V850 Opcodes. (line 81)
* temporary symbol names: Symbol Names. (line 40)
* text and data sections, joining: R. (line 6)
* 'text' directive: Text. (line 6)
* text section: Ld Sections. (line 9)
* 'tfloat' directive, i386: i386-Float. (line 14)
* 'tfloat' directive, x86-64: i386-Float. (line 14)
* Thumb support: ARM-Dependent. (line 6)
* TIC54X builtin math functions: TIC54X-Builtins. (line 6)
* TIC54X line comment character: TIC54X-Chars. (line 6)
* TIC54X line separator: TIC54X-Chars. (line 17)
* TIC54X machine directives: TIC54X-Directives. (line 6)
* TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6)
* TIC54X options: TIC54X-Opts. (line 6)
* TIC54X subsym builtins: TIC54X-Macros. (line 16)
* TIC54X support: TIC54X-Dependent. (line 6)
* TIC54X-specific macros: TIC54X-Macros. (line 6)
* TIC6X big-endian output: TIC6X Options. (line 46)
* TIC6X line comment character: TIC6X Syntax. (line 6)
* TIC6X line separator: TIC6X Syntax. (line 13)
* TIC6X little-endian output: TIC6X Options. (line 46)
* TIC6X machine directives: TIC6X Directives. (line 6)
* TIC6X options: TIC6X Options. (line 6)
* TIC6X support: TIC6X-Dependent. (line 6)
* TILE-Gx machine directives: TILE-Gx Directives. (line 6)
* TILE-Gx modifiers: TILE-Gx Modifiers. (line 6)
* TILE-Gx opcode names: TILE-Gx Opcodes. (line 6)
* TILE-Gx register names: TILE-Gx Registers. (line 6)
* TILE-Gx support: TILE-Gx-Dependent. (line 6)
* TILE-Gx syntax: TILE-Gx Syntax. (line 6)
* TILEPro machine directives: TILEPro Directives. (line 6)
* TILEPro modifiers: TILEPro Modifiers. (line 6)
* TILEPro opcode names: TILEPro Opcodes. (line 6)
* TILEPro register names: TILEPro Registers. (line 6)
* TILEPro support: TILEPro-Dependent. (line 6)
* TILEPro syntax: TILEPro Syntax. (line 6)
* time, total for assembly: statistics. (line 6)
* 'title' directive: Title. (line 6)
* 'tls_gd' directive, Nios II: Nios II Relocations. (line 38)
* 'tls_ie' directive, Nios II: Nios II Relocations. (line 38)
* 'tls_ldm' directive, Nios II: Nios II Relocations. (line 38)
* 'tls_ldo' directive, Nios II: Nios II Relocations. (line 38)
* 'tls_le' directive, Nios II: Nios II Relocations. (line 38)
* TMS320C6X support: TIC6X-Dependent. (line 6)
* 'tp' register, V850: V850-Regs. (line 16)
* 'transform' directive: Transform Directive. (line 6)
* trusted compiler: f. (line 6)
* turning preprocessing on and off: Preprocessing. (line 26)
* 'type' directive (COFF version): Type. (line 11)
* 'type' directive (ELF version): Type. (line 22)
* type of a symbol: Symbol Type. (line 6)
* 'ualong' directive, SH: SH Directives. (line 6)
* 'uaquad' directive, SH: SH Directives. (line 6)
* 'uaword' directive, SH: SH Directives. (line 6)
* 'ubyte' directive, TIC54X: TIC54X-Directives. (line 34)
* 'uchar' directive, TIC54X: TIC54X-Directives. (line 34)
* 'uhalf' directive, TIC54X: TIC54X-Directives. (line 109)
* 'uint' directive, TIC54X: TIC54X-Directives. (line 109)
* 'uleb128' directive: Uleb128. (line 6)
* 'ulong' directive, TIC54X: TIC54X-Directives. (line 133)
* undefined section: Ld Sections. (line 36)
* 'union' directive, TIC54X: TIC54X-Directives. (line 248)
* unsegm: Z8000 Directives. (line 14)
* 'usect' directive, TIC54X: TIC54X-Directives. (line 260)
* 'ushort' directive, TIC54X: TIC54X-Directives. (line 109)
* 'uword' directive, TIC54X: TIC54X-Directives. (line 109)
* V850 command line options: V850 Options. (line 9)
* V850 floating point (IEEE): V850 Floating Point. (line 6)
* V850 line comment character: V850-Chars. (line 6)
* V850 line separator: V850-Chars. (line 13)
* V850 machine directives: V850 Directives. (line 6)
* V850 opcodes: V850 Opcodes. (line 6)
* V850 options (none): V850 Options. (line 6)
* V850 register names: V850-Regs. (line 6)
* V850 support: V850-Dependent. (line 6)
* 'val' directive: Val. (line 6)
* value attribute, COFF: Val. (line 6)
* value of a symbol: Symbol Value. (line 6)
* 'var' directive, TIC54X: TIC54X-Directives. (line 270)
* VAX bitfields not supported: VAX-no. (line 6)
* VAX branch improvement: VAX-branch. (line 6)
* VAX command-line options ignored: VAX-Opts. (line 6)
* VAX displacement sizing character: VAX-operands. (line 12)
* VAX floating point: VAX-float. (line 6)
* VAX immediate character: VAX-operands. (line 6)
* VAX indirect character: VAX-operands. (line 9)
* VAX line comment character: VAX-Chars. (line 6)
* VAX line separator: VAX-Chars. (line 14)
* VAX machine directives: VAX-directives. (line 6)
* VAX opcode mnemonics: VAX-opcodes. (line 6)
* VAX operand notation: VAX-operands. (line 6)
* VAX register names: VAX-operands. (line 17)
* VAX support: Vax-Dependent. (line 6)
* Vax-11 C compatibility: VAX-Opts. (line 42)
* VAX/VMS options: VAX-Opts. (line 42)
* 'version' directive: Version. (line 6)
* 'version' directive, TIC54X: TIC54X-Directives. (line 274)
* version of assembler: v. (line 6)
* versions of symbols: Symver. (line 6)
* Virtualization instruction generation override: MIPS ASE Instruction Generation Overrides.
(line 46)
* visibility: Hidden. (line 6)
* visibility <1>: Internal. (line 6)
* visibility <2>: Protected. (line 6)
* VMS (VAX) options: VAX-Opts. (line 42)
* 'vtable_entry' directive: VTableEntry. (line 6)
* 'vtable_inherit' directive: VTableInherit. (line 6)
* warning directive: Warning. (line 6)
* warning for altered difference tables: K. (line 6)
* warning messages: Errors. (line 6)
* warnings, causing error: W. (line 16)
* warnings, M32R: M32R-Warnings. (line 6)
* warnings, suppressing: W. (line 11)
* warnings, switching on: W. (line 19)
* 'weak' directive: Weak. (line 6)
* 'weakref' directive: Weakref. (line 6)
* whitespace: Whitespace. (line 6)
* whitespace, removed by preprocessor: Preprocessing. (line 7)
* wide floating point directives, VAX: VAX-directives. (line 9)
* 'width' directive, TIC54X: TIC54X-Directives. (line 125)
* Width of continuation lines of disassembly output: listing. (line 21)
* Width of first line disassembly output: listing. (line 16)
* Width of source line output: listing. (line 28)
* 'wmsg' directive, TIC54X: TIC54X-Directives. (line 75)
* 'word' directive: Word. (line 6)
* 'word' directive, ARC: ARC Directives. (line 162)
* 'word' directive, H8/300: H8/300 Directives. (line 6)
* 'word' directive, i386: i386-Float. (line 21)
* 'word' directive, Nios II: Nios II Directives. (line 13)
* 'word' directive, SPARC: Sparc-Directives. (line 51)
* 'word' directive, TIC54X: TIC54X-Directives. (line 109)
* 'word' directive, x86-64: i386-Float. (line 21)
* writing patterns in memory: Fill. (line 6)
* wval: Z8000 Directives. (line 24)
* x86 machine directives: i386-Directives. (line 6)
* x86-64 arch directive: i386-Arch. (line 6)
* x86-64 att_syntax pseudo op: i386-Variations. (line 6)
* x86-64 conversion instructions: i386-Mnemonics. (line 36)
* x86-64 floating point: i386-Float. (line 6)
* x86-64 immediate operands: i386-Variations. (line 15)
* x86-64 instruction naming: i386-Mnemonics. (line 6)
* x86-64 intel_syntax pseudo op: i386-Variations. (line 6)
* x86-64 jump optimization: i386-Jumps. (line 6)
* x86-64 jump, call, return: i386-Variations. (line 40)
* x86-64 jump/call operands: i386-Variations. (line 15)
* x86-64 memory references: i386-Memory. (line 6)
* x86-64 options: i386-Options. (line 6)
* x86-64 register operands: i386-Variations. (line 15)
* x86-64 registers: i386-Regs. (line 6)
* x86-64 sections: i386-Variations. (line 46)
* x86-64 size suffixes: i386-Variations. (line 28)
* x86-64 source, destination operands: i386-Variations. (line 21)
* x86-64 support: i386-Dependent. (line 6)
* x86-64 syntax compatibility: i386-Variations. (line 6)
* 'xfloat' directive, TIC54X: TIC54X-Directives. (line 62)
* XGATE addressing modes: XGATE-Syntax. (line 28)
* XGATE assembler directives: XGATE-Directives. (line 6)
* XGATE floating point: XGATE-Float. (line 6)
* XGATE line comment character: XGATE-Syntax. (line 16)
* XGATE line separator: XGATE-Syntax. (line 25)
* XGATE opcodes: XGATE-opcodes. (line 6)
* XGATE options: XGATE-Opts. (line 6)
* XGATE support: XGATE-Dependent. (line 6)
* XGATE syntax: XGATE-Syntax. (line 6)
* 'xlong' directive, TIC54X: TIC54X-Directives. (line 133)
* XStormy16 comment character: XStormy16-Chars. (line 11)
* XStormy16 line comment character: XStormy16-Chars. (line 6)
* XStormy16 line separator: XStormy16-Chars. (line 14)
* XStormy16 machine directives: XStormy16 Directives.
(line 6)
* XStormy16 pseudo-opcodes: XStormy16 Opcodes. (line 6)
* XStormy16 support: XSTORMY16-Dependent. (line 6)
* Xtensa architecture: Xtensa-Dependent. (line 6)
* Xtensa assembler syntax: Xtensa Syntax. (line 6)
* Xtensa directives: Xtensa Directives. (line 6)
* Xtensa opcode names: Xtensa Opcodes. (line 6)
* Xtensa register names: Xtensa Registers. (line 6)
* 'xword' directive, SPARC: Sparc-Directives. (line 55)
* Z80 $: Z80-Chars. (line 15)
* Z80 ': Z80-Chars. (line 20)
* Z80 floating point: Z80 Floating Point. (line 6)
* Z80 line comment character: Z80-Chars. (line 6)
* Z80 line separator: Z80-Chars. (line 13)
* Z80 options: Z80 Options. (line 6)
* Z80 registers: Z80-Regs. (line 6)
* Z80 support: Z80-Dependent. (line 6)
* Z80 Syntax: Z80 Options. (line 40)
* Z80, case sensitivity: Z80-Case. (line 6)
* Z80, \: Z80-Chars. (line 18)
* Z80-only directives: Z80 Directives. (line 9)
* Z800 addressing modes: Z8000-Addressing. (line 6)
* Z8000 directives: Z8000 Directives. (line 6)
* Z8000 line comment character: Z8000-Chars. (line 6)
* Z8000 line separator: Z8000-Chars. (line 13)
* Z8000 opcode summary: Z8000 Opcodes. (line 6)
* Z8000 options: Z8000 Options. (line 6)
* Z8000 registers: Z8000-Regs. (line 6)
* Z8000 support: Z8000-Dependent. (line 6)
* 'zdaoff' pseudo-op, V850: V850 Opcodes. (line 98)
* 'zero' register, V850: V850-Regs. (line 7)
* zero-terminated strings: Asciz. (line 6)