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 <a name="ARM-Opcodes"></a>
 <div class="header">
 <p>
 Next: <a href="ARM-Mapping-Symbols.html#ARM-Mapping-Symbols" accesskey="n" rel="next">ARM Mapping Symbols</a>, Previous: <a href="ARM-Directives.html#ARM-Directives" accesskey="p" rel="prev">ARM Directives</a>, Up: <a href="ARM_002dDependent.html#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
 </div>
 <hr>
 <a name="Opcodes-3"></a>
 <h4 class="subsection">9.4.5 Opcodes</h4>

 <a name="index-ARM-opcodes"></a>
 <a name="index-opcodes-for-ARM"></a>
 <p><code>as</code> implements all the standard ARM opcodes.  It also
 implements several pseudo opcodes, including several synthetic load
 instructions.
 </p>
 <dl compact="compact">
 <dd>
 <a name="index-NOP-pseudo-op_002c-ARM"></a>
 </dd>
 <dt><code>NOP</code></dt>
 <dd><div class="smallexample">
 <pre class="smallexample">  nop
 </pre></div>

 <p>This pseudo op will always evaluate to a legal ARM instruction that does
 nothing.  Currently it will evaluate to MOV r0, r0.
 </p>
 <a name="index-LDR-reg_002c_003d_003clabel_003e-pseudo-op_002c-ARM"></a>
 </dd>
 <dt><code>LDR</code></dt>
 <dd><div class="smallexample">
 <pre class="smallexample">  ldr &lt;register&gt; , = &lt;expression&gt;
 </pre></div>

 <p>If expression evaluates to a numeric constant then a MOV or MVN
 instruction will be used in place of the LDR instruction, if the
 constant can be generated by either of these instructions.  Otherwise
 the constant will be placed into the nearest literal pool (if it not
 already there) and a PC relative LDR instruction will be generated.
 </p>
 <a name="index-ADR-reg_002c_003clabel_003e-pseudo-op_002c-ARM"></a>
 </dd>
 <dt><code>ADR</code></dt>
 <dd><div class="smallexample">
 <pre class="smallexample">  adr &lt;register&gt; &lt;label&gt;
 </pre></div>

 <p>This instruction will load the address of <var>label</var> into the indicated
 register.  The instruction will evaluate to a PC relative ADD or SUB
 instruction depending upon where the label is located.  If the label is
 out of range, or if it is not defined in the same file (and section) as
 the ADR instruction, then an error will be generated.  This instruction
 will not make use of the literal pool.
 </p>
 <a name="index-ADRL-reg_002c_003clabel_003e-pseudo-op_002c-ARM"></a>
 </dd>
 <dt><code>ADRL</code></dt>
 <dd><div class="smallexample">
 <pre class="smallexample">  adrl &lt;register&gt; &lt;label&gt;
 </pre></div>

 <p>This instruction will load the address of <var>label</var> into the indicated
 register.  The instruction will evaluate to one or two PC relative ADD
 or SUB instructions depending upon where the label is located.  If a
 second instruction is not needed a NOP instruction will be generated in
 its place, so that this instruction is always 8 bytes long.
 </p>
 <p>If the label is out of range, or if it is not defined in the same file
 (and section) as the ADRL instruction, then an error will be generated.
 This instruction will not make use of the literal pool.
 </p>
 </dd>
 </dl>

 <p>For information on the ARM or Thumb instruction sets, see <cite>ARM
 Software Development Toolkit Reference Manual</cite>, Advanced RISC Machines
 Ltd.
 </p>
 <hr>
 <div class="header">
 <p>
 Next: <a href="ARM-Mapping-Symbols.html#ARM-Mapping-Symbols" accesskey="n" rel="next">ARM Mapping Symbols</a>, Previous: <a href="ARM-Directives.html#ARM-Directives" accesskey="p" rel="prev">ARM Directives</a>, Up: <a href="ARM_002dDependent.html#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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	<a name="ARM-Opcodes"></a>
	<div class="header">
	<p>
	Next: <a href="ARM-Mapping-Symbols.html#ARM-Mapping-Symbols" accesskey="n" rel="next">ARM Mapping Symbols</a>, Previous: <a href="ARM-Directives.html#ARM-Directives" accesskey="p" rel="prev">ARM Directives</a>, Up: <a href="ARM_002dDependent.html#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a>   [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
	</div>
	<hr>
	<a name="Opcodes-3"></a>
	<h4 class="subsection">9.4.5 Opcodes</h4>

	<a name="index-ARM-opcodes"></a>
	<a name="index-opcodes-for-ARM"></a>
	<p><code>as</code> implements all the standard ARM opcodes. It also
	implements several pseudo opcodes, including several synthetic load
	instructions.
	</p>
	<dl compact="compact">
	<dd>
	<a name="index-NOP-pseudo-op_002c-ARM"></a>
	</dd>
	<dt><code>NOP</code></dt>
	<dd><div class="smallexample">
	<pre class="smallexample"> nop
	</pre></div>

	<p>This pseudo op will always evaluate to a legal ARM instruction that does
	nothing. Currently it will evaluate to MOV r0, r0.
	</p>
	<a name="index-LDR-reg_002c_003d_003clabel_003e-pseudo-op_002c-ARM"></a>
	</dd>
	<dt><code>LDR</code></dt>
	<dd><div class="smallexample">
	<pre class="smallexample"> ldr <register> , = <expression>
	</pre></div>

	<p>If expression evaluates to a numeric constant then a MOV or MVN
	instruction will be used in place of the LDR instruction, if the
	constant can be generated by either of these instructions. Otherwise
	the constant will be placed into the nearest literal pool (if it not
	already there) and a PC relative LDR instruction will be generated.
	</p>
	<a name="index-ADR-reg_002c_003clabel_003e-pseudo-op_002c-ARM"></a>
	</dd>
	<dt><code>ADR</code></dt>
	<dd><div class="smallexample">
	<pre class="smallexample"> adr <register> <label>
	</pre></div>

	<p>This instruction will load the address of <var>label</var> into the indicated
	register. The instruction will evaluate to a PC relative ADD or SUB
	instruction depending upon where the label is located. If the label is
	out of range, or if it is not defined in the same file (and section) as
	the ADR instruction, then an error will be generated. This instruction
	will not make use of the literal pool.
	</p>
	<a name="index-ADRL-reg_002c_003clabel_003e-pseudo-op_002c-ARM"></a>
	</dd>
	<dt><code>ADRL</code></dt>
	<dd><div class="smallexample">
	<pre class="smallexample"> adrl <register> <label>
	</pre></div>

	<p>This instruction will load the address of <var>label</var> into the indicated
	register. The instruction will evaluate to one or two PC relative ADD
	or SUB instructions depending upon where the label is located. If a
	second instruction is not needed a NOP instruction will be generated in
	its place, so that this instruction is always 8 bytes long.
	</p>
	<p>If the label is out of range, or if it is not defined in the same file
	(and section) as the ADRL instruction, then an error will be generated.
	This instruction will not make use of the literal pool.
	</p>
	</dd>
	</dl>

	<p>For information on the ARM or Thumb instruction sets, see <cite>ARM
	Software Development Toolkit Reference Manual</cite>, Advanced RISC Machines
	Ltd.
	</p>
	<hr>
	<div class="header">
	<p>
	Next: <a href="ARM-Mapping-Symbols.html#ARM-Mapping-Symbols" accesskey="n" rel="next">ARM Mapping Symbols</a>, Previous: <a href="ARM-Directives.html#ARM-Directives" accesskey="p" rel="prev">ARM Directives</a>, Up: <a href="ARM_002dDependent.html#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a>   [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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