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 <a name="i386_002dOptions"></a>
 <div class="header">
 <p>
 Next: <a href="i386_002dDirectives.html#i386_002dDirectives" accesskey="n" rel="next">i386-Directives</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
 </div>
 <hr>
 <a name="Options-10"></a>
 <h4 class="subsection">9.15.1 Options</h4>

 <a name="index-options-for-i386"></a>
 <a name="index-options-for-x86_002d64"></a>
 <a name="index-i386-options"></a>
 <a name="index-x86_002d64-options"></a>

 <p>The i386 version of <code>as</code> has a few machine
 dependent options:
 </p>
 <dl compact="compact">
 <dd><a name="index-_002d_002d32-option_002c-i386"></a>
 <a name="index-_002d_002d32-option_002c-x86_002d64"></a>
 <a name="index-_002d_002dx32-option_002c-i386"></a>
 <a name="index-_002d_002dx32-option_002c-x86_002d64"></a>
 <a name="index-_002d_002d64-option_002c-i386"></a>
 <a name="index-_002d_002d64-option_002c-x86_002d64"></a>
 </dd>
 <dt><code>--32 | --x32 | --64</code></dt>
 <dd><p>Select the word size, either 32 bits or 64 bits.  &lsquo;<samp>--32</samp>&rsquo;
 implies Intel i386 architecture, while &lsquo;<samp>--x32</samp>&rsquo; and &lsquo;<samp>--64</samp>&rsquo;
 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
 respectively.
 </p>
 <p>These options are only available with the ELF object file format, and
 require that the necessary BFD support has been included (on a 32-bit
 platform you have to add &ndash;enable-64-bit-bfd to configure enable 64-bit
 usage and use x86-64 as target platform).
 </p>
 </dd>
 <dt><code>-n</code></dt>
 <dd><p>By default, x86 GAS replaces multiple nop instructions used for
 alignment within code sections with multi-byte nop instructions such
 as leal 0(%esi,1),%esi.  This switch disables the optimization.
 </p>
 <a name="index-_002d_002ddivide-option_002c-i386"></a>
 </dd>
 <dt><code>--divide</code></dt>
 <dd><p>On SVR4-derived platforms, the character &lsquo;<samp>/</samp>&rsquo; is treated as a comment
 character, which means that it cannot be used in expressions.  The
 &lsquo;<samp>--divide</samp>&rsquo; option turns &lsquo;<samp>/</samp>&rsquo; into a normal character.  This does
 not disable &lsquo;<samp>/</samp>&rsquo; at the beginning of a line starting a comment, or
 affect using &lsquo;<samp>#</samp>&rsquo; for starting a comment.
 </p>
 <a name="index-_002dmarch_003d-option_002c-i386"></a>
 <a name="index-_002dmarch_003d-option_002c-x86_002d64"></a>
 </dd>
 <dt><code>-march=<var>CPU</var>[+<var>EXTENSION</var>&hellip;]</code></dt>
 <dd><p>This option specifies the target processor.  The assembler will
 issue an error message if an attempt is made to assemble an instruction
 which will not execute on the target processor.  The following
 processor names are recognized:
 <code>i8086</code>,
 <code>i186</code>,
 <code>i286</code>,
 <code>i386</code>,
 <code>i486</code>,
 <code>i586</code>,
 <code>i686</code>,
 <code>pentium</code>,
 <code>pentiumpro</code>,
 <code>pentiumii</code>,
 <code>pentiumiii</code>,
 <code>pentium4</code>,
 <code>prescott</code>,
 <code>nocona</code>,
 <code>core</code>,
 <code>core2</code>,
 <code>corei7</code>,
 <code>l1om</code>,
 <code>k1om</code>,
 <code>k6</code>,
 <code>k6_2</code>,
 <code>athlon</code>,
 <code>opteron</code>,
 <code>k8</code>,
 <code>amdfam10</code>,
 <code>bdver1</code>,
 <code>bdver2</code>,
 <code>bdver3</code>,
 <code>btver1</code>,
 <code>btver2</code>,
 <code>generic32</code> and
 <code>generic64</code>.
 </p>
 <p>In addition to the basic instruction set, the assembler can be told to
 accept various extension mnemonics.  For example,
 <code>-march=i686+sse4+vmx</code> extends <var>i686</var> with <var>sse4</var> and
 <var>vmx</var>.  The following extensions are currently supported:
 <code>8087</code>,
 <code>287</code>,
 <code>387</code>,
 <code>no87</code>,
 <code>mmx</code>,
 <code>nommx</code>,
 <code>sse</code>,
 <code>sse2</code>,
 <code>sse3</code>,
 <code>ssse3</code>,
 <code>sse4.1</code>,
 <code>sse4.2</code>,
 <code>sse4</code>,
 <code>nosse</code>,
 <code>avx</code>,
 <code>avx2</code>,
 <code>adx</code>,
 <code>rdseed</code>,
 <code>prfchw</code>,
 <code>smap</code>,
 <code>mpx</code>,
 <code>sha</code>,
 <code>avx512f</code>,
 <code>avx512cd</code>,
 <code>avx512er</code>,
 <code>avx512pf</code>,
 <code>noavx</code>,
 <code>vmx</code>,
 <code>vmfunc</code>,
 <code>smx</code>,
 <code>xsave</code>,
 <code>xsaveopt</code>,
 <code>aes</code>,
 <code>pclmul</code>,
 <code>fsgsbase</code>,
 <code>rdrnd</code>,
 <code>f16c</code>,
 <code>bmi2</code>,
 <code>fma</code>,
 <code>movbe</code>,
 <code>ept</code>,
 <code>lzcnt</code>,
 <code>hle</code>,
 <code>rtm</code>,
 <code>invpcid</code>,
 <code>clflush</code>,
 <code>lwp</code>,
 <code>fma4</code>,
 <code>xop</code>,
 <code>cx16</code>,
 <code>syscall</code>,
 <code>rdtscp</code>,
 <code>3dnow</code>,
 <code>3dnowa</code>,
 <code>sse4a</code>,
 <code>sse5</code>,
 <code>svme</code>,
 <code>abm</code> and
 <code>padlock</code>.
 Note that rather than extending a basic instruction set, the extension
 mnemonics starting with <code>no</code> revoke the respective functionality.
 </p>
 <p>When the <code>.arch</code> directive is used with <samp>-march</samp>, the
 <code>.arch</code> directive will take precedent.
 </p>
 <a name="index-_002dmtune_003d-option_002c-i386"></a>
 <a name="index-_002dmtune_003d-option_002c-x86_002d64"></a>
 </dd>
 <dt><code>-mtune=<var>CPU</var></code></dt>
 <dd><p>This option specifies a processor to optimize for. When used in
 conjunction with the <samp>-march</samp> option, only instructions
 of the processor specified by the <samp>-march</samp> option will be
 generated.
 </p>
 <p>Valid <var>CPU</var> values are identical to the processor list of
 <samp>-march=<var>CPU</var></samp>.
 </p>
 <a name="index-_002dmsse2avx-option_002c-i386"></a>
 <a name="index-_002dmsse2avx-option_002c-x86_002d64"></a>
 </dd>
 <dt><code>-msse2avx</code></dt>
 <dd><p>This option specifies that the assembler should encode SSE instructions
 with VEX prefix.
 </p>
 <a name="index-_002dmsse_002dcheck_003d-option_002c-i386"></a>
 <a name="index-_002dmsse_002dcheck_003d-option_002c-x86_002d64"></a>
 </dd>
 <dt><code>-msse-check=<var>none</var></code></dt>
 <dt><code>-msse-check=<var>warning</var></code></dt>
 <dt><code>-msse-check=<var>error</var></code></dt>
 <dd><p>These options control if the assembler should check SSE instructions.
 <samp>-msse-check=<var>none</var></samp> will make the assembler not to check SSE
 instructions,  which is the default.  <samp>-msse-check=<var>warning</var></samp>
 will make the assembler issue a warning for any SSE instruction.
 <samp>-msse-check=<var>error</var></samp> will make the assembler issue an error
 for any SSE instruction.
 </p>
 <a name="index-_002dmavxscalar_003d-option_002c-i386"></a>
 <a name="index-_002dmavxscalar_003d-option_002c-x86_002d64"></a>
 </dd>
 <dt><code>-mavxscalar=<var>128</var></code></dt>
 <dt><code>-mavxscalar=<var>256</var></code></dt>
 <dd><p>These options control how the assembler should encode scalar AVX
 instructions.  <samp>-mavxscalar=<var>128</var></samp> will encode scalar
 AVX instructions with 128bit vector length, which is the default.
 <samp>-mavxscalar=<var>256</var></samp> will encode scalar AVX instructions
 with 256bit vector length.
 </p>
 <a name="index-_002dmevexlig_003d-option_002c-i386"></a>
 <a name="index-_002dmevexlig_003d-option_002c-x86_002d64"></a>
 </dd>
 <dt><code>-mevexlig=<var>128</var></code></dt>
 <dt><code>-mevexlig=<var>256</var></code></dt>
 <dt><code>-mevexlig=<var>512</var></code></dt>
 <dd><p>These options control how the assembler should encode length-ignored
 (LIG) EVEX instructions.  <samp>-mevexlig=<var>128</var></samp> will encode LIG
 EVEX instructions with 128bit vector length, which is the default.
 <samp>-mevexlig=<var>256</var></samp> and <samp>-mevexlig=<var>512</var></samp> will
 encode LIG EVEX instructions with 256bit and 512bit vector length,
 respectively.
 </p>
 <a name="index-_002dmevexwig_003d-option_002c-i386"></a>
 <a name="index-_002dmevexwig_003d-option_002c-x86_002d64"></a>
 </dd>
 <dt><code>-mevexwig=<var>0</var></code></dt>
 <dt><code>-mevexwig=<var>1</var></code></dt>
 <dd><p>These options control how the assembler should encode w-ignored (WIG)
 EVEX instructions.  <samp>-mevexwig=<var>0</var></samp> will encode WIG
 EVEX instructions with evex.w = 0, which is the default.
 <samp>-mevexwig=<var>1</var></samp> will encode WIG EVEX instructions with
 evex.w = 1.
 </p>
 <a name="index-_002dmmnemonic_003d-option_002c-i386"></a>
 <a name="index-_002dmmnemonic_003d-option_002c-x86_002d64"></a>
 </dd>
 <dt><code>-mmnemonic=<var>att</var></code></dt>
 <dt><code>-mmnemonic=<var>intel</var></code></dt>
 <dd><p>This option specifies instruction mnemonic for matching instructions.
 The <code>.att_mnemonic</code> and <code>.intel_mnemonic</code> directives will
 take precedent.
 </p>
 <a name="index-_002dmsyntax_003d-option_002c-i386"></a>
 <a name="index-_002dmsyntax_003d-option_002c-x86_002d64"></a>
 </dd>
 <dt><code>-msyntax=<var>att</var></code></dt>
 <dt><code>-msyntax=<var>intel</var></code></dt>
 <dd><p>This option specifies instruction syntax when processing instructions.
 The <code>.att_syntax</code> and <code>.intel_syntax</code> directives will
 take precedent.
 </p>
 <a name="index-_002dmnaked_002dreg-option_002c-i386"></a>
 <a name="index-_002dmnaked_002dreg-option_002c-x86_002d64"></a>
 </dd>
 <dt><code>-mnaked-reg</code></dt>
 <dd><p>This opetion specifies that registers don&rsquo;t require a &lsquo;<samp>%</samp>&rsquo; prefix.
 The <code>.att_syntax</code> and <code>.intel_syntax</code> directives will take precedent.
 </p>
 <a name="index-_002dmadd_002dbnd_002dprefix-option_002c-i386"></a>
 <a name="index-_002dmadd_002dbnd_002dprefix-option_002c-x86_002d64"></a>
 </dd>
 <dt><code>-madd-bnd-prefix</code></dt>
 <dd><p>This option forces the assembler to add BND prefix to all branches, even
 if such prefix was not explicitly specified in the source code.
 </p>
 </dd>
 </dl>

 <hr>
 <div class="header">
 <p>
 Next: <a href="i386_002dDirectives.html#i386_002dDirectives" accesskey="n" rel="next">i386-Directives</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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	<a name="i386_002dOptions"></a>
	<div class="header">
	<p>
	Next: <a href="i386_002dDirectives.html#i386_002dDirectives" accesskey="n" rel="next">i386-Directives</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a>   [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
	</div>
	<hr>
	<a name="Options-10"></a>
	<h4 class="subsection">9.15.1 Options</h4>

	<a name="index-options-for-i386"></a>
	<a name="index-options-for-x86_002d64"></a>
	<a name="index-i386-options"></a>
	<a name="index-x86_002d64-options"></a>

	<p>The i386 version of <code>as</code> has a few machine
	dependent options:
	</p>
	<dl compact="compact">
	<dd><a name="index-_002d_002d32-option_002c-i386"></a>
	<a name="index-_002d_002d32-option_002c-x86_002d64"></a>
	<a name="index-_002d_002dx32-option_002c-i386"></a>
	<a name="index-_002d_002dx32-option_002c-x86_002d64"></a>
	<a name="index-_002d_002d64-option_002c-i386"></a>
	<a name="index-_002d_002d64-option_002c-x86_002d64"></a>
	</dd>
	<dt><code>--32 \| --x32 \| --64</code></dt>
	<dd><p>Select the word size, either 32 bits or 64 bits. ‘<samp>--32</samp>’
	implies Intel i386 architecture, while ‘<samp>--x32</samp>’ and ‘<samp>--64</samp>’
	imply AMD x86-64 architecture with 32-bit or 64-bit word-size
	respectively.
	</p>
	<p>These options are only available with the ELF object file format, and
	require that the necessary BFD support has been included (on a 32-bit
	platform you have to add –enable-64-bit-bfd to configure enable 64-bit
	usage and use x86-64 as target platform).
	</p>
	</dd>
	<dt><code>-n</code></dt>
	<dd><p>By default, x86 GAS replaces multiple nop instructions used for
	alignment within code sections with multi-byte nop instructions such
	as leal 0(%esi,1),%esi. This switch disables the optimization.
	</p>
	<a name="index-_002d_002ddivide-option_002c-i386"></a>
	</dd>
	<dt><code>--divide</code></dt>
	<dd><p>On SVR4-derived platforms, the character ‘<samp>/</samp>’ is treated as a comment
	character, which means that it cannot be used in expressions. The
	‘<samp>--divide</samp>’ option turns ‘<samp>/</samp>’ into a normal character. This does
	not disable ‘<samp>/</samp>’ at the beginning of a line starting a comment, or
	affect using ‘<samp>#</samp>’ for starting a comment.
	</p>
	<a name="index-_002dmarch_003d-option_002c-i386"></a>
	<a name="index-_002dmarch_003d-option_002c-x86_002d64"></a>
	</dd>
	<dt><code>-march=<var>CPU</var>[+<var>EXTENSION</var>…]</code></dt>
	<dd><p>This option specifies the target processor. The assembler will
	issue an error message if an attempt is made to assemble an instruction
	which will not execute on the target processor. The following
	processor names are recognized:
	<code>i8086</code>,
	<code>i186</code>,
	<code>i286</code>,
	<code>i386</code>,
	<code>i486</code>,
	<code>i586</code>,
	<code>i686</code>,
	<code>pentium</code>,
	<code>pentiumpro</code>,
	<code>pentiumii</code>,
	<code>pentiumiii</code>,
	<code>pentium4</code>,
	<code>prescott</code>,
	<code>nocona</code>,
	<code>core</code>,
	<code>core2</code>,
	<code>corei7</code>,
	<code>l1om</code>,
	<code>k1om</code>,
	<code>k6</code>,
	<code>k6_2</code>,
	<code>athlon</code>,
	<code>opteron</code>,
	<code>k8</code>,
	<code>amdfam10</code>,
	<code>bdver1</code>,
	<code>bdver2</code>,
	<code>bdver3</code>,
	<code>btver1</code>,
	<code>btver2</code>,
	<code>generic32</code> and
	<code>generic64</code>.
	</p>
	<p>In addition to the basic instruction set, the assembler can be told to
	accept various extension mnemonics. For example,
	<code>-march=i686+sse4+vmx</code> extends <var>i686</var> with <var>sse4</var> and
	<var>vmx</var>. The following extensions are currently supported:
	<code>8087</code>,
	<code>287</code>,
	<code>387</code>,
	<code>no87</code>,
	<code>mmx</code>,
	<code>nommx</code>,
	<code>sse</code>,
	<code>sse2</code>,
	<code>sse3</code>,
	<code>ssse3</code>,
	<code>sse4.1</code>,
	<code>sse4.2</code>,
	<code>sse4</code>,
	<code>nosse</code>,
	<code>avx</code>,
	<code>avx2</code>,
	<code>adx</code>,
	<code>rdseed</code>,
	<code>prfchw</code>,
	<code>smap</code>,
	<code>mpx</code>,
	<code>sha</code>,
	<code>avx512f</code>,
	<code>avx512cd</code>,
	<code>avx512er</code>,
	<code>avx512pf</code>,
	<code>noavx</code>,
	<code>vmx</code>,
	<code>vmfunc</code>,
	<code>smx</code>,
	<code>xsave</code>,
	<code>xsaveopt</code>,
	<code>aes</code>,
	<code>pclmul</code>,
	<code>fsgsbase</code>,
	<code>rdrnd</code>,
	<code>f16c</code>,
	<code>bmi2</code>,
	<code>fma</code>,
	<code>movbe</code>,
	<code>ept</code>,
	<code>lzcnt</code>,
	<code>hle</code>,
	<code>rtm</code>,
	<code>invpcid</code>,
	<code>clflush</code>,
	<code>lwp</code>,
	<code>fma4</code>,
	<code>xop</code>,
	<code>cx16</code>,
	<code>syscall</code>,
	<code>rdtscp</code>,
	<code>3dnow</code>,
	<code>3dnowa</code>,
	<code>sse4a</code>,
	<code>sse5</code>,
	<code>svme</code>,
	<code>abm</code> and
	<code>padlock</code>.
	Note that rather than extending a basic instruction set, the extension
	mnemonics starting with <code>no</code> revoke the respective functionality.
	</p>
	<p>When the <code>.arch</code> directive is used with <samp>-march</samp>, the
	<code>.arch</code> directive will take precedent.
	</p>
	<a name="index-_002dmtune_003d-option_002c-i386"></a>
	<a name="index-_002dmtune_003d-option_002c-x86_002d64"></a>
	</dd>
	<dt><code>-mtune=<var>CPU</var></code></dt>
	<dd><p>This option specifies a processor to optimize for. When used in
	conjunction with the <samp>-march</samp> option, only instructions
	of the processor specified by the <samp>-march</samp> option will be
	generated.
	</p>
	<p>Valid <var>CPU</var> values are identical to the processor list of
	<samp>-march=<var>CPU</var></samp>.
	</p>
	<a name="index-_002dmsse2avx-option_002c-i386"></a>
	<a name="index-_002dmsse2avx-option_002c-x86_002d64"></a>
	</dd>
	<dt><code>-msse2avx</code></dt>
	<dd><p>This option specifies that the assembler should encode SSE instructions
	with VEX prefix.
	</p>
	<a name="index-_002dmsse_002dcheck_003d-option_002c-i386"></a>
	<a name="index-_002dmsse_002dcheck_003d-option_002c-x86_002d64"></a>
	</dd>
	<dt><code>-msse-check=<var>none</var></code></dt>
	<dt><code>-msse-check=<var>warning</var></code></dt>
	<dt><code>-msse-check=<var>error</var></code></dt>
	<dd><p>These options control if the assembler should check SSE instructions.
	<samp>-msse-check=<var>none</var></samp> will make the assembler not to check SSE
	instructions, which is the default. <samp>-msse-check=<var>warning</var></samp>
	will make the assembler issue a warning for any SSE instruction.
	<samp>-msse-check=<var>error</var></samp> will make the assembler issue an error
	for any SSE instruction.
	</p>
	<a name="index-_002dmavxscalar_003d-option_002c-i386"></a>
	<a name="index-_002dmavxscalar_003d-option_002c-x86_002d64"></a>
	</dd>
	<dt><code>-mavxscalar=<var>128</var></code></dt>
	<dt><code>-mavxscalar=<var>256</var></code></dt>
	<dd><p>These options control how the assembler should encode scalar AVX
	instructions. <samp>-mavxscalar=<var>128</var></samp> will encode scalar
	AVX instructions with 128bit vector length, which is the default.
	<samp>-mavxscalar=<var>256</var></samp> will encode scalar AVX instructions
	with 256bit vector length.
	</p>
	<a name="index-_002dmevexlig_003d-option_002c-i386"></a>
	<a name="index-_002dmevexlig_003d-option_002c-x86_002d64"></a>
	</dd>
	<dt><code>-mevexlig=<var>128</var></code></dt>
	<dt><code>-mevexlig=<var>256</var></code></dt>
	<dt><code>-mevexlig=<var>512</var></code></dt>
	<dd><p>These options control how the assembler should encode length-ignored
	(LIG) EVEX instructions. <samp>-mevexlig=<var>128</var></samp> will encode LIG
	EVEX instructions with 128bit vector length, which is the default.
	<samp>-mevexlig=<var>256</var></samp> and <samp>-mevexlig=<var>512</var></samp> will
	encode LIG EVEX instructions with 256bit and 512bit vector length,
	respectively.
	</p>
	<a name="index-_002dmevexwig_003d-option_002c-i386"></a>
	<a name="index-_002dmevexwig_003d-option_002c-x86_002d64"></a>
	</dd>
	<dt><code>-mevexwig=<var>0</var></code></dt>
	<dt><code>-mevexwig=<var>1</var></code></dt>
	<dd><p>These options control how the assembler should encode w-ignored (WIG)
	EVEX instructions. <samp>-mevexwig=<var>0</var></samp> will encode WIG
	EVEX instructions with evex.w = 0, which is the default.
	<samp>-mevexwig=<var>1</var></samp> will encode WIG EVEX instructions with
	evex.w = 1.
	</p>
	<a name="index-_002dmmnemonic_003d-option_002c-i386"></a>
	<a name="index-_002dmmnemonic_003d-option_002c-x86_002d64"></a>
	</dd>
	<dt><code>-mmnemonic=<var>att</var></code></dt>
	<dt><code>-mmnemonic=<var>intel</var></code></dt>
	<dd><p>This option specifies instruction mnemonic for matching instructions.
	The <code>.att_mnemonic</code> and <code>.intel_mnemonic</code> directives will
	take precedent.
	</p>
	<a name="index-_002dmsyntax_003d-option_002c-i386"></a>
	<a name="index-_002dmsyntax_003d-option_002c-x86_002d64"></a>
	</dd>
	<dt><code>-msyntax=<var>att</var></code></dt>
	<dt><code>-msyntax=<var>intel</var></code></dt>
	<dd><p>This option specifies instruction syntax when processing instructions.
	The <code>.att_syntax</code> and <code>.intel_syntax</code> directives will
	take precedent.
	</p>
	<a name="index-_002dmnaked_002dreg-option_002c-i386"></a>
	<a name="index-_002dmnaked_002dreg-option_002c-x86_002d64"></a>
	</dd>
	<dt><code>-mnaked-reg</code></dt>
	<dd><p>This opetion specifies that registers don’t require a ‘<samp>%</samp>’ prefix.
	The <code>.att_syntax</code> and <code>.intel_syntax</code> directives will take precedent.
	</p>
	<a name="index-_002dmadd_002dbnd_002dprefix-option_002c-i386"></a>
	<a name="index-_002dmadd_002dbnd_002dprefix-option_002c-x86_002d64"></a>
	</dd>
	<dt><code>-madd-bnd-prefix</code></dt>
	<dd><p>This option forces the assembler to add BND prefix to all branches, even
	if such prefix was not explicitly specified in the source code.
	</p>
	</dd>
	</dl>

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