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| <title>Using the GNU Compiler Collection (GCC): SH Options</title> |
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| <hr> |
| <a name="SH-Options-1"></a> |
| <h4 class="subsection">3.17.42 SH Options</h4> |
| |
| <p>These ‘<samp>-m</samp>’ options are defined for the SH implementations: |
| </p> |
| <dl compact="compact"> |
| <dt><code>-m1</code></dt> |
| <dd><a name="index-m1"></a> |
| <p>Generate code for the SH1. |
| </p> |
| </dd> |
| <dt><code>-m2</code></dt> |
| <dd><a name="index-m2"></a> |
| <p>Generate code for the SH2. |
| </p> |
| </dd> |
| <dt><code>-m2e</code></dt> |
| <dd><p>Generate code for the SH2e. |
| </p> |
| </dd> |
| <dt><code>-m2a-nofpu</code></dt> |
| <dd><a name="index-m2a_002dnofpu"></a> |
| <p>Generate code for the SH2a without FPU, or for a SH2a-FPU in such a way |
| that the floating-point unit is not used. |
| </p> |
| </dd> |
| <dt><code>-m2a-single-only</code></dt> |
| <dd><a name="index-m2a_002dsingle_002donly"></a> |
| <p>Generate code for the SH2a-FPU, in such a way that no double-precision |
| floating-point operations are used. |
| </p> |
| </dd> |
| <dt><code>-m2a-single</code></dt> |
| <dd><a name="index-m2a_002dsingle"></a> |
| <p>Generate code for the SH2a-FPU assuming the floating-point unit is in |
| single-precision mode by default. |
| </p> |
| </dd> |
| <dt><code>-m2a</code></dt> |
| <dd><a name="index-m2a"></a> |
| <p>Generate code for the SH2a-FPU assuming the floating-point unit is in |
| double-precision mode by default. |
| </p> |
| </dd> |
| <dt><code>-m3</code></dt> |
| <dd><a name="index-m3"></a> |
| <p>Generate code for the SH3. |
| </p> |
| </dd> |
| <dt><code>-m3e</code></dt> |
| <dd><a name="index-m3e"></a> |
| <p>Generate code for the SH3e. |
| </p> |
| </dd> |
| <dt><code>-m4-nofpu</code></dt> |
| <dd><a name="index-m4_002dnofpu"></a> |
| <p>Generate code for the SH4 without a floating-point unit. |
| </p> |
| </dd> |
| <dt><code>-m4-single-only</code></dt> |
| <dd><a name="index-m4_002dsingle_002donly"></a> |
| <p>Generate code for the SH4 with a floating-point unit that only |
| supports single-precision arithmetic. |
| </p> |
| </dd> |
| <dt><code>-m4-single</code></dt> |
| <dd><a name="index-m4_002dsingle"></a> |
| <p>Generate code for the SH4 assuming the floating-point unit is in |
| single-precision mode by default. |
| </p> |
| </dd> |
| <dt><code>-m4</code></dt> |
| <dd><a name="index-m4"></a> |
| <p>Generate code for the SH4. |
| </p> |
| </dd> |
| <dt><code>-m4-100</code></dt> |
| <dd><a name="index-m4_002d100"></a> |
| <p>Generate code for SH4-100. |
| </p> |
| </dd> |
| <dt><code>-m4-100-nofpu</code></dt> |
| <dd><a name="index-m4_002d100_002dnofpu"></a> |
| <p>Generate code for SH4-100 in such a way that the |
| floating-point unit is not used. |
| </p> |
| </dd> |
| <dt><code>-m4-100-single</code></dt> |
| <dd><a name="index-m4_002d100_002dsingle"></a> |
| <p>Generate code for SH4-100 assuming the floating-point unit is in |
| single-precision mode by default. |
| </p> |
| </dd> |
| <dt><code>-m4-100-single-only</code></dt> |
| <dd><a name="index-m4_002d100_002dsingle_002donly"></a> |
| <p>Generate code for SH4-100 in such a way that no double-precision |
| floating-point operations are used. |
| </p> |
| </dd> |
| <dt><code>-m4-200</code></dt> |
| <dd><a name="index-m4_002d200"></a> |
| <p>Generate code for SH4-200. |
| </p> |
| </dd> |
| <dt><code>-m4-200-nofpu</code></dt> |
| <dd><a name="index-m4_002d200_002dnofpu"></a> |
| <p>Generate code for SH4-200 without in such a way that the |
| floating-point unit is not used. |
| </p> |
| </dd> |
| <dt><code>-m4-200-single</code></dt> |
| <dd><a name="index-m4_002d200_002dsingle"></a> |
| <p>Generate code for SH4-200 assuming the floating-point unit is in |
| single-precision mode by default. |
| </p> |
| </dd> |
| <dt><code>-m4-200-single-only</code></dt> |
| <dd><a name="index-m4_002d200_002dsingle_002donly"></a> |
| <p>Generate code for SH4-200 in such a way that no double-precision |
| floating-point operations are used. |
| </p> |
| </dd> |
| <dt><code>-m4-300</code></dt> |
| <dd><a name="index-m4_002d300"></a> |
| <p>Generate code for SH4-300. |
| </p> |
| </dd> |
| <dt><code>-m4-300-nofpu</code></dt> |
| <dd><a name="index-m4_002d300_002dnofpu"></a> |
| <p>Generate code for SH4-300 without in such a way that the |
| floating-point unit is not used. |
| </p> |
| </dd> |
| <dt><code>-m4-300-single</code></dt> |
| <dd><a name="index-m4_002d300_002dsingle"></a> |
| <p>Generate code for SH4-300 in such a way that no double-precision |
| floating-point operations are used. |
| </p> |
| </dd> |
| <dt><code>-m4-300-single-only</code></dt> |
| <dd><a name="index-m4_002d300_002dsingle_002donly"></a> |
| <p>Generate code for SH4-300 in such a way that no double-precision |
| floating-point operations are used. |
| </p> |
| </dd> |
| <dt><code>-m4-340</code></dt> |
| <dd><a name="index-m4_002d340"></a> |
| <p>Generate code for SH4-340 (no MMU, no FPU). |
| </p> |
| </dd> |
| <dt><code>-m4-500</code></dt> |
| <dd><a name="index-m4_002d500"></a> |
| <p>Generate code for SH4-500 (no FPU). Passes <samp>-isa=sh4-nofpu</samp> to the |
| assembler. |
| </p> |
| </dd> |
| <dt><code>-m4a-nofpu</code></dt> |
| <dd><a name="index-m4a_002dnofpu"></a> |
| <p>Generate code for the SH4al-dsp, or for a SH4a in such a way that the |
| floating-point unit is not used. |
| </p> |
| </dd> |
| <dt><code>-m4a-single-only</code></dt> |
| <dd><a name="index-m4a_002dsingle_002donly"></a> |
| <p>Generate code for the SH4a, in such a way that no double-precision |
| floating-point operations are used. |
| </p> |
| </dd> |
| <dt><code>-m4a-single</code></dt> |
| <dd><a name="index-m4a_002dsingle"></a> |
| <p>Generate code for the SH4a assuming the floating-point unit is in |
| single-precision mode by default. |
| </p> |
| </dd> |
| <dt><code>-m4a</code></dt> |
| <dd><a name="index-m4a"></a> |
| <p>Generate code for the SH4a. |
| </p> |
| </dd> |
| <dt><code>-m4al</code></dt> |
| <dd><a name="index-m4al"></a> |
| <p>Same as <samp>-m4a-nofpu</samp>, except that it implicitly passes |
| <samp>-dsp</samp> to the assembler. GCC doesn’t generate any DSP |
| instructions at the moment. |
| </p> |
| </dd> |
| <dt><code>-m5-32media</code></dt> |
| <dd><a name="index-m5_002d32media"></a> |
| <p>Generate 32-bit code for SHmedia. |
| </p> |
| </dd> |
| <dt><code>-m5-32media-nofpu</code></dt> |
| <dd><a name="index-m5_002d32media_002dnofpu"></a> |
| <p>Generate 32-bit code for SHmedia in such a way that the |
| floating-point unit is not used. |
| </p> |
| </dd> |
| <dt><code>-m5-64media</code></dt> |
| <dd><a name="index-m5_002d64media"></a> |
| <p>Generate 64-bit code for SHmedia. |
| </p> |
| </dd> |
| <dt><code>-m5-64media-nofpu</code></dt> |
| <dd><a name="index-m5_002d64media_002dnofpu"></a> |
| <p>Generate 64-bit code for SHmedia in such a way that the |
| floating-point unit is not used. |
| </p> |
| </dd> |
| <dt><code>-m5-compact</code></dt> |
| <dd><a name="index-m5_002dcompact"></a> |
| <p>Generate code for SHcompact. |
| </p> |
| </dd> |
| <dt><code>-m5-compact-nofpu</code></dt> |
| <dd><a name="index-m5_002dcompact_002dnofpu"></a> |
| <p>Generate code for SHcompact in such a way that the |
| floating-point unit is not used. |
| </p> |
| </dd> |
| <dt><code>-mb</code></dt> |
| <dd><a name="index-mb"></a> |
| <p>Compile code for the processor in big-endian mode. |
| </p> |
| </dd> |
| <dt><code>-ml</code></dt> |
| <dd><a name="index-ml-1"></a> |
| <p>Compile code for the processor in little-endian mode. |
| </p> |
| </dd> |
| <dt><code>-mdalign</code></dt> |
| <dd><a name="index-mdalign"></a> |
| <p>Align doubles at 64-bit boundaries. Note that this changes the calling |
| conventions, and thus some functions from the standard C library do |
| not work unless you recompile it first with <samp>-mdalign</samp>. |
| </p> |
| </dd> |
| <dt><code>-mrelax</code></dt> |
| <dd><a name="index-mrelax-6"></a> |
| <p>Shorten some address references at link time, when possible; uses the |
| linker option <samp>-relax</samp>. |
| </p> |
| </dd> |
| <dt><code>-mbigtable</code></dt> |
| <dd><a name="index-mbigtable"></a> |
| <p>Use 32-bit offsets in <code>switch</code> tables. The default is to use |
| 16-bit offsets. |
| </p> |
| </dd> |
| <dt><code>-mbitops</code></dt> |
| <dd><a name="index-mbitops-1"></a> |
| <p>Enable the use of bit manipulation instructions on SH2A. |
| </p> |
| </dd> |
| <dt><code>-mfmovd</code></dt> |
| <dd><a name="index-mfmovd"></a> |
| <p>Enable the use of the instruction <code>fmovd</code>. Check <samp>-mdalign</samp> for |
| alignment constraints. |
| </p> |
| </dd> |
| <dt><code>-mrenesas</code></dt> |
| <dd><a name="index-mrenesas"></a> |
| <p>Comply with the calling conventions defined by Renesas. |
| </p> |
| </dd> |
| <dt><code>-mno-renesas</code></dt> |
| <dd><a name="index-mno_002drenesas"></a> |
| <p>Comply with the calling conventions defined for GCC before the Renesas |
| conventions were available. This option is the default for all |
| targets of the SH toolchain. |
| </p> |
| </dd> |
| <dt><code>-mnomacsave</code></dt> |
| <dd><a name="index-mnomacsave"></a> |
| <p>Mark the <code>MAC</code> register as call-clobbered, even if |
| <samp>-mrenesas</samp> is given. |
| </p> |
| </dd> |
| <dt><code>-mieee</code></dt> |
| <dt><code>-mno-ieee</code></dt> |
| <dd><a name="index-mieee-1"></a> |
| <a name="index-mno_002dieee"></a> |
| <p>Control the IEEE compliance of floating-point comparisons, which affects the |
| handling of cases where the result of a comparison is unordered. By default |
| <samp>-mieee</samp> is implicitly enabled. If <samp>-ffinite-math-only</samp> is |
| enabled <samp>-mno-ieee</samp> is implicitly set, which results in faster |
| floating-point greater-equal and less-equal comparisons. The implcit settings |
| can be overridden by specifying either <samp>-mieee</samp> or <samp>-mno-ieee</samp>. |
| </p> |
| </dd> |
| <dt><code>-minline-ic_invalidate</code></dt> |
| <dd><a name="index-minline_002dic_005finvalidate"></a> |
| <p>Inline code to invalidate instruction cache entries after setting up |
| nested function trampolines. |
| This option has no effect if <samp>-musermode</samp> is in effect and the selected |
| code generation option (e.g. <samp>-m4</samp>) does not allow the use of the <code>icbi</code> |
| instruction. |
| If the selected code generation option does not allow the use of the <code>icbi</code> |
| instruction, and <samp>-musermode</samp> is not in effect, the inlined code |
| manipulates the instruction cache address array directly with an associative |
| write. This not only requires privileged mode at run time, but it also |
| fails if the cache line had been mapped via the TLB and has become unmapped. |
| </p> |
| </dd> |
| <dt><code>-misize</code></dt> |
| <dd><a name="index-misize-1"></a> |
| <p>Dump instruction size and location in the assembly code. |
| </p> |
| </dd> |
| <dt><code>-mpadstruct</code></dt> |
| <dd><a name="index-mpadstruct"></a> |
| <p>This option is deprecated. It pads structures to multiple of 4 bytes, |
| which is incompatible with the SH ABI. |
| </p> |
| </dd> |
| <dt><code>-matomic-model=<var>model</var></code></dt> |
| <dd><a name="index-matomic_002dmodel_003dmodel"></a> |
| <p>Sets the model of atomic operations and additional parameters as a comma |
| separated list. For details on the atomic built-in functions see |
| <a href="_005f_005fatomic-Builtins.html#g_t_005f_005fatomic-Builtins">__atomic Builtins</a>. The following models and parameters are supported: |
| </p> |
| <dl compact="compact"> |
| <dt>‘<samp>none</samp>’</dt> |
| <dd><p>Disable compiler generated atomic sequences and emit library calls for atomic |
| operations. This is the default if the target is not <code>sh*-*-linux*</code>. |
| </p> |
| </dd> |
| <dt>‘<samp>soft-gusa</samp>’</dt> |
| <dd><p>Generate GNU/Linux compatible gUSA software atomic sequences for the atomic |
| built-in functions. The generated atomic sequences require additional support |
| from the interrupt/exception handling code of the system and are only suitable |
| for SH3* and SH4* single-core systems. This option is enabled by default when |
| the target is <code>sh*-*-linux*</code> and SH3* or SH4*. When the target is SH4A, |
| this option will also partially utilize the hardware atomic instructions |
| <code>movli.l</code> and <code>movco.l</code> to create more efficient code, unless |
| ‘<samp>strict</samp>’ is specified. |
| </p> |
| </dd> |
| <dt>‘<samp>soft-tcb</samp>’</dt> |
| <dd><p>Generate software atomic sequences that use a variable in the thread control |
| block. This is a variation of the gUSA sequences which can also be used on |
| SH1* and SH2* targets. The generated atomic sequences require additional |
| support from the interrupt/exception handling code of the system and are only |
| suitable for single-core systems. When using this model, the ‘<samp>gbr-offset=</samp>’ |
| parameter has to be specified as well. |
| </p> |
| </dd> |
| <dt>‘<samp>soft-imask</samp>’</dt> |
| <dd><p>Generate software atomic sequences that temporarily disable interrupts by |
| setting <code>SR.IMASK = 1111</code>. This model works only when the program runs |
| in privileged mode and is only suitable for single-core systems. Additional |
| support from the interrupt/exception handling code of the system is not |
| required. This model is enabled by default when the target is |
| <code>sh*-*-linux*</code> and SH1* or SH2*. |
| </p> |
| </dd> |
| <dt>‘<samp>hard-llcs</samp>’</dt> |
| <dd><p>Generate hardware atomic sequences using the <code>movli.l</code> and <code>movco.l</code> |
| instructions only. This is only available on SH4A and is suitable for |
| multi-core systems. Since the hardware instructions support only 32 bit atomic |
| variables access to 8 or 16 bit variables is emulated with 32 bit accesses. |
| Code compiled with this option will also be compatible with other software |
| atomic model interrupt/exception handling systems if executed on an SH4A |
| system. Additional support from the interrupt/exception handling code of the |
| system is not required for this model. |
| </p> |
| </dd> |
| <dt>‘<samp>gbr-offset=</samp>’</dt> |
| <dd><p>This parameter specifies the offset in bytes of the variable in the thread |
| control block structure that should be used by the generated atomic sequences |
| when the ‘<samp>soft-tcb</samp>’ model has been selected. For other models this |
| parameter is ignored. The specified value must be an integer multiple of four |
| and in the range 0-1020. |
| </p> |
| </dd> |
| <dt>‘<samp>strict</samp>’</dt> |
| <dd><p>This parameter prevents mixed usage of multiple atomic models, even though they |
| would be compatible, and will make the compiler generate atomic sequences of the |
| specified model only. |
| </p> |
| </dd> |
| </dl> |
| |
| </dd> |
| <dt><code>-mtas</code></dt> |
| <dd><a name="index-mtas"></a> |
| <p>Generate the <code>tas.b</code> opcode for <code>__atomic_test_and_set</code>. |
| Notice that depending on the particular hardware and software configuration |
| this can degrade overall performance due to the operand cache line flushes |
| that are implied by the <code>tas.b</code> instruction. On multi-core SH4A |
| processors the <code>tas.b</code> instruction must be used with caution since it |
| can result in data corruption for certain cache configurations. |
| </p> |
| </dd> |
| <dt><code>-mprefergot</code></dt> |
| <dd><a name="index-mprefergot"></a> |
| <p>When generating position-independent code, emit function calls using |
| the Global Offset Table instead of the Procedure Linkage Table. |
| </p> |
| </dd> |
| <dt><code>-musermode</code></dt> |
| <dt><code>-mno-usermode</code></dt> |
| <dd><a name="index-musermode"></a> |
| <a name="index-mno_002dusermode"></a> |
| <p>Don’t allow (allow) the compiler generating privileged mode code. Specifying |
| <samp>-musermode</samp> also implies <samp>-mno-inline-ic_invalidate</samp> if the |
| inlined code would not work in user mode. <samp>-musermode</samp> is the default |
| when the target is <code>sh*-*-linux*</code>. If the target is SH1* or SH2* |
| <samp>-musermode</samp> has no effect, since there is no user mode. |
| </p> |
| </dd> |
| <dt><code>-multcost=<var>number</var></code></dt> |
| <dd><a name="index-multcost_003dnumber"></a> |
| <p>Set the cost to assume for a multiply insn. |
| </p> |
| </dd> |
| <dt><code>-mdiv=<var>strategy</var></code></dt> |
| <dd><a name="index-mdiv_003dstrategy"></a> |
| <p>Set the division strategy to be used for integer division operations. |
| For SHmedia <var>strategy</var> can be one of: |
| </p> |
| <dl compact="compact"> |
| <dt>‘<samp>fp</samp>’</dt> |
| <dd><p>Performs the operation in floating point. This has a very high latency, |
| but needs only a few instructions, so it might be a good choice if |
| your code has enough easily-exploitable ILP to allow the compiler to |
| schedule the floating-point instructions together with other instructions. |
| Division by zero causes a floating-point exception. |
| </p> |
| </dd> |
| <dt>‘<samp>inv</samp>’</dt> |
| <dd><p>Uses integer operations to calculate the inverse of the divisor, |
| and then multiplies the dividend with the inverse. This strategy allows |
| CSE and hoisting of the inverse calculation. Division by zero calculates |
| an unspecified result, but does not trap. |
| </p> |
| </dd> |
| <dt>‘<samp>inv:minlat</samp>’</dt> |
| <dd><p>A variant of ‘<samp>inv</samp>’ where, if no CSE or hoisting opportunities |
| have been found, or if the entire operation has been hoisted to the same |
| place, the last stages of the inverse calculation are intertwined with the |
| final multiply to reduce the overall latency, at the expense of using a few |
| more instructions, and thus offering fewer scheduling opportunities with |
| other code. |
| </p> |
| </dd> |
| <dt>‘<samp>call</samp>’</dt> |
| <dd><p>Calls a library function that usually implements the ‘<samp>inv:minlat</samp>’ |
| strategy. |
| This gives high code density for <code>m5-*media-nofpu</code> compilations. |
| </p> |
| </dd> |
| <dt>‘<samp>call2</samp>’</dt> |
| <dd><p>Uses a different entry point of the same library function, where it |
| assumes that a pointer to a lookup table has already been set up, which |
| exposes the pointer load to CSE and code hoisting optimizations. |
| </p> |
| </dd> |
| <dt>‘<samp>inv:call</samp>’</dt> |
| <dt>‘<samp>inv:call2</samp>’</dt> |
| <dt>‘<samp>inv:fp</samp>’</dt> |
| <dd><p>Use the ‘<samp>inv</samp>’ algorithm for initial |
| code generation, but if the code stays unoptimized, revert to the ‘<samp>call</samp>’, |
| ‘<samp>call2</samp>’, or ‘<samp>fp</samp>’ strategies, respectively. Note that the |
| potentially-trapping side effect of division by zero is carried by a |
| separate instruction, so it is possible that all the integer instructions |
| are hoisted out, but the marker for the side effect stays where it is. |
| A recombination to floating-point operations or a call is not possible |
| in that case. |
| </p> |
| </dd> |
| <dt>‘<samp>inv20u</samp>’</dt> |
| <dt>‘<samp>inv20l</samp>’</dt> |
| <dd><p>Variants of the ‘<samp>inv:minlat</samp>’ strategy. In the case |
| that the inverse calculation is not separated from the multiply, they speed |
| up division where the dividend fits into 20 bits (plus sign where applicable) |
| by inserting a test to skip a number of operations in this case; this test |
| slows down the case of larger dividends. ‘<samp>inv20u</samp>’ assumes the case of a such |
| a small dividend to be unlikely, and ‘<samp>inv20l</samp>’ assumes it to be likely. |
| </p> |
| </dd> |
| </dl> |
| |
| <p>For targets other than SHmedia <var>strategy</var> can be one of: |
| </p> |
| <dl compact="compact"> |
| <dt>‘<samp>call-div1</samp>’</dt> |
| <dd><p>Calls a library function that uses the single-step division instruction |
| <code>div1</code> to perform the operation. Division by zero calculates an |
| unspecified result and does not trap. This is the default except for SH4, |
| SH2A and SHcompact. |
| </p> |
| </dd> |
| <dt>‘<samp>call-fp</samp>’</dt> |
| <dd><p>Calls a library function that performs the operation in double precision |
| floating point. Division by zero causes a floating-point exception. This is |
| the default for SHcompact with FPU. Specifying this for targets that do not |
| have a double precision FPU will default to <code>call-div1</code>. |
| </p> |
| </dd> |
| <dt>‘<samp>call-table</samp>’</dt> |
| <dd><p>Calls a library function that uses a lookup table for small divisors and |
| the <code>div1</code> instruction with case distinction for larger divisors. Division |
| by zero calculates an unspecified result and does not trap. This is the default |
| for SH4. Specifying this for targets that do not have dynamic shift |
| instructions will default to <code>call-div1</code>. |
| </p> |
| </dd> |
| </dl> |
| |
| <p>When a division strategy has not been specified the default strategy will be |
| selected based on the current target. For SH2A the default strategy is to |
| use the <code>divs</code> and <code>divu</code> instructions instead of library function |
| calls. |
| </p> |
| </dd> |
| <dt><code>-maccumulate-outgoing-args</code></dt> |
| <dd><a name="index-maccumulate_002doutgoing_002dargs-1"></a> |
| <p>Reserve space once for outgoing arguments in the function prologue rather |
| than around each call. Generally beneficial for performance and size. Also |
| needed for unwinding to avoid changing the stack frame around conditional code. |
| </p> |
| </dd> |
| <dt><code>-mdivsi3_libfunc=<var>name</var></code></dt> |
| <dd><a name="index-mdivsi3_005flibfunc_003dname"></a> |
| <p>Set the name of the library function used for 32-bit signed division to |
| <var>name</var>. |
| This only affects the name used in the ‘<samp>call</samp>’ and ‘<samp>inv:call</samp>’ |
| division strategies, and the compiler still expects the same |
| sets of input/output/clobbered registers as if this option were not present. |
| </p> |
| </dd> |
| <dt><code>-mfixed-range=<var>register-range</var></code></dt> |
| <dd><a name="index-mfixed_002drange-2"></a> |
| <p>Generate code treating the given register range as fixed registers. |
| A fixed register is one that the register allocator can not use. This is |
| useful when compiling kernel code. A register range is specified as |
| two registers separated by a dash. Multiple register ranges can be |
| specified separated by a comma. |
| </p> |
| </dd> |
| <dt><code>-mindexed-addressing</code></dt> |
| <dd><a name="index-mindexed_002daddressing"></a> |
| <p>Enable the use of the indexed addressing mode for SHmedia32/SHcompact. |
| This is only safe if the hardware and/or OS implement 32-bit wrap-around |
| semantics for the indexed addressing mode. The architecture allows the |
| implementation of processors with 64-bit MMU, which the OS could use to |
| get 32-bit addressing, but since no current hardware implementation supports |
| this or any other way to make the indexed addressing mode safe to use in |
| the 32-bit ABI, the default is <samp>-mno-indexed-addressing</samp>. |
| </p> |
| </dd> |
| <dt><code>-mgettrcost=<var>number</var></code></dt> |
| <dd><a name="index-mgettrcost_003dnumber"></a> |
| <p>Set the cost assumed for the <code>gettr</code> instruction to <var>number</var>. |
| The default is 2 if <samp>-mpt-fixed</samp> is in effect, 100 otherwise. |
| </p> |
| </dd> |
| <dt><code>-mpt-fixed</code></dt> |
| <dd><a name="index-mpt_002dfixed"></a> |
| <p>Assume <code>pt*</code> instructions won’t trap. This generally generates |
| better-scheduled code, but is unsafe on current hardware. |
| The current architecture |
| definition says that <code>ptabs</code> and <code>ptrel</code> trap when the target |
| anded with 3 is 3. |
| This has the unintentional effect of making it unsafe to schedule these |
| instructions before a branch, or hoist them out of a loop. For example, |
| <code>__do_global_ctors</code>, a part of <samp>libgcc</samp> |
| that runs constructors at program |
| startup, calls functions in a list which is delimited by -1. With the |
| <samp>-mpt-fixed</samp> option, the <code>ptabs</code> is done before testing against -1. |
| That means that all the constructors run a bit more quickly, but when |
| the loop comes to the end of the list, the program crashes because <code>ptabs</code> |
| loads -1 into a target register. |
| </p> |
| <p>Since this option is unsafe for any |
| hardware implementing the current architecture specification, the default |
| is <samp>-mno-pt-fixed</samp>. Unless specified explicitly with |
| <samp>-mgettrcost</samp>, <samp>-mno-pt-fixed</samp> also implies <samp>-mgettrcost=100</samp>; |
| this deters register allocation from using target registers for storing |
| ordinary integers. |
| </p> |
| </dd> |
| <dt><code>-minvalid-symbols</code></dt> |
| <dd><a name="index-minvalid_002dsymbols"></a> |
| <p>Assume symbols might be invalid. Ordinary function symbols generated by |
| the compiler are always valid to load with |
| <code>movi</code>/<code>shori</code>/<code>ptabs</code> or |
| <code>movi</code>/<code>shori</code>/<code>ptrel</code>, |
| but with assembler and/or linker tricks it is possible |
| to generate symbols that cause <code>ptabs</code> or <code>ptrel</code> to trap. |
| This option is only meaningful when <samp>-mno-pt-fixed</samp> is in effect. |
| It prevents cross-basic-block CSE, hoisting and most scheduling |
| of symbol loads. The default is <samp>-mno-invalid-symbols</samp>. |
| </p> |
| </dd> |
| <dt><code>-mbranch-cost=<var>num</var></code></dt> |
| <dd><a name="index-mbranch_002dcost_003dnum"></a> |
| <p>Assume <var>num</var> to be the cost for a branch instruction. Higher numbers |
| make the compiler try to generate more branch-free code if possible. |
| If not specified the value is selected depending on the processor type that |
| is being compiled for. |
| </p> |
| </dd> |
| <dt><code>-mzdcbranch</code></dt> |
| <dt><code>-mno-zdcbranch</code></dt> |
| <dd><a name="index-mzdcbranch"></a> |
| <a name="index-mno_002dzdcbranch"></a> |
| <p>Assume (do not assume) that zero displacement conditional branch instructions |
| <code>bt</code> and <code>bf</code> are fast. If <samp>-mzdcbranch</samp> is specified, the |
| compiler will try to prefer zero displacement branch code sequences. This is |
| enabled by default when generating code for SH4 and SH4A. It can be explicitly |
| disabled by specifying <samp>-mno-zdcbranch</samp>. |
| </p> |
| </dd> |
| <dt><code>-mfused-madd</code></dt> |
| <dt><code>-mno-fused-madd</code></dt> |
| <dd><a name="index-mfused_002dmadd-4"></a> |
| <a name="index-mno_002dfused_002dmadd-4"></a> |
| <p>Generate code that uses (does not use) the floating-point multiply and |
| accumulate instructions. These instructions are generated by default |
| if hardware floating point is used. The machine-dependent |
| <samp>-mfused-madd</samp> option is now mapped to the machine-independent |
| <samp>-ffp-contract=fast</samp> option, and <samp>-mno-fused-madd</samp> is |
| mapped to <samp>-ffp-contract=off</samp>. |
| </p> |
| </dd> |
| <dt><code>-mfsca</code></dt> |
| <dt><code>-mno-fsca</code></dt> |
| <dd><a name="index-mfsca"></a> |
| <a name="index-mno_002dfsca"></a> |
| <p>Allow or disallow the compiler to emit the <code>fsca</code> instruction for sine |
| and cosine approximations. The option <code>-mfsca</code> must be used in |
| combination with <code>-funsafe-math-optimizations</code>. It is enabled by default |
| when generating code for SH4A. Using <code>-mno-fsca</code> disables sine and cosine |
| approximations even if <code>-funsafe-math-optimizations</code> is in effect. |
| </p> |
| </dd> |
| <dt><code>-mfsrra</code></dt> |
| <dt><code>-mno-fsrra</code></dt> |
| <dd><a name="index-mfsrra"></a> |
| <a name="index-mno_002dfsrra"></a> |
| <p>Allow or disallow the compiler to emit the <code>fsrra</code> instruction for |
| reciprocal square root approximations. The option <code>-mfsrra</code> must be used |
| in combination with <code>-funsafe-math-optimizations</code> and |
| <code>-ffinite-math-only</code>. It is enabled by default when generating code for |
| SH4A. Using <code>-mno-fsrra</code> disables reciprocal square root approximations |
| even if <code>-funsafe-math-optimizations</code> and <code>-ffinite-math-only</code> are |
| in effect. |
| </p> |
| </dd> |
| <dt><code>-mpretend-cmove</code></dt> |
| <dd><a name="index-mpretend_002dcmove"></a> |
| <p>Prefer zero-displacement conditional branches for conditional move instruction |
| patterns. This can result in faster code on the SH4 processor. |
| </p> |
| </dd> |
| </dl> |
| |
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