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<title>GNU Compiler Collection (GCC) Internals: Register Classes</title>
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<a name="Register-Classes"></a>
<div class="header">
<p>
Next: <a href="Old-Constraints.html#Old-Constraints" accesskey="n" rel="next">Old Constraints</a>, Previous: <a href="Registers.html#Registers" accesskey="p" rel="prev">Registers</a>, Up: <a href="Target-Macros.html#Target-Macros" accesskey="u" rel="up">Target Macros</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
</div>
<hr>
<a name="Register-Classes-1"></a>
<h3 class="section">17.8 Register Classes</h3>
<a name="index-register-class-definitions"></a>
<a name="index-class-definitions_002c-register"></a>
<p>On many machines, the numbered registers are not all equivalent.
For example, certain registers may not be allowed for indexed addressing;
certain registers may not be allowed in some instructions. These machine
restrictions are described to the compiler using <em>register classes</em>.
</p>
<p>You define a number of register classes, giving each one a name and saying
which of the registers belong to it. Then you can specify register classes
that are allowed as operands to particular instruction patterns.
</p>
<a name="index-ALL_005fREGS"></a>
<a name="index-NO_005fREGS"></a>
<p>In general, each register will belong to several classes. In fact, one
class must be named <code>ALL_REGS</code> and contain all the registers. Another
class must be named <code>NO_REGS</code> and contain no registers. Often the
union of two classes will be another class; however, this is not required.
</p>
<a name="index-GENERAL_005fREGS"></a>
<p>One of the classes must be named <code>GENERAL_REGS</code>. There is nothing
terribly special about the name, but the operand constraint letters
&lsquo;<samp>r</samp>&rsquo; and &lsquo;<samp>g</samp>&rsquo; specify this class. If <code>GENERAL_REGS</code> is
the same as <code>ALL_REGS</code>, just define it as a macro which expands
to <code>ALL_REGS</code>.
</p>
<p>Order the classes so that if class <var>x</var> is contained in class <var>y</var>
then <var>x</var> has a lower class number than <var>y</var>.
</p>
<p>The way classes other than <code>GENERAL_REGS</code> are specified in operand
constraints is through machine-dependent operand constraint letters.
You can define such letters to correspond to various classes, then use
them in operand constraints.
</p>
<p>You must define the narrowest register classes for allocatable
registers, so that each class either has no subclasses, or that for
some mode, the move cost between registers within the class is
cheaper than moving a register in the class to or from memory
(see <a href="Costs.html#Costs">Costs</a>).
</p>
<p>You should define a class for the union of two classes whenever some
instruction allows both classes. For example, if an instruction allows
either a floating point (coprocessor) register or a general register for a
certain operand, you should define a class <code>FLOAT_OR_GENERAL_REGS</code>
which includes both of them. Otherwise you will get suboptimal code,
or even internal compiler errors when reload cannot find a register in the
class computed via <code>reg_class_subunion</code>.
</p>
<p>You must also specify certain redundant information about the register
classes: for each class, which classes contain it and which ones are
contained in it; for each pair of classes, the largest class contained
in their union.
</p>
<p>When a value occupying several consecutive registers is expected in a
certain class, all the registers used must belong to that class.
Therefore, register classes cannot be used to enforce a requirement for
a register pair to start with an even-numbered register. The way to
specify this requirement is with <code>HARD_REGNO_MODE_OK</code>.
</p>
<p>Register classes used for input-operands of bitwise-and or shift
instructions have a special requirement: each such class must have, for
each fixed-point machine mode, a subclass whose registers can transfer that
mode to or from memory. For example, on some machines, the operations for
single-byte values (<code>QImode</code>) are limited to certain registers. When
this is so, each register class that is used in a bitwise-and or shift
instruction must have a subclass consisting of registers from which
single-byte values can be loaded or stored. This is so that
<code>PREFERRED_RELOAD_CLASS</code> can always have a possible value to return.
</p>
<dl>
<dt><a name="index-enum-reg_005fclass"></a>Data type: <strong>enum reg_class</strong></dt>
<dd><p>An enumerated type that must be defined with all the register class names
as enumerated values. <code>NO_REGS</code> must be first. <code>ALL_REGS</code>
must be the last register class, followed by one more enumerated value,
<code>LIM_REG_CLASSES</code>, which is not a register class but rather
tells how many classes there are.
</p>
<p>Each register class has a number, which is the value of casting
the class name to type <code>int</code>. The number serves as an index
in many of the tables described below.
</p></dd></dl>
<dl>
<dt><a name="index-N_005fREG_005fCLASSES"></a>Macro: <strong>N_REG_CLASSES</strong></dt>
<dd><p>The number of distinct register classes, defined as follows:
</p>
<div class="smallexample">
<pre class="smallexample">#define N_REG_CLASSES (int) LIM_REG_CLASSES
</pre></div>
</dd></dl>
<dl>
<dt><a name="index-REG_005fCLASS_005fNAMES"></a>Macro: <strong>REG_CLASS_NAMES</strong></dt>
<dd><p>An initializer containing the names of the register classes as C string
constants. These names are used in writing some of the debugging dumps.
</p></dd></dl>
<dl>
<dt><a name="index-REG_005fCLASS_005fCONTENTS"></a>Macro: <strong>REG_CLASS_CONTENTS</strong></dt>
<dd><p>An initializer containing the contents of the register classes, as integers
which are bit masks. The <var>n</var>th integer specifies the contents of class
<var>n</var>. The way the integer <var>mask</var> is interpreted is that
register <var>r</var> is in the class if <code><var>mask</var> &amp; (1 &lt;&lt; <var>r</var>)</code> is 1.
</p>
<p>When the machine has more than 32 registers, an integer does not suffice.
Then the integers are replaced by sub-initializers, braced groupings containing
several integers. Each sub-initializer must be suitable as an initializer
for the type <code>HARD_REG_SET</code> which is defined in <samp>hard-reg-set.h</samp>.
In this situation, the first integer in each sub-initializer corresponds to
registers 0 through 31, the second integer to registers 32 through 63, and
so on.
</p></dd></dl>
<dl>
<dt><a name="index-REGNO_005fREG_005fCLASS"></a>Macro: <strong>REGNO_REG_CLASS</strong> <em>(<var>regno</var>)</em></dt>
<dd><p>A C expression whose value is a register class containing hard register
<var>regno</var>. In general there is more than one such class; choose a class
which is <em>minimal</em>, meaning that no smaller class also contains the
register.
</p></dd></dl>
<dl>
<dt><a name="index-BASE_005fREG_005fCLASS"></a>Macro: <strong>BASE_REG_CLASS</strong></dt>
<dd><p>A macro whose definition is the name of the class to which a valid
base register must belong. A base register is one used in an address
which is the register value plus a displacement.
</p></dd></dl>
<dl>
<dt><a name="index-MODE_005fBASE_005fREG_005fCLASS"></a>Macro: <strong>MODE_BASE_REG_CLASS</strong> <em>(<var>mode</var>)</em></dt>
<dd><p>This is a variation of the <code>BASE_REG_CLASS</code> macro which allows
the selection of a base register in a mode dependent manner. If
<var>mode</var> is VOIDmode then it should return the same value as
<code>BASE_REG_CLASS</code>.
</p></dd></dl>
<dl>
<dt><a name="index-MODE_005fBASE_005fREG_005fREG_005fCLASS"></a>Macro: <strong>MODE_BASE_REG_REG_CLASS</strong> <em>(<var>mode</var>)</em></dt>
<dd><p>A C expression whose value is the register class to which a valid
base register must belong in order to be used in a base plus index
register address. You should define this macro if base plus index
addresses have different requirements than other base register uses.
</p></dd></dl>
<dl>
<dt><a name="index-MODE_005fCODE_005fBASE_005fREG_005fCLASS"></a>Macro: <strong>MODE_CODE_BASE_REG_CLASS</strong> <em>(<var>mode</var>, <var>address_space</var>, <var>outer_code</var>, <var>index_code</var>)</em></dt>
<dd><p>A C expression whose value is the register class to which a valid
base register for a memory reference in mode <var>mode</var> to address
space <var>address_space</var> must belong. <var>outer_code</var> and <var>index_code</var>
define the context in which the base register occurs. <var>outer_code</var> is
the code of the immediately enclosing expression (<code>MEM</code> for the top level
of an address, <code>ADDRESS</code> for something that occurs in an
<code>address_operand</code>). <var>index_code</var> is the code of the corresponding
index expression if <var>outer_code</var> is <code>PLUS</code>; <code>SCRATCH</code> otherwise.
</p></dd></dl>
<dl>
<dt><a name="index-INDEX_005fREG_005fCLASS"></a>Macro: <strong>INDEX_REG_CLASS</strong></dt>
<dd><p>A macro whose definition is the name of the class to which a valid
index register must belong. An index register is one used in an
address where its value is either multiplied by a scale factor or
added to another register (as well as added to a displacement).
</p></dd></dl>
<dl>
<dt><a name="index-REGNO_005fOK_005fFOR_005fBASE_005fP"></a>Macro: <strong>REGNO_OK_FOR_BASE_P</strong> <em>(<var>num</var>)</em></dt>
<dd><p>A C expression which is nonzero if register number <var>num</var> is
suitable for use as a base register in operand addresses.
</p></dd></dl>
<dl>
<dt><a name="index-REGNO_005fMODE_005fOK_005fFOR_005fBASE_005fP"></a>Macro: <strong>REGNO_MODE_OK_FOR_BASE_P</strong> <em>(<var>num</var>, <var>mode</var>)</em></dt>
<dd><p>A C expression that is just like <code>REGNO_OK_FOR_BASE_P</code>, except that
that expression may examine the mode of the memory reference in
<var>mode</var>. You should define this macro if the mode of the memory
reference affects whether a register may be used as a base register. If
you define this macro, the compiler will use it instead of
<code>REGNO_OK_FOR_BASE_P</code>. The mode may be <code>VOIDmode</code> for
addresses that appear outside a <code>MEM</code>, i.e., as an
<code>address_operand</code>.
</p></dd></dl>
<dl>
<dt><a name="index-REGNO_005fMODE_005fOK_005fFOR_005fREG_005fBASE_005fP"></a>Macro: <strong>REGNO_MODE_OK_FOR_REG_BASE_P</strong> <em>(<var>num</var>, <var>mode</var>)</em></dt>
<dd><p>A C expression which is nonzero if register number <var>num</var> is suitable for
use as a base register in base plus index operand addresses, accessing
memory in mode <var>mode</var>. It may be either a suitable hard register or a
pseudo register that has been allocated such a hard register. You should
define this macro if base plus index addresses have different requirements
than other base register uses.
</p>
<p>Use of this macro is deprecated; please use the more general
<code>REGNO_MODE_CODE_OK_FOR_BASE_P</code>.
</p></dd></dl>
<dl>
<dt><a name="index-REGNO_005fMODE_005fCODE_005fOK_005fFOR_005fBASE_005fP"></a>Macro: <strong>REGNO_MODE_CODE_OK_FOR_BASE_P</strong> <em>(<var>num</var>, <var>mode</var>, <var>address_space</var>, <var>outer_code</var>, <var>index_code</var>)</em></dt>
<dd><p>A C expression which is nonzero if register number <var>num</var> is
suitable for use as a base register in operand addresses, accessing
memory in mode <var>mode</var> in address space <var>address_space</var>.
This is similar to <code>REGNO_MODE_OK_FOR_BASE_P</code>, except
that that expression may examine the context in which the register
appears in the memory reference. <var>outer_code</var> is the code of the
immediately enclosing expression (<code>MEM</code> if at the top level of the
address, <code>ADDRESS</code> for something that occurs in an
<code>address_operand</code>). <var>index_code</var> is the code of the
corresponding index expression if <var>outer_code</var> is <code>PLUS</code>;
<code>SCRATCH</code> otherwise. The mode may be <code>VOIDmode</code> for addresses
that appear outside a <code>MEM</code>, i.e., as an <code>address_operand</code>.
</p></dd></dl>
<dl>
<dt><a name="index-REGNO_005fOK_005fFOR_005fINDEX_005fP"></a>Macro: <strong>REGNO_OK_FOR_INDEX_P</strong> <em>(<var>num</var>)</em></dt>
<dd><p>A C expression which is nonzero if register number <var>num</var> is
suitable for use as an index register in operand addresses. It may be
either a suitable hard register or a pseudo register that has been
allocated such a hard register.
</p>
<p>The difference between an index register and a base register is that
the index register may be scaled. If an address involves the sum of
two registers, neither one of them scaled, then either one may be
labeled the &ldquo;base&rdquo; and the other the &ldquo;index&rdquo;; but whichever
labeling is used must fit the machine&rsquo;s constraints of which registers
may serve in each capacity. The compiler will try both labelings,
looking for one that is valid, and will reload one or both registers
only if neither labeling works.
</p></dd></dl>
<dl>
<dt><a name="index-TARGET_005fPREFERRED_005fRENAME_005fCLASS"></a>Target Hook: <em>reg_class_t</em> <strong>TARGET_PREFERRED_RENAME_CLASS</strong> <em>(reg_class_t <var>rclass</var>)</em></dt>
<dd><p>A target hook that places additional preference on the register class to use when it is necessary to rename a register in class <var>rclass</var> to another class, or perhaps <var>NO_REGS</var>, if no preferred register class is found or hook <code>preferred_rename_class</code> is not implemented. Sometimes returning a more restrictive class makes better code. For example, on ARM, thumb-2 instructions using <code>LO_REGS</code> may be smaller than instructions using <code>GENERIC_REGS</code>. By returning <code>LO_REGS</code> from <code>preferred_rename_class</code>, code size can be reduced.
</p></dd></dl>
<dl>
<dt><a name="index-TARGET_005fPREFERRED_005fRELOAD_005fCLASS"></a>Target Hook: <em>reg_class_t</em> <strong>TARGET_PREFERRED_RELOAD_CLASS</strong> <em>(rtx <var>x</var>, reg_class_t <var>rclass</var>)</em></dt>
<dd><p>A target hook that places additional restrictions on the register class
to use when it is necessary to copy value <var>x</var> into a register in class
<var>rclass</var>. The value is a register class; perhaps <var>rclass</var>, or perhaps
another, smaller class.
</p>
<p>The default version of this hook always returns value of <code>rclass</code> argument.
</p>
<p>Sometimes returning a more restrictive class makes better code. For
example, on the 68000, when <var>x</var> is an integer constant that is in range
for a &lsquo;<samp>moveq</samp>&rsquo; instruction, the value of this macro is always
<code>DATA_REGS</code> as long as <var>rclass</var> includes the data registers.
Requiring a data register guarantees that a &lsquo;<samp>moveq</samp>&rsquo; will be used.
</p>
<p>One case where <code>TARGET_PREFERRED_RELOAD_CLASS</code> must not return
<var>rclass</var> is if <var>x</var> is a legitimate constant which cannot be
loaded into some register class. By returning <code>NO_REGS</code> you can
force <var>x</var> into a memory location. For example, rs6000 can load
immediate values into general-purpose registers, but does not have an
instruction for loading an immediate value into a floating-point
register, so <code>TARGET_PREFERRED_RELOAD_CLASS</code> returns <code>NO_REGS</code> when
<var>x</var> is a floating-point constant. If the constant can&rsquo;t be loaded
into any kind of register, code generation will be better if
<code>TARGET_LEGITIMATE_CONSTANT_P</code> makes the constant illegitimate instead
of using <code>TARGET_PREFERRED_RELOAD_CLASS</code>.
</p>
<p>If an insn has pseudos in it after register allocation, reload will go
through the alternatives and call repeatedly <code>TARGET_PREFERRED_RELOAD_CLASS</code>
to find the best one. Returning <code>NO_REGS</code>, in this case, makes
reload add a <code>!</code> in front of the constraint: the x86 back-end uses
this feature to discourage usage of 387 registers when math is done in
the SSE registers (and vice versa).
</p></dd></dl>
<dl>
<dt><a name="index-PREFERRED_005fRELOAD_005fCLASS"></a>Macro: <strong>PREFERRED_RELOAD_CLASS</strong> <em>(<var>x</var>, <var>class</var>)</em></dt>
<dd><p>A C expression that places additional restrictions on the register class
to use when it is necessary to copy value <var>x</var> into a register in class
<var>class</var>. The value is a register class; perhaps <var>class</var>, or perhaps
another, smaller class. On many machines, the following definition is
safe:
</p>
<div class="smallexample">
<pre class="smallexample">#define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
</pre></div>
<p>Sometimes returning a more restrictive class makes better code. For
example, on the 68000, when <var>x</var> is an integer constant that is in range
for a &lsquo;<samp>moveq</samp>&rsquo; instruction, the value of this macro is always
<code>DATA_REGS</code> as long as <var>class</var> includes the data registers.
Requiring a data register guarantees that a &lsquo;<samp>moveq</samp>&rsquo; will be used.
</p>
<p>One case where <code>PREFERRED_RELOAD_CLASS</code> must not return
<var>class</var> is if <var>x</var> is a legitimate constant which cannot be
loaded into some register class. By returning <code>NO_REGS</code> you can
force <var>x</var> into a memory location. For example, rs6000 can load
immediate values into general-purpose registers, but does not have an
instruction for loading an immediate value into a floating-point
register, so <code>PREFERRED_RELOAD_CLASS</code> returns <code>NO_REGS</code> when
<var>x</var> is a floating-point constant. If the constant can&rsquo;t be loaded
into any kind of register, code generation will be better if
<code>TARGET_LEGITIMATE_CONSTANT_P</code> makes the constant illegitimate instead
of using <code>TARGET_PREFERRED_RELOAD_CLASS</code>.
</p>
<p>If an insn has pseudos in it after register allocation, reload will go
through the alternatives and call repeatedly <code>PREFERRED_RELOAD_CLASS</code>
to find the best one. Returning <code>NO_REGS</code>, in this case, makes
reload add a <code>!</code> in front of the constraint: the x86 back-end uses
this feature to discourage usage of 387 registers when math is done in
the SSE registers (and vice versa).
</p></dd></dl>
<dl>
<dt><a name="index-TARGET_005fPREFERRED_005fOUTPUT_005fRELOAD_005fCLASS"></a>Target Hook: <em>reg_class_t</em> <strong>TARGET_PREFERRED_OUTPUT_RELOAD_CLASS</strong> <em>(rtx <var>x</var>, reg_class_t <var>rclass</var>)</em></dt>
<dd><p>Like <code>TARGET_PREFERRED_RELOAD_CLASS</code>, but for output reloads instead of
input reloads.
</p>
<p>The default version of this hook always returns value of <code>rclass</code>
argument.
</p>
<p>You can also use <code>TARGET_PREFERRED_OUTPUT_RELOAD_CLASS</code> to discourage
reload from using some alternatives, like <code>TARGET_PREFERRED_RELOAD_CLASS</code>.
</p></dd></dl>
<dl>
<dt><a name="index-LIMIT_005fRELOAD_005fCLASS"></a>Macro: <strong>LIMIT_RELOAD_CLASS</strong> <em>(<var>mode</var>, <var>class</var>)</em></dt>
<dd><p>A C expression that places additional restrictions on the register class
to use when it is necessary to be able to hold a value of mode
<var>mode</var> in a reload register for which class <var>class</var> would
ordinarily be used.
</p>
<p>Unlike <code>PREFERRED_RELOAD_CLASS</code>, this macro should be used when
there are certain modes that simply can&rsquo;t go in certain reload classes.
</p>
<p>The value is a register class; perhaps <var>class</var>, or perhaps another,
smaller class.
</p>
<p>Don&rsquo;t define this macro unless the target machine has limitations which
require the macro to do something nontrivial.
</p></dd></dl>
<dl>
<dt><a name="index-TARGET_005fSECONDARY_005fRELOAD"></a>Target Hook: <em>reg_class_t</em> <strong>TARGET_SECONDARY_RELOAD</strong> <em>(bool <var>in_p</var>, rtx <var>x</var>, reg_class_t <var>reload_class</var>, enum machine_mode <var>reload_mode</var>, secondary_reload_info *<var>sri</var>)</em></dt>
<dd><p>Many machines have some registers that cannot be copied directly to or
from memory or even from other types of registers. An example is the
&lsquo;<samp>MQ</samp>&rsquo; register, which on most machines, can only be copied to or
from general registers, but not memory. Below, we shall be using the
term &rsquo;intermediate register&rsquo; when a move operation cannot be performed
directly, but has to be done by copying the source into the intermediate
register first, and then copying the intermediate register to the
destination. An intermediate register always has the same mode as
source and destination. Since it holds the actual value being copied,
reload might apply optimizations to re-use an intermediate register
and eliding the copy from the source when it can determine that the
intermediate register still holds the required value.
</p>
<p>Another kind of secondary reload is required on some machines which
allow copying all registers to and from memory, but require a scratch
register for stores to some memory locations (e.g., those with symbolic
address on the RT, and those with certain symbolic address on the SPARC
when compiling PIC). Scratch registers need not have the same mode
as the value being copied, and usually hold a different value than
that being copied. Special patterns in the md file are needed to
describe how the copy is performed with the help of the scratch register;
these patterns also describe the number, register class(es) and mode(s)
of the scratch register(s).
</p>
<p>In some cases, both an intermediate and a scratch register are required.
</p>
<p>For input reloads, this target hook is called with nonzero <var>in_p</var>,
and <var>x</var> is an rtx that needs to be copied to a register of class
<var>reload_class</var> in <var>reload_mode</var>. For output reloads, this target
hook is called with zero <var>in_p</var>, and a register of class <var>reload_class</var>
needs to be copied to rtx <var>x</var> in <var>reload_mode</var>.
</p>
<p>If copying a register of <var>reload_class</var> from/to <var>x</var> requires
an intermediate register, the hook <code>secondary_reload</code> should
return the register class required for this intermediate register.
If no intermediate register is required, it should return NO_REGS.
If more than one intermediate register is required, describe the one
that is closest in the copy chain to the reload register.
</p>
<p>If scratch registers are needed, you also have to describe how to
perform the copy from/to the reload register to/from this
closest intermediate register. Or if no intermediate register is
required, but still a scratch register is needed, describe the
copy from/to the reload register to/from the reload operand <var>x</var>.
</p>
<p>You do this by setting <code>sri-&gt;icode</code> to the instruction code of a pattern
in the md file which performs the move. Operands 0 and 1 are the output
and input of this copy, respectively. Operands from operand 2 onward are
for scratch operands. These scratch operands must have a mode, and a
single-register-class
output constraint.
</p>
<p>When an intermediate register is used, the <code>secondary_reload</code>
hook will be called again to determine how to copy the intermediate
register to/from the reload operand <var>x</var>, so your hook must also
have code to handle the register class of the intermediate operand.
</p>
<p><var>x</var> might be a pseudo-register or a <code>subreg</code> of a
pseudo-register, which could either be in a hard register or in memory.
Use <code>true_regnum</code> to find out; it will return -1 if the pseudo is
in memory and the hard register number if it is in a register.
</p>
<p>Scratch operands in memory (constraint <code>&quot;=m&quot;</code> / <code>&quot;=&amp;m&quot;</code>) are
currently not supported. For the time being, you will have to continue
to use <code>SECONDARY_MEMORY_NEEDED</code> for that purpose.
</p>
<p><code>copy_cost</code> also uses this target hook to find out how values are
copied. If you want it to include some extra cost for the need to allocate
(a) scratch register(s), set <code>sri-&gt;extra_cost</code> to the additional cost.
Or if two dependent moves are supposed to have a lower cost than the sum
of the individual moves due to expected fortuitous scheduling and/or special
forwarding logic, you can set <code>sri-&gt;extra_cost</code> to a negative amount.
</p></dd></dl>
<dl>
<dt><a name="index-SECONDARY_005fRELOAD_005fCLASS"></a>Macro: <strong>SECONDARY_RELOAD_CLASS</strong> <em>(<var>class</var>, <var>mode</var>, <var>x</var>)</em></dt>
<dt><a name="index-SECONDARY_005fINPUT_005fRELOAD_005fCLASS"></a>Macro: <strong>SECONDARY_INPUT_RELOAD_CLASS</strong> <em>(<var>class</var>, <var>mode</var>, <var>x</var>)</em></dt>
<dt><a name="index-SECONDARY_005fOUTPUT_005fRELOAD_005fCLASS"></a>Macro: <strong>SECONDARY_OUTPUT_RELOAD_CLASS</strong> <em>(<var>class</var>, <var>mode</var>, <var>x</var>)</em></dt>
<dd><p>These macros are obsolete, new ports should use the target hook
<code>TARGET_SECONDARY_RELOAD</code> instead.
</p>
<p>These are obsolete macros, replaced by the <code>TARGET_SECONDARY_RELOAD</code>
target hook. Older ports still define these macros to indicate to the
reload phase that it may
need to allocate at least one register for a reload in addition to the
register to contain the data. Specifically, if copying <var>x</var> to a
register <var>class</var> in <var>mode</var> requires an intermediate register,
you were supposed to define <code>SECONDARY_INPUT_RELOAD_CLASS</code> to return the
largest register class all of whose registers can be used as
intermediate registers or scratch registers.
</p>
<p>If copying a register <var>class</var> in <var>mode</var> to <var>x</var> requires an
intermediate or scratch register, <code>SECONDARY_OUTPUT_RELOAD_CLASS</code>
was supposed to be defined be defined to return the largest register
class required. If the
requirements for input and output reloads were the same, the macro
<code>SECONDARY_RELOAD_CLASS</code> should have been used instead of defining both
macros identically.
</p>
<p>The values returned by these macros are often <code>GENERAL_REGS</code>.
Return <code>NO_REGS</code> if no spare register is needed; i.e., if <var>x</var>
can be directly copied to or from a register of <var>class</var> in
<var>mode</var> without requiring a scratch register. Do not define this
macro if it would always return <code>NO_REGS</code>.
</p>
<p>If a scratch register is required (either with or without an
intermediate register), you were supposed to define patterns for
&lsquo;<samp>reload_in<var>m</var></samp>&rsquo; or &lsquo;<samp>reload_out<var>m</var></samp>&rsquo;, as required
(see <a href="Standard-Names.html#Standard-Names">Standard Names</a>. These patterns, which were normally
implemented with a <code>define_expand</code>, should be similar to the
&lsquo;<samp>mov<var>m</var></samp>&rsquo; patterns, except that operand 2 is the scratch
register.
</p>
<p>These patterns need constraints for the reload register and scratch
register that
contain a single register class. If the original reload register (whose
class is <var>class</var>) can meet the constraint given in the pattern, the
value returned by these macros is used for the class of the scratch
register. Otherwise, two additional reload registers are required.
Their classes are obtained from the constraints in the insn pattern.
</p>
<p><var>x</var> might be a pseudo-register or a <code>subreg</code> of a
pseudo-register, which could either be in a hard register or in memory.
Use <code>true_regnum</code> to find out; it will return -1 if the pseudo is
in memory and the hard register number if it is in a register.
</p>
<p>These macros should not be used in the case where a particular class of
registers can only be copied to memory and not to another class of
registers. In that case, secondary reload registers are not needed and
would not be helpful. Instead, a stack location must be used to perform
the copy and the <code>mov<var>m</var></code> pattern should use memory as an
intermediate storage. This case often occurs between floating-point and
general registers.
</p></dd></dl>
<dl>
<dt><a name="index-SECONDARY_005fMEMORY_005fNEEDED"></a>Macro: <strong>SECONDARY_MEMORY_NEEDED</strong> <em>(<var>class1</var>, <var>class2</var>, <var>m</var>)</em></dt>
<dd><p>Certain machines have the property that some registers cannot be copied
to some other registers without using memory. Define this macro on
those machines to be a C expression that is nonzero if objects of mode
<var>m</var> in registers of <var>class1</var> can only be copied to registers of
class <var>class2</var> by storing a register of <var>class1</var> into memory
and loading that memory location into a register of <var>class2</var>.
</p>
<p>Do not define this macro if its value would always be zero.
</p></dd></dl>
<dl>
<dt><a name="index-SECONDARY_005fMEMORY_005fNEEDED_005fRTX"></a>Macro: <strong>SECONDARY_MEMORY_NEEDED_RTX</strong> <em>(<var>mode</var>)</em></dt>
<dd><p>Normally when <code>SECONDARY_MEMORY_NEEDED</code> is defined, the compiler
allocates a stack slot for a memory location needed for register copies.
If this macro is defined, the compiler instead uses the memory location
defined by this macro.
</p>
<p>Do not define this macro if you do not define
<code>SECONDARY_MEMORY_NEEDED</code>.
</p></dd></dl>
<dl>
<dt><a name="index-SECONDARY_005fMEMORY_005fNEEDED_005fMODE"></a>Macro: <strong>SECONDARY_MEMORY_NEEDED_MODE</strong> <em>(<var>mode</var>)</em></dt>
<dd><p>When the compiler needs a secondary memory location to copy between two
registers of mode <var>mode</var>, it normally allocates sufficient memory to
hold a quantity of <code>BITS_PER_WORD</code> bits and performs the store and
load operations in a mode that many bits wide and whose class is the
same as that of <var>mode</var>.
</p>
<p>This is right thing to do on most machines because it ensures that all
bits of the register are copied and prevents accesses to the registers
in a narrower mode, which some machines prohibit for floating-point
registers.
</p>
<p>However, this default behavior is not correct on some machines, such as
the DEC Alpha, that store short integers in floating-point registers
differently than in integer registers. On those machines, the default
widening will not work correctly and you must define this macro to
suppress that widening in some cases. See the file <samp>alpha.h</samp> for
details.
</p>
<p>Do not define this macro if you do not define
<code>SECONDARY_MEMORY_NEEDED</code> or if widening <var>mode</var> to a mode that
is <code>BITS_PER_WORD</code> bits wide is correct for your machine.
</p></dd></dl>
<dl>
<dt><a name="index-TARGET_005fCLASS_005fLIKELY_005fSPILLED_005fP"></a>Target Hook: <em>bool</em> <strong>TARGET_CLASS_LIKELY_SPILLED_P</strong> <em>(reg_class_t <var>rclass</var>)</em></dt>
<dd><p>A target hook which returns <code>true</code> if pseudos that have been assigned
to registers of class <var>rclass</var> would likely be spilled because
registers of <var>rclass</var> are needed for spill registers.
</p>
<p>The default version of this target hook returns <code>true</code> if <var>rclass</var>
has exactly one register and <code>false</code> otherwise. On most machines, this
default should be used. For generally register-starved machines, such as
i386, or machines with right register constraints, such as SH, this hook
can be used to avoid excessive spilling.
</p>
<p>This hook is also used by some of the global intra-procedural code
transformations to throtle code motion, to avoid increasing register
pressure.
</p></dd></dl>
<dl>
<dt><a name="index-TARGET_005fCLASS_005fMAX_005fNREGS"></a>Target Hook: <em>unsigned char</em> <strong>TARGET_CLASS_MAX_NREGS</strong> <em>(reg_class_t <var>rclass</var>, enum machine_mode <var>mode</var>)</em></dt>
<dd><p>A target hook returns the maximum number of consecutive registers
of class <var>rclass</var> needed to hold a value of mode <var>mode</var>.
</p>
<p>This is closely related to the macro <code>HARD_REGNO_NREGS</code>. In fact,
the value returned by <code>TARGET_CLASS_MAX_NREGS (<var>rclass</var>,
<var>mode</var>)</code> target hook should be the maximum value of
<code>HARD_REGNO_NREGS (<var>regno</var>, <var>mode</var>)</code> for all <var>regno</var>
values in the class <var>rclass</var>.
</p>
<p>This target hook helps control the handling of multiple-word values
in the reload pass.
</p>
<p>The default version of this target hook returns the size of <var>mode</var>
in words.
</p></dd></dl>
<dl>
<dt><a name="index-CLASS_005fMAX_005fNREGS"></a>Macro: <strong>CLASS_MAX_NREGS</strong> <em>(<var>class</var>, <var>mode</var>)</em></dt>
<dd><p>A C expression for the maximum number of consecutive registers
of class <var>class</var> needed to hold a value of mode <var>mode</var>.
</p>
<p>This is closely related to the macro <code>HARD_REGNO_NREGS</code>. In fact,
the value of the macro <code>CLASS_MAX_NREGS (<var>class</var>, <var>mode</var>)</code>
should be the maximum value of <code>HARD_REGNO_NREGS (<var>regno</var>,
<var>mode</var>)</code> for all <var>regno</var> values in the class <var>class</var>.
</p>
<p>This macro helps control the handling of multiple-word values
in the reload pass.
</p></dd></dl>
<dl>
<dt><a name="index-CANNOT_005fCHANGE_005fMODE_005fCLASS"></a>Macro: <strong>CANNOT_CHANGE_MODE_CLASS</strong> <em>(<var>from</var>, <var>to</var>, <var>class</var>)</em></dt>
<dd><p>If defined, a C expression that returns nonzero for a <var>class</var> for which
a change from mode <var>from</var> to mode <var>to</var> is invalid.
</p>
<p>For the example, loading 32-bit integer or floating-point objects into
floating-point registers on the Alpha extends them to 64 bits.
Therefore loading a 64-bit object and then storing it as a 32-bit object
does not store the low-order 32 bits, as would be the case for a normal
register. Therefore, <samp>alpha.h</samp> defines <code>CANNOT_CHANGE_MODE_CLASS</code>
as below:
</p>
<div class="smallexample">
<pre class="smallexample">#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0)
</pre></div>
</dd></dl>
<dl>
<dt><a name="index-TARGET_005fLRA_005fP"></a>Target Hook: <em>bool</em> <strong>TARGET_LRA_P</strong> <em>(void)</em></dt>
<dd><p>A target hook which returns true if we use LRA instead of reload pass. It means that LRA was ported to the target. The default version of this target hook returns always false.
</p></dd></dl>
<dl>
<dt><a name="index-TARGET_005fREGISTER_005fPRIORITY"></a>Target Hook: <em>int</em> <strong>TARGET_REGISTER_PRIORITY</strong> <em>(int)</em></dt>
<dd><p>A target hook which returns the register priority number to which the register <var>hard_regno</var> belongs to. The bigger the number, the more preferable the hard register usage (when all other conditions are the same). This hook can be used to prefer some hard register over others in LRA. For example, some x86-64 register usage needs additional prefix which makes instructions longer. The hook can return lower priority number for such registers make them less favorable and as result making the generated code smaller. The default version of this target hook returns always zero.
</p></dd></dl>
<dl>
<dt><a name="index-TARGET_005fREGISTER_005fUSAGE_005fLEVELING_005fP"></a>Target Hook: <em>bool</em> <strong>TARGET_REGISTER_USAGE_LEVELING_P</strong> <em>(void)</em></dt>
<dd><p>A target hook which returns true if we need register usage leveling. That means if a few hard registers are equally good for the assignment, we choose the least used hard register. The register usage leveling may be profitable for some targets. Don&rsquo;t use the usage leveling for targets with conditional execution or targets with big register files as it hurts if-conversion and cross-jumping optimizations. The default version of this target hook returns always false.
</p></dd></dl>
<dl>
<dt><a name="index-TARGET_005fDIFFERENT_005fADDR_005fDISPLACEMENT_005fP"></a>Target Hook: <em>bool</em> <strong>TARGET_DIFFERENT_ADDR_DISPLACEMENT_P</strong> <em>(void)</em></dt>
<dd><p>A target hook which returns true if an address with the same structure can have different maximal legitimate displacement. For example, the displacement can depend on memory mode or on operand combinations in the insn. The default version of this target hook returns always false.
</p></dd></dl>
<dl>
<dt><a name="index-TARGET_005fSPILL_005fCLASS"></a>Target Hook: <em>reg_class_t</em> <strong>TARGET_SPILL_CLASS</strong> <em>(reg_class_t, enum <var>machine_mode</var>)</em></dt>
<dd><p>This hook defines a class of registers which could be used for spilling pseudos of the given mode and class, or <code>NO_REGS</code> if only memory should be used. Not defining this hook is equivalent to returning <code>NO_REGS</code> for all inputs.
</p></dd></dl>
<dl>
<dt><a name="index-TARGET_005fCSTORE_005fMODE"></a>Target Hook: <em>enum machine_mode</em> <strong>TARGET_CSTORE_MODE</strong> <em>(enum insn_code <var>icode</var>)</em></dt>
<dd><p>This hook defines the machine mode to use for the boolean result of conditional store patterns. The ICODE argument is the instruction code for the cstore being performed. Not definiting this hook is the same as accepting the mode encoded into operand 0 of the cstore expander patterns.
</p></dd></dl>
<hr>
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