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 <a name="ARM-Options"></a>
 <div class="header">
 <p>
 Next: <a href="ARM-Syntax.html#ARM-Syntax" accesskey="n" rel="next">ARM Syntax</a>, Up: <a href="ARM_002dDependent.html#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
 </div>
 <hr>
 <a name="Options-3"></a>
 <h4 class="subsection">9.4.1 Options</h4>
 <a name="index-ARM-options-_0028none_0029"></a>
 <a name="index-options-for-ARM-_0028none_0029"></a>

 <dl compact="compact">
 <dd>
 <a name="index-_002dmcpu_003d-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-mcpu=<var>processor</var>[+<var>extension</var>&hellip;]</code></dt>
 <dd><p>This option specifies the target processor.  The assembler will issue an
 error message if an attempt is made to assemble an instruction which
 will not execute on the target processor.  The following processor names are
 recognized:
 <code>arm1</code>,
 <code>arm2</code>,
 <code>arm250</code>,
 <code>arm3</code>,
 <code>arm6</code>,
 <code>arm60</code>,
 <code>arm600</code>,
 <code>arm610</code>,
 <code>arm620</code>,
 <code>arm7</code>,
 <code>arm7m</code>,
 <code>arm7d</code>,
 <code>arm7dm</code>,
 <code>arm7di</code>,
 <code>arm7dmi</code>,
 <code>arm70</code>,
 <code>arm700</code>,
 <code>arm700i</code>,
 <code>arm710</code>,
 <code>arm710t</code>,
 <code>arm720</code>,
 <code>arm720t</code>,
 <code>arm740t</code>,
 <code>arm710c</code>,
 <code>arm7100</code>,
 <code>arm7500</code>,
 <code>arm7500fe</code>,
 <code>arm7t</code>,
 <code>arm7tdmi</code>,
 <code>arm7tdmi-s</code>,
 <code>arm8</code>,
 <code>arm810</code>,
 <code>strongarm</code>,
 <code>strongarm1</code>,
 <code>strongarm110</code>,
 <code>strongarm1100</code>,
 <code>strongarm1110</code>,
 <code>arm9</code>,
 <code>arm920</code>,
 <code>arm920t</code>,
 <code>arm922t</code>,
 <code>arm940t</code>,
 <code>arm9tdmi</code>,
 <code>fa526</code> (Faraday FA526 processor),
 <code>fa626</code> (Faraday FA626 processor),
 <code>arm9e</code>,
 <code>arm926e</code>,
 <code>arm926ej-s</code>,
 <code>arm946e-r0</code>,
 <code>arm946e</code>,
 <code>arm946e-s</code>,
 <code>arm966e-r0</code>,
 <code>arm966e</code>,
 <code>arm966e-s</code>,
 <code>arm968e-s</code>,
 <code>arm10t</code>,
 <code>arm10tdmi</code>,
 <code>arm10e</code>,
 <code>arm1020</code>,
 <code>arm1020t</code>,
 <code>arm1020e</code>,
 <code>arm1022e</code>,
 <code>arm1026ej-s</code>,
 <code>fa606te</code> (Faraday FA606TE processor),
 <code>fa616te</code> (Faraday FA616TE processor),
 <code>fa626te</code> (Faraday FA626TE processor),
 <code>fmp626</code> (Faraday FMP626 processor),
 <code>fa726te</code> (Faraday FA726TE processor),
 <code>arm1136j-s</code>,
 <code>arm1136jf-s</code>,
 <code>arm1156t2-s</code>,
 <code>arm1156t2f-s</code>,
 <code>arm1176jz-s</code>,
 <code>arm1176jzf-s</code>,
 <code>mpcore</code>,
 <code>mpcorenovfp</code>,
 <code>cortex-a5</code>,
 <code>cortex-a7</code>,
 <code>cortex-a8</code>,
 <code>cortex-a9</code>,
 <code>cortex-a15</code>,
 <code>cortex-a53</code>,
 <code>cortex-a57</code>,
 <code>cortex-a72</code>,
 <code>cortex-r4</code>,
 <code>cortex-r4f</code>,
 <code>cortex-r5</code>,
 <code>cortex-r7</code>,
 <code>cortex-m7</code>,
 <code>cortex-m4</code>,
 <code>cortex-m3</code>,
 <code>cortex-m1</code>,
 <code>cortex-m0</code>,
 <code>cortex-m0plus</code>,
 <code>exynos-m1</code>,
 <code>marvell-pj4</code>,
 <code>marvell-whitney</code>,
 <code>xgene1</code>,
 <code>xgene2</code>,
 <code>ep9312</code> (ARM920 with Cirrus Maverick coprocessor),
 <code>i80200</code> (Intel XScale processor)
 <code>iwmmxt</code> (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
 and
 <code>xscale</code>.
 The special name <code>all</code> may be used to allow the
 assembler to accept instructions valid for any ARM processor.
 </p>
 <p>In addition to the basic instruction set, the assembler can be told to
 accept various extension mnemonics that extend the processor using the
 co-processor instruction space.  For example, <code>-mcpu=arm920+maverick</code>
 is equivalent to specifying <code>-mcpu=ep9312</code>.
 </p>
 <p>Multiple extensions may be specified, separated by a <code>+</code>.  The
 extensions should be specified in ascending alphabetical order.
 </p>
 <p>Some extensions may be restricted to particular architectures; this is
 documented in the list of extensions below.
 </p>
 <p>Extension mnemonics may also be removed from those the assembler accepts.
 This is done be prepending <code>no</code> to the option that adds the extension.
 Extensions that are removed should be listed after all extensions which have
 been added, again in ascending alphabetical order.  For example,
 <code>-mcpu=ep9312+nomaverick</code> is equivalent to specifying <code>-mcpu=arm920</code>.
 </p>

 <p>The following extensions are currently supported:
 <code>crc</code>
 <code>crypto</code> (Cryptography Extensions for v8-A architecture, implies <code>fp+simd</code>),
 <code>fp</code> (Floating Point Extensions for v8-A architecture),
 <code>idiv</code> (Integer Divide Extensions for v7-A and v7-R architectures),
 <code>iwmmxt</code>,
 <code>iwmmxt2</code>,
 <code>xscale</code>,
 <code>maverick</code>,
 <code>mp</code> (Multiprocessing Extensions for v7-A and v7-R
 architectures),
 <code>os</code> (Operating System for v6M architecture),
 <code>sec</code> (Security Extensions for v6K and v7-A architectures),
 <code>simd</code> (Advanced SIMD Extensions for v8-A architecture, implies <code>fp</code>),
 <code>virt</code> (Virtualization Extensions for v7-A architecture, implies
 <code>idiv</code>),
 <code>pan</code> (Priviliged Access Never Extensions for v8-A architecture),
 <code>rdma</code> (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
 <code>simd</code>)
 and
 <code>xscale</code>.
 </p>
 <a name="index-_002dmarch_003d-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-march=<var>architecture</var>[+<var>extension</var>&hellip;]</code></dt>
 <dd><p>This option specifies the target architecture.  The assembler will issue
 an error message if an attempt is made to assemble an instruction which
 will not execute on the target architecture.  The following architecture
 names are recognized:
 <code>armv1</code>,
 <code>armv2</code>,
 <code>armv2a</code>,
 <code>armv2s</code>,
 <code>armv3</code>,
 <code>armv3m</code>,
 <code>armv4</code>,
 <code>armv4xm</code>,
 <code>armv4t</code>,
 <code>armv4txm</code>,
 <code>armv5</code>,
 <code>armv5t</code>,
 <code>armv5txm</code>,
 <code>armv5te</code>,
 <code>armv5texp</code>,
 <code>armv6</code>,
 <code>armv6j</code>,
 <code>armv6k</code>,
 <code>armv6z</code>,
 <code>armv6zk</code>,
 <code>armv6-m</code>,
 <code>armv6s-m</code>,
 <code>armv7</code>,
 <code>armv7-a</code>,
 <code>armv7ve</code>,
 <code>armv7-r</code>,
 <code>armv7-m</code>,
 <code>armv7e-m</code>,
 <code>armv8-a</code>,
 <code>armv8.1-a</code>,
 <code>iwmmxt</code>
 <code>iwmmxt2</code>
 and
 <code>xscale</code>.
 If both <code>-mcpu</code> and
 <code>-march</code> are specified, the assembler will use
 the setting for <code>-mcpu</code>.
 </p>
 <p>The architecture option can be extended with the same instruction set
 extension options as the <code>-mcpu</code> option.
 </p>
 <a name="index-_002dmfpu_003d-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-mfpu=<var>floating-point-format</var></code></dt>
 <dd>
 <p>This option specifies the floating point format to assemble for.  The
 assembler will issue an error message if an attempt is made to assemble
 an instruction which will not execute on the target floating point unit.
 The following format options are recognized:
 <code>softfpa</code>,
 <code>fpe</code>,
 <code>fpe2</code>,
 <code>fpe3</code>,
 <code>fpa</code>,
 <code>fpa10</code>,
 <code>fpa11</code>,
 <code>arm7500fe</code>,
 <code>softvfp</code>,
 <code>softvfp+vfp</code>,
 <code>vfp</code>,
 <code>vfp10</code>,
 <code>vfp10-r0</code>,
 <code>vfp9</code>,
 <code>vfpxd</code>,
 <code>vfpv2</code>,
 <code>vfpv3</code>,
 <code>vfpv3-fp16</code>,
 <code>vfpv3-d16</code>,
 <code>vfpv3-d16-fp16</code>,
 <code>vfpv3xd</code>,
 <code>vfpv3xd-d16</code>,
 <code>vfpv4</code>,
 <code>vfpv4-d16</code>,
 <code>fpv4-sp-d16</code>,
 <code>fpv5-sp-d16</code>,
 <code>fpv5-d16</code>,
 <code>fp-armv8</code>,
 <code>arm1020t</code>,
 <code>arm1020e</code>,
 <code>arm1136jf-s</code>,
 <code>maverick</code>,
 <code>neon</code>,
 <code>neon-vfpv4</code>,
 <code>neon-fp-armv8</code>,
 <code>crypto-neon-fp-armv8</code>.
 and
 <code>neon-fp-armv8-1</code>,
 </p>
 <p>In addition to determining which instructions are assembled, this option
 also affects the way in which the <code>.double</code> assembler directive behaves
 when assembling little-endian code.
 </p>
 <p>The default is dependent on the processor selected.  For Architecture 5 or
 later, the default is to assembler for VFP instructions; for earlier
 architectures the default is to assemble for FPA instructions.
 </p>
 <a name="index-_002dmthumb-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-mthumb</code></dt>
 <dd><p>This option specifies that the assembler should start assembling Thumb
 instructions; that is, it should behave as though the file starts with a
 <code>.code 16</code> directive.
 </p>
 <a name="index-_002dmthumb_002dinterwork-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-mthumb-interwork</code></dt>
 <dd><p>This option specifies that the output generated by the assembler should
 be marked as supporting interworking.
 </p>
 <a name="index-_002dmimplicit_002dit-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-mimplicit-it=never</code></dt>
 <dt><code>-mimplicit-it=always</code></dt>
 <dt><code>-mimplicit-it=arm</code></dt>
 <dt><code>-mimplicit-it=thumb</code></dt>
 <dd><p>The <code>-mimplicit-it</code> option controls the behavior of the assembler when
 conditional instructions are not enclosed in IT blocks.
 There are four possible behaviors.
 If <code>never</code> is specified, such constructs cause a warning in ARM
 code and an error in Thumb-2 code.
 If <code>always</code> is specified, such constructs are accepted in both
 ARM and Thumb-2 code, where the IT instruction is added implicitly.
 If <code>arm</code> is specified, such constructs are accepted in ARM code
 and cause an error in Thumb-2 code.
 If <code>thumb</code> is specified, such constructs cause a warning in ARM
 code and are accepted in Thumb-2 code.  If you omit this option, the
 behavior is equivalent to <code>-mimplicit-it=arm</code>.
 </p>
 <a name="index-_002dmapcs_002d26-command-line-option_002c-ARM"></a>
 <a name="index-_002dmapcs_002d32-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-mapcs-26</code></dt>
 <dt><code>-mapcs-32</code></dt>
 <dd><p>These options specify that the output generated by the assembler should
 be marked as supporting the indicated version of the Arm Procedure.
 Calling Standard.
 </p>
 <a name="index-_002dmatpcs-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-matpcs</code></dt>
 <dd><p>This option specifies that the output generated by the assembler should
 be marked as supporting the Arm/Thumb Procedure Calling Standard.  If
 enabled this option will cause the assembler to create an empty
 debugging section in the object file called .arm.atpcs.  Debuggers can
 use this to determine the ABI being used by.
 </p>
 <a name="index-_002dmapcs_002dfloat-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-mapcs-float</code></dt>
 <dd><p>This indicates the floating point variant of the APCS should be
 used.  In this variant floating point arguments are passed in FP
 registers rather than integer registers.
 </p>
 <a name="index-_002dmapcs_002dreentrant-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-mapcs-reentrant</code></dt>
 <dd><p>This indicates that the reentrant variant of the APCS should be used.
 This variant supports position independent code.
 </p>
 <a name="index-_002dmfloat_002dabi_003d-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-mfloat-abi=<var>abi</var></code></dt>
 <dd><p>This option specifies that the output generated by the assembler should be
 marked as using specified floating point ABI.
 The following values are recognized:
 <code>soft</code>,
 <code>softfp</code>
 and
 <code>hard</code>.
 </p>
 <a name="index-_002deabi_003d-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-meabi=<var>ver</var></code></dt>
 <dd><p>This option specifies which EABI version the produced object files should
 conform to.
 The following values are recognized:
 <code>gnu</code>,
 <code>4</code>
 and
 <code>5</code>.
 </p>
 <a name="index-_002dEB-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-EB</code></dt>
 <dd><p>This option specifies that the output generated by the assembler should
 be marked as being encoded for a big-endian processor.
 </p>
 <p>Note: If a program is being built for a system with big-endian data
 and little-endian instructions then it should be assembled with the
 <samp>-EB</samp> option, (all of it, code and data) and then linked with
 the <samp>--be8</samp> option.  This will reverse the endianness of the
 instructions back to little-endian, but leave the data as big-endian.
 </p>
 <a name="index-_002dEL-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-EL</code></dt>
 <dd><p>This option specifies that the output generated by the assembler should
 be marked as being encoded for a little-endian processor.
 </p>
 <a name="index-_002dk-command-line-option_002c-ARM"></a>
 <a name="index-PIC-code-generation-for-ARM"></a>
 </dd>
 <dt><code>-k</code></dt>
 <dd><p>This option specifies that the output of the assembler should be marked
 as position-independent code (PIC).
 </p>
 <a name="index-_002d_002dfix_002dv4bx-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>--fix-v4bx</code></dt>
 <dd><p>Allow <code>BX</code> instructions in ARMv4 code.  This is intended for use with
 the linker option of the same name.
 </p>
 <a name="index-_002dmwarn_002ddeprecated-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-mwarn-deprecated</code></dt>
 <dt><code>-mno-warn-deprecated</code></dt>
 <dd><p>Enable or disable warnings about using deprecated options or
 features.  The default is to warn.
 </p>
 <a name="index-_002dmccs-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-mccs</code></dt>
 <dd><p>Turns on CodeComposer Studio assembly syntax compatibility mode.
 </p>
 <a name="index-_002dmwarn_002dsyms-command-line-option_002c-ARM"></a>
 </dd>
 <dt><code>-mwarn-syms</code></dt>
 <dt><code>-mno-warn-syms</code></dt>
 <dd><p>Enable or disable warnings about symbols that match the names of ARM
 instructions.  The default is to warn.
 </p>
 </dd>
 </dl>


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	<a name="ARM-Options"></a>
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	Next: <a href="ARM-Syntax.html#ARM-Syntax" accesskey="n" rel="next">ARM Syntax</a>, Up: <a href="ARM_002dDependent.html#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a>   [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
	</div>
	<hr>
	<a name="Options-3"></a>
	<h4 class="subsection">9.4.1 Options</h4>
	<a name="index-ARM-options-_0028none_0029"></a>
	<a name="index-options-for-ARM-_0028none_0029"></a>

	<dl compact="compact">
	<dd>
	<a name="index-_002dmcpu_003d-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-mcpu=<var>processor</var>[+<var>extension</var>…]</code></dt>
	<dd><p>This option specifies the target processor. The assembler will issue an
	error message if an attempt is made to assemble an instruction which
	will not execute on the target processor. The following processor names are
	recognized:
	<code>arm1</code>,
	<code>arm2</code>,
	<code>arm250</code>,
	<code>arm3</code>,
	<code>arm6</code>,
	<code>arm60</code>,
	<code>arm600</code>,
	<code>arm610</code>,
	<code>arm620</code>,
	<code>arm7</code>,
	<code>arm7m</code>,
	<code>arm7d</code>,
	<code>arm7dm</code>,
	<code>arm7di</code>,
	<code>arm7dmi</code>,
	<code>arm70</code>,
	<code>arm700</code>,
	<code>arm700i</code>,
	<code>arm710</code>,
	<code>arm710t</code>,
	<code>arm720</code>,
	<code>arm720t</code>,
	<code>arm740t</code>,
	<code>arm710c</code>,
	<code>arm7100</code>,
	<code>arm7500</code>,
	<code>arm7500fe</code>,
	<code>arm7t</code>,
	<code>arm7tdmi</code>,
	<code>arm7tdmi-s</code>,
	<code>arm8</code>,
	<code>arm810</code>,
	<code>strongarm</code>,
	<code>strongarm1</code>,
	<code>strongarm110</code>,
	<code>strongarm1100</code>,
	<code>strongarm1110</code>,
	<code>arm9</code>,
	<code>arm920</code>,
	<code>arm920t</code>,
	<code>arm922t</code>,
	<code>arm940t</code>,
	<code>arm9tdmi</code>,
	<code>fa526</code> (Faraday FA526 processor),
	<code>fa626</code> (Faraday FA626 processor),
	<code>arm9e</code>,
	<code>arm926e</code>,
	<code>arm926ej-s</code>,
	<code>arm946e-r0</code>,
	<code>arm946e</code>,
	<code>arm946e-s</code>,
	<code>arm966e-r0</code>,
	<code>arm966e</code>,
	<code>arm966e-s</code>,
	<code>arm968e-s</code>,
	<code>arm10t</code>,
	<code>arm10tdmi</code>,
	<code>arm10e</code>,
	<code>arm1020</code>,
	<code>arm1020t</code>,
	<code>arm1020e</code>,
	<code>arm1022e</code>,
	<code>arm1026ej-s</code>,
	<code>fa606te</code> (Faraday FA606TE processor),
	<code>fa616te</code> (Faraday FA616TE processor),
	<code>fa626te</code> (Faraday FA626TE processor),
	<code>fmp626</code> (Faraday FMP626 processor),
	<code>fa726te</code> (Faraday FA726TE processor),
	<code>arm1136j-s</code>,
	<code>arm1136jf-s</code>,
	<code>arm1156t2-s</code>,
	<code>arm1156t2f-s</code>,
	<code>arm1176jz-s</code>,
	<code>arm1176jzf-s</code>,
	<code>mpcore</code>,
	<code>mpcorenovfp</code>,
	<code>cortex-a5</code>,
	<code>cortex-a7</code>,
	<code>cortex-a8</code>,
	<code>cortex-a9</code>,
	<code>cortex-a15</code>,
	<code>cortex-a53</code>,
	<code>cortex-a57</code>,
	<code>cortex-a72</code>,
	<code>cortex-r4</code>,
	<code>cortex-r4f</code>,
	<code>cortex-r5</code>,
	<code>cortex-r7</code>,
	<code>cortex-m7</code>,
	<code>cortex-m4</code>,
	<code>cortex-m3</code>,
	<code>cortex-m1</code>,
	<code>cortex-m0</code>,
	<code>cortex-m0plus</code>,
	<code>exynos-m1</code>,
	<code>marvell-pj4</code>,
	<code>marvell-whitney</code>,
	<code>xgene1</code>,
	<code>xgene2</code>,
	<code>ep9312</code> (ARM920 with Cirrus Maverick coprocessor),
	<code>i80200</code> (Intel XScale processor)
	<code>iwmmxt</code> (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
	and
	<code>xscale</code>.
	The special name <code>all</code> may be used to allow the
	assembler to accept instructions valid for any ARM processor.
	</p>
	<p>In addition to the basic instruction set, the assembler can be told to
	accept various extension mnemonics that extend the processor using the
	co-processor instruction space. For example, <code>-mcpu=arm920+maverick</code>
	is equivalent to specifying <code>-mcpu=ep9312</code>.
	</p>
	<p>Multiple extensions may be specified, separated by a <code>+</code>. The
	extensions should be specified in ascending alphabetical order.
	</p>
	<p>Some extensions may be restricted to particular architectures; this is
	documented in the list of extensions below.
	</p>
	<p>Extension mnemonics may also be removed from those the assembler accepts.
	This is done be prepending <code>no</code> to the option that adds the extension.
	Extensions that are removed should be listed after all extensions which have
	been added, again in ascending alphabetical order. For example,
	<code>-mcpu=ep9312+nomaverick</code> is equivalent to specifying <code>-mcpu=arm920</code>.
	</p>

	<p>The following extensions are currently supported:
	<code>crc</code>
	<code>crypto</code> (Cryptography Extensions for v8-A architecture, implies <code>fp+simd</code>),
	<code>fp</code> (Floating Point Extensions for v8-A architecture),
	<code>idiv</code> (Integer Divide Extensions for v7-A and v7-R architectures),
	<code>iwmmxt</code>,
	<code>iwmmxt2</code>,
	<code>xscale</code>,
	<code>maverick</code>,
	<code>mp</code> (Multiprocessing Extensions for v7-A and v7-R
	architectures),
	<code>os</code> (Operating System for v6M architecture),
	<code>sec</code> (Security Extensions for v6K and v7-A architectures),
	<code>simd</code> (Advanced SIMD Extensions for v8-A architecture, implies <code>fp</code>),
	<code>virt</code> (Virtualization Extensions for v7-A architecture, implies
	<code>idiv</code>),
	<code>pan</code> (Priviliged Access Never Extensions for v8-A architecture),
	<code>rdma</code> (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
	<code>simd</code>)
	and
	<code>xscale</code>.
	</p>
	<a name="index-_002dmarch_003d-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-march=<var>architecture</var>[+<var>extension</var>…]</code></dt>
	<dd><p>This option specifies the target architecture. The assembler will issue
	an error message if an attempt is made to assemble an instruction which
	will not execute on the target architecture. The following architecture
	names are recognized:
	<code>armv1</code>,
	<code>armv2</code>,
	<code>armv2a</code>,
	<code>armv2s</code>,
	<code>armv3</code>,
	<code>armv3m</code>,
	<code>armv4</code>,
	<code>armv4xm</code>,
	<code>armv4t</code>,
	<code>armv4txm</code>,
	<code>armv5</code>,
	<code>armv5t</code>,
	<code>armv5txm</code>,
	<code>armv5te</code>,
	<code>armv5texp</code>,
	<code>armv6</code>,
	<code>armv6j</code>,
	<code>armv6k</code>,
	<code>armv6z</code>,
	<code>armv6zk</code>,
	<code>armv6-m</code>,
	<code>armv6s-m</code>,
	<code>armv7</code>,
	<code>armv7-a</code>,
	<code>armv7ve</code>,
	<code>armv7-r</code>,
	<code>armv7-m</code>,
	<code>armv7e-m</code>,
	<code>armv8-a</code>,
	<code>armv8.1-a</code>,
	<code>iwmmxt</code>
	<code>iwmmxt2</code>
	and
	<code>xscale</code>.
	If both <code>-mcpu</code> and
	<code>-march</code> are specified, the assembler will use
	the setting for <code>-mcpu</code>.
	</p>
	<p>The architecture option can be extended with the same instruction set
	extension options as the <code>-mcpu</code> option.
	</p>
	<a name="index-_002dmfpu_003d-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-mfpu=<var>floating-point-format</var></code></dt>
	<dd>
	<p>This option specifies the floating point format to assemble for. The
	assembler will issue an error message if an attempt is made to assemble
	an instruction which will not execute on the target floating point unit.
	The following format options are recognized:
	<code>softfpa</code>,
	<code>fpe</code>,
	<code>fpe2</code>,
	<code>fpe3</code>,
	<code>fpa</code>,
	<code>fpa10</code>,
	<code>fpa11</code>,
	<code>arm7500fe</code>,
	<code>softvfp</code>,
	<code>softvfp+vfp</code>,
	<code>vfp</code>,
	<code>vfp10</code>,
	<code>vfp10-r0</code>,
	<code>vfp9</code>,
	<code>vfpxd</code>,
	<code>vfpv2</code>,
	<code>vfpv3</code>,
	<code>vfpv3-fp16</code>,
	<code>vfpv3-d16</code>,
	<code>vfpv3-d16-fp16</code>,
	<code>vfpv3xd</code>,
	<code>vfpv3xd-d16</code>,
	<code>vfpv4</code>,
	<code>vfpv4-d16</code>,
	<code>fpv4-sp-d16</code>,
	<code>fpv5-sp-d16</code>,
	<code>fpv5-d16</code>,
	<code>fp-armv8</code>,
	<code>arm1020t</code>,
	<code>arm1020e</code>,
	<code>arm1136jf-s</code>,
	<code>maverick</code>,
	<code>neon</code>,
	<code>neon-vfpv4</code>,
	<code>neon-fp-armv8</code>,
	<code>crypto-neon-fp-armv8</code>.
	and
	<code>neon-fp-armv8-1</code>,
	</p>
	<p>In addition to determining which instructions are assembled, this option
	also affects the way in which the <code>.double</code> assembler directive behaves
	when assembling little-endian code.
	</p>
	<p>The default is dependent on the processor selected. For Architecture 5 or
	later, the default is to assembler for VFP instructions; for earlier
	architectures the default is to assemble for FPA instructions.
	</p>
	<a name="index-_002dmthumb-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-mthumb</code></dt>
	<dd><p>This option specifies that the assembler should start assembling Thumb
	instructions; that is, it should behave as though the file starts with a
	<code>.code 16</code> directive.
	</p>
	<a name="index-_002dmthumb_002dinterwork-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-mthumb-interwork</code></dt>
	<dd><p>This option specifies that the output generated by the assembler should
	be marked as supporting interworking.
	</p>
	<a name="index-_002dmimplicit_002dit-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-mimplicit-it=never</code></dt>
	<dt><code>-mimplicit-it=always</code></dt>
	<dt><code>-mimplicit-it=arm</code></dt>
	<dt><code>-mimplicit-it=thumb</code></dt>
	<dd><p>The <code>-mimplicit-it</code> option controls the behavior of the assembler when
	conditional instructions are not enclosed in IT blocks.
	There are four possible behaviors.
	If <code>never</code> is specified, such constructs cause a warning in ARM
	code and an error in Thumb-2 code.
	If <code>always</code> is specified, such constructs are accepted in both
	ARM and Thumb-2 code, where the IT instruction is added implicitly.
	If <code>arm</code> is specified, such constructs are accepted in ARM code
	and cause an error in Thumb-2 code.
	If <code>thumb</code> is specified, such constructs cause a warning in ARM
	code and are accepted in Thumb-2 code. If you omit this option, the
	behavior is equivalent to <code>-mimplicit-it=arm</code>.
	</p>
	<a name="index-_002dmapcs_002d26-command-line-option_002c-ARM"></a>
	<a name="index-_002dmapcs_002d32-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-mapcs-26</code></dt>
	<dt><code>-mapcs-32</code></dt>
	<dd><p>These options specify that the output generated by the assembler should
	be marked as supporting the indicated version of the Arm Procedure.
	Calling Standard.
	</p>
	<a name="index-_002dmatpcs-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-matpcs</code></dt>
	<dd><p>This option specifies that the output generated by the assembler should
	be marked as supporting the Arm/Thumb Procedure Calling Standard. If
	enabled this option will cause the assembler to create an empty
	debugging section in the object file called .arm.atpcs. Debuggers can
	use this to determine the ABI being used by.
	</p>
	<a name="index-_002dmapcs_002dfloat-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-mapcs-float</code></dt>
	<dd><p>This indicates the floating point variant of the APCS should be
	used. In this variant floating point arguments are passed in FP
	registers rather than integer registers.
	</p>
	<a name="index-_002dmapcs_002dreentrant-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-mapcs-reentrant</code></dt>
	<dd><p>This indicates that the reentrant variant of the APCS should be used.
	This variant supports position independent code.
	</p>
	<a name="index-_002dmfloat_002dabi_003d-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-mfloat-abi=<var>abi</var></code></dt>
	<dd><p>This option specifies that the output generated by the assembler should be
	marked as using specified floating point ABI.
	The following values are recognized:
	<code>soft</code>,
	<code>softfp</code>
	and
	<code>hard</code>.
	</p>
	<a name="index-_002deabi_003d-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-meabi=<var>ver</var></code></dt>
	<dd><p>This option specifies which EABI version the produced object files should
	conform to.
	The following values are recognized:
	<code>gnu</code>,
	<code>4</code>
	and
	<code>5</code>.
	</p>
	<a name="index-_002dEB-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-EB</code></dt>
	<dd><p>This option specifies that the output generated by the assembler should
	be marked as being encoded for a big-endian processor.
	</p>
	<p>Note: If a program is being built for a system with big-endian data
	and little-endian instructions then it should be assembled with the
	<samp>-EB</samp> option, (all of it, code and data) and then linked with
	the <samp>--be8</samp> option. This will reverse the endianness of the
	instructions back to little-endian, but leave the data as big-endian.
	</p>
	<a name="index-_002dEL-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-EL</code></dt>
	<dd><p>This option specifies that the output generated by the assembler should
	be marked as being encoded for a little-endian processor.
	</p>
	<a name="index-_002dk-command-line-option_002c-ARM"></a>
	<a name="index-PIC-code-generation-for-ARM"></a>
	</dd>
	<dt><code>-k</code></dt>
	<dd><p>This option specifies that the output of the assembler should be marked
	as position-independent code (PIC).
	</p>
	<a name="index-_002d_002dfix_002dv4bx-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>--fix-v4bx</code></dt>
	<dd><p>Allow <code>BX</code> instructions in ARMv4 code. This is intended for use with
	the linker option of the same name.
	</p>
	<a name="index-_002dmwarn_002ddeprecated-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-mwarn-deprecated</code></dt>
	<dt><code>-mno-warn-deprecated</code></dt>
	<dd><p>Enable or disable warnings about using deprecated options or
	features. The default is to warn.
	</p>
	<a name="index-_002dmccs-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-mccs</code></dt>
	<dd><p>Turns on CodeComposer Studio assembly syntax compatibility mode.
	</p>
	<a name="index-_002dmwarn_002dsyms-command-line-option_002c-ARM"></a>
	</dd>
	<dt><code>-mwarn-syms</code></dt>
	<dt><code>-mno-warn-syms</code></dt>
	<dd><p>Enable or disable warnings about symbols that match the names of ARM
	instructions. The default is to warn.
	</p>
	</dd>
	</dl>


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