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| <p> |
| Previous: <a href="NDS32_002dRegs.html#NDS32_002dRegs" accesskey="p" rel="prev">NDS32-Regs</a>, Up: <a href="NDS32-Syntax.html#NDS32-Syntax" accesskey="u" rel="up">NDS32 Syntax</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p> |
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| <a name="Pseudo-Instructions"></a> |
| <h4 class="subsubsection">9.30.2.3 Pseudo Instructions</h4> |
| <dl compact="compact"> |
| <dt><code>li rt5,imm32</code></dt> |
| <dd><p>load 32-bit integer into register rt5. ‘<samp>sethi rt5,hi20(imm32)</samp>’ and then |
| ‘<samp>ori rt5,reg,lo12(imm32)</samp>’. |
| </p> |
| </dd> |
| <dt><code>la rt5,var</code></dt> |
| <dd><p>Load 32-bit address of var into register rt5. ‘<samp>sethi rt5,hi20(var)</samp>’ and |
| then ‘<samp>ori reg,rt5,lo12(var)</samp>’ |
| </p> |
| </dd> |
| <dt><code>l.[bhw] rt5,var</code></dt> |
| <dd><p>Load value of var into register rt5. ‘<samp>sethi $ta,hi20(var)</samp>’ and then |
| ‘<samp>l[bhw]i rt5,[$ta+lo12(var)]</samp>’ |
| </p> |
| </dd> |
| <dt><code>l.[bh]s rt5,var</code></dt> |
| <dd><p>Load value of var into register rt5. ‘<samp>sethi $ta,hi20(var)</samp>’ and then |
| ‘<samp>l[bh]si rt5,[$ta+lo12(var)]</samp>’ |
| </p> |
| </dd> |
| <dt><code>l.[bhw]p rt5,var,inc</code></dt> |
| <dd><p>Load value of var into register rt5 and increment $ta by amount inc. |
| ‘<samp>la $ta,var</samp>’ and then ‘<samp>l[bhw]i.bi rt5,[$ta],inc</samp>’ |
| </p> |
| </dd> |
| <dt><code>l.[bhw]pc rt5,inc</code></dt> |
| <dd><p>Continue loading value of var into register rt5 and increment $ta by amount inc. |
| ‘<samp>l[bhw]i.bi rt5,[$ta],inc.</samp>’ |
| </p> |
| </dd> |
| <dt><code>l.[bh]sp rt5,var,inc</code></dt> |
| <dd><p>Load value of var into register rt5 and increment $ta by amount inc. |
| ‘<samp>la $ta,var</samp>’ and then ‘<samp>l[bh]si.bi rt5,[$ta],inc</samp>’ |
| </p> |
| </dd> |
| <dt><code>l.[bh]spc rt5,inc</code></dt> |
| <dd><p>Continue loading value of var into register rt5 and increment $ta by amount inc. |
| ‘<samp>l[bh]si.bi rt5,[$ta],inc.</samp>’ |
| </p> |
| </dd> |
| <dt><code>s.[bhw] rt5,var</code></dt> |
| <dd><p>Store register rt5 to var. |
| ‘<samp>sethi $ta,hi20(var)</samp>’ and then ‘<samp>s[bhw]i rt5,[$ta+lo12(var)]</samp>’ |
| </p> |
| </dd> |
| <dt><code>s.[bhw]p rt5,var,inc</code></dt> |
| <dd><p>Store register rt5 to var and increment $ta by amount inc. |
| ‘<samp>la $ta,var</samp>’ and then ‘<samp>s[bhw]i.bi rt5,[$ta],inc</samp>’ |
| </p> |
| </dd> |
| <dt><code>s.[bhw]pc rt5,inc</code></dt> |
| <dd><p>Continue storing register rt5 to var and increment $ta by amount inc. |
| ‘<samp>s[bhw]i.bi rt5,[$ta],inc.</samp>’ |
| </p> |
| </dd> |
| <dt><code>not rt5,ra5</code></dt> |
| <dd><p>Alias of ‘<samp>nor rt5,ra5,ra5</samp>’. |
| </p> |
| </dd> |
| <dt><code>neg rt5,ra5</code></dt> |
| <dd><p>Alias of ‘<samp>subri rt5,ra5,0</samp>’. |
| </p> |
| </dd> |
| <dt><code>br rb5</code></dt> |
| <dd><p>Depending on how it is assembled, it is translated into ‘<samp>r5 rb5</samp>’ |
| or ‘<samp>jr rb5</samp>’. |
| </p> |
| </dd> |
| <dt><code>b label</code></dt> |
| <dd><p>Branch to label depending on how it is assembled, it is translated into |
| ‘<samp>j8 label</samp>’, ‘<samp>j label</samp>’, or "‘<samp>la $ta,label</samp>’ ‘<samp>br $ta</samp>’". |
| </p> |
| </dd> |
| <dt><code>bral rb5</code></dt> |
| <dd><p>Alias of jral br5 depending on how it is assembled, it is translated |
| into ‘<samp>jral5 rb5</samp>’ or ‘<samp>jral rb5</samp>’. |
| </p> |
| </dd> |
| <dt><code>bal fname</code></dt> |
| <dd><p>Alias of jal fname depending on how it is assembled, it is translated into |
| ‘<samp>jal fname</samp>’ or "‘<samp>la $ta,fname</samp>’ ‘<samp>bral $ta</samp>’". |
| </p> |
| </dd> |
| <dt><code>call fname</code></dt> |
| <dd><p>Call function fname same as ‘<samp>jal fname</samp>’. |
| </p> |
| </dd> |
| <dt><code>move rt5,ra5</code></dt> |
| <dd><p>For 16-bit, this is ‘<samp>mov55 rt5,ra5</samp>’. |
| For no 16-bit, this is ‘<samp>ori rt5,ra5,0</samp>’. |
| </p> |
| </dd> |
| <dt><code>move rt5,var</code></dt> |
| <dd><p>This is the same as ‘<samp>l.w rt5,var</samp>’. |
| </p> |
| </dd> |
| <dt><code>move rt5,imm32</code></dt> |
| <dd><p>This is the same as ‘<samp>li rt5,imm32</samp>’. |
| </p> |
| </dd> |
| <dt><code>pushm ra5,rb5</code></dt> |
| <dd><p>Push contents of registers from ra5 to rb5 into stack. |
| </p> |
| </dd> |
| <dt><code>push ra5</code></dt> |
| <dd><p>Push content of register ra5 into stack. (same ‘<samp>pushm ra5,ra5</samp>’). |
| </p> |
| </dd> |
| <dt><code>push.d var</code></dt> |
| <dd><p>Push value of double-word variable var into stack. |
| </p> |
| </dd> |
| <dt><code>push.w var</code></dt> |
| <dd><p>Push value of word variable var into stack. |
| </p> |
| </dd> |
| <dt><code>push.h var</code></dt> |
| <dd><p>Push value of half-word variable var into stack. |
| </p> |
| </dd> |
| <dt><code>push.b var</code></dt> |
| <dd><p>Push value of byte variable var into stack. |
| </p> |
| </dd> |
| <dt><code>pusha var</code></dt> |
| <dd><p>Push 32-bit address of variable var into stack. |
| </p> |
| </dd> |
| <dt><code>pushi imm32</code></dt> |
| <dd><p>Push 32-bit immediate value into stack. |
| </p> |
| </dd> |
| <dt><code>popm ra5,rb5</code></dt> |
| <dd><p>Pop top of stack values into registers ra5 to rb5. |
| </p> |
| </dd> |
| <dt><code>pop rt5</code></dt> |
| <dd><p>Pop top of stack value into register. (same as ‘<samp>popm rt5,rt5</samp>’.) |
| </p> |
| </dd> |
| <dt><code>pop.d var,ra5</code></dt> |
| <dd><p>Pop value of double-word variable var from stack using register ra5 |
| as 2nd scratch register. (1st is $ta) |
| </p> |
| </dd> |
| <dt><code>pop.w var,ra5</code></dt> |
| <dd><p>Pop value of word variable var from stack using register ra5. |
| </p> |
| </dd> |
| <dt><code>pop.h var,ra5</code></dt> |
| <dd><p>Pop value of half-word variable var from stack using register ra5. |
| </p> |
| </dd> |
| <dt><code>pop.b var,ra5</code></dt> |
| <dd><p>Pop value of byte variable var from stack using register ra5. |
| </p> |
| </dd> |
| </dl> |
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