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| <hr> |
| <a name="IBM-RS_002f6000-and-PowerPC-Options"></a> |
| <h4 class="subsection">3.17.37 IBM RS/6000 and PowerPC Options</h4> |
| <a name="index-RS_002f6000-and-PowerPC-Options"></a> |
| <a name="index-IBM-RS_002f6000-and-PowerPC-Options"></a> |
| |
| <p>These ‘<samp>-m</samp>’ options are defined for the IBM RS/6000 and PowerPC: |
| </p><dl compact="compact"> |
| <dt><code>-mpowerpc-gpopt</code></dt> |
| <dt><code>-mno-powerpc-gpopt</code></dt> |
| <dt><code>-mpowerpc-gfxopt</code></dt> |
| <dt><code>-mno-powerpc-gfxopt</code></dt> |
| <dt><code>-mpowerpc64</code></dt> |
| <dt><code>-mno-powerpc64</code></dt> |
| <dt><code>-mmfcrf</code></dt> |
| <dt><code>-mno-mfcrf</code></dt> |
| <dt><code>-mpopcntb</code></dt> |
| <dt><code>-mno-popcntb</code></dt> |
| <dt><code>-mpopcntd</code></dt> |
| <dt><code>-mno-popcntd</code></dt> |
| <dt><code>-mfprnd</code></dt> |
| <dt><code>-mno-fprnd</code></dt> |
| <dt><code>-mcmpb</code></dt> |
| <dt><code>-mno-cmpb</code></dt> |
| <dt><code>-mmfpgpr</code></dt> |
| <dt><code>-mno-mfpgpr</code></dt> |
| <dt><code>-mhard-dfp</code></dt> |
| <dt><code>-mno-hard-dfp</code></dt> |
| <dd><a name="index-mpowerpc_002dgpopt"></a> |
| <a name="index-mno_002dpowerpc_002dgpopt"></a> |
| <a name="index-mpowerpc_002dgfxopt"></a> |
| <a name="index-mno_002dpowerpc_002dgfxopt"></a> |
| <a name="index-mpowerpc64"></a> |
| <a name="index-mno_002dpowerpc64"></a> |
| <a name="index-mmfcrf"></a> |
| <a name="index-mno_002dmfcrf"></a> |
| <a name="index-mpopcntb"></a> |
| <a name="index-mno_002dpopcntb"></a> |
| <a name="index-mpopcntd"></a> |
| <a name="index-mno_002dpopcntd"></a> |
| <a name="index-mfprnd"></a> |
| <a name="index-mno_002dfprnd"></a> |
| <a name="index-mcmpb"></a> |
| <a name="index-mno_002dcmpb"></a> |
| <a name="index-mmfpgpr"></a> |
| <a name="index-mno_002dmfpgpr"></a> |
| <a name="index-mhard_002ddfp"></a> |
| <a name="index-mno_002dhard_002ddfp"></a> |
| <p>You use these options to specify which instructions are available on the |
| processor you are using. The default value of these options is |
| determined when configuring GCC. Specifying the |
| <samp>-mcpu=<var>cpu_type</var></samp> overrides the specification of these |
| options. We recommend you use the <samp>-mcpu=<var>cpu_type</var></samp> option |
| rather than the options listed above. |
| </p> |
| <p>Specifying <samp>-mpowerpc-gpopt</samp> allows |
| GCC to use the optional PowerPC architecture instructions in the |
| General Purpose group, including floating-point square root. Specifying |
| <samp>-mpowerpc-gfxopt</samp> allows GCC to |
| use the optional PowerPC architecture instructions in the Graphics |
| group, including floating-point select. |
| </p> |
| <p>The <samp>-mmfcrf</samp> option allows GCC to generate the move from |
| condition register field instruction implemented on the POWER4 |
| processor and other processors that support the PowerPC V2.01 |
| architecture. |
| The <samp>-mpopcntb</samp> option allows GCC to generate the popcount and |
| double-precision FP reciprocal estimate instruction implemented on the |
| POWER5 processor and other processors that support the PowerPC V2.02 |
| architecture. |
| The <samp>-mpopcntd</samp> option allows GCC to generate the popcount |
| instruction implemented on the POWER7 processor and other processors |
| that support the PowerPC V2.06 architecture. |
| The <samp>-mfprnd</samp> option allows GCC to generate the FP round to |
| integer instructions implemented on the POWER5+ processor and other |
| processors that support the PowerPC V2.03 architecture. |
| The <samp>-mcmpb</samp> option allows GCC to generate the compare bytes |
| instruction implemented on the POWER6 processor and other processors |
| that support the PowerPC V2.05 architecture. |
| The <samp>-mmfpgpr</samp> option allows GCC to generate the FP move to/from |
| general-purpose register instructions implemented on the POWER6X |
| processor and other processors that support the extended PowerPC V2.05 |
| architecture. |
| The <samp>-mhard-dfp</samp> option allows GCC to generate the decimal |
| floating-point instructions implemented on some POWER processors. |
| </p> |
| <p>The <samp>-mpowerpc64</samp> option allows GCC to generate the additional |
| 64-bit instructions that are found in the full PowerPC64 architecture |
| and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to |
| <samp>-mno-powerpc64</samp>. |
| </p> |
| </dd> |
| <dt><code>-mcpu=<var>cpu_type</var></code></dt> |
| <dd><a name="index-mcpu-8"></a> |
| <p>Set architecture type, register usage, and |
| instruction scheduling parameters for machine type <var>cpu_type</var>. |
| Supported values for <var>cpu_type</var> are ‘<samp>401</samp>’, ‘<samp>403</samp>’, |
| ‘<samp>405</samp>’, ‘<samp>405fp</samp>’, ‘<samp>440</samp>’, ‘<samp>440fp</samp>’, ‘<samp>464</samp>’, ‘<samp>464fp</samp>’, |
| ‘<samp>476</samp>’, ‘<samp>476fp</samp>’, ‘<samp>505</samp>’, ‘<samp>601</samp>’, ‘<samp>602</samp>’, ‘<samp>603</samp>’, |
| ‘<samp>603e</samp>’, ‘<samp>604</samp>’, ‘<samp>604e</samp>’, ‘<samp>620</samp>’, ‘<samp>630</samp>’, ‘<samp>740</samp>’, |
| ‘<samp>7400</samp>’, ‘<samp>7450</samp>’, ‘<samp>750</samp>’, ‘<samp>801</samp>’, ‘<samp>821</samp>’, ‘<samp>823</samp>’, |
| ‘<samp>860</samp>’, ‘<samp>970</samp>’, ‘<samp>8540</samp>’, ‘<samp>a2</samp>’, ‘<samp>e300c2</samp>’, |
| ‘<samp>e300c3</samp>’, ‘<samp>e500mc</samp>’, ‘<samp>e500mc64</samp>’, ‘<samp>e5500</samp>’, |
| ‘<samp>e6500</samp>’, ‘<samp>ec603e</samp>’, ‘<samp>G3</samp>’, ‘<samp>G4</samp>’, ‘<samp>G5</samp>’, |
| ‘<samp>titan</samp>’, ‘<samp>power3</samp>’, ‘<samp>power4</samp>’, ‘<samp>power5</samp>’, ‘<samp>power5+</samp>’, |
| ‘<samp>power6</samp>’, ‘<samp>power6x</samp>’, ‘<samp>power7</samp>’, ‘<samp>power8</samp>’, ‘<samp>powerpc</samp>’, |
| ‘<samp>powerpc64</samp>’, ‘<samp>powerpc64le</samp>’, and ‘<samp>rs64</samp>’. |
| </p> |
| <p><samp>-mcpu=powerpc</samp>, <samp>-mcpu=powerpc64</samp>, and |
| <samp>-mcpu=powerpc64le</samp> specify pure 32-bit PowerPC (either |
| endian), 64-bit big endian PowerPC and 64-bit little endian PowerPC |
| architecture machine types, with an appropriate, generic processor |
| model assumed for scheduling purposes. |
| </p> |
| <p>The other options specify a specific processor. Code generated under |
| those options runs best on that processor, and may not run at all on |
| others. |
| </p> |
| <p>The <samp>-mcpu</samp> options automatically enable or disable the |
| following options: |
| </p> |
| <div class="smallexample"> |
| <pre class="smallexample">-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple |
| -mpopcntb -mpopcntd -mpowerpc64 |
| -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float |
| -msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx |
| -mcrypto -mdirect-move -mpower8-fusion -mpower8-vector |
| -mquad-memory -mquad-memory-atomic |
| </pre></div> |
| |
| <p>The particular options set for any particular CPU varies between |
| compiler versions, depending on what setting seems to produce optimal |
| code for that CPU; it doesn’t necessarily reflect the actual hardware’s |
| capabilities. If you wish to set an individual option to a particular |
| value, you may specify it after the <samp>-mcpu</samp> option, like |
| <samp>-mcpu=970 -mno-altivec</samp>. |
| </p> |
| <p>On AIX, the <samp>-maltivec</samp> and <samp>-mpowerpc64</samp> options are |
| not enabled or disabled by the <samp>-mcpu</samp> option at present because |
| AIX does not have full support for these options. You may still |
| enable or disable them individually if you’re sure it’ll work in your |
| environment. |
| </p> |
| </dd> |
| <dt><code>-mtune=<var>cpu_type</var></code></dt> |
| <dd><a name="index-mtune-10"></a> |
| <p>Set the instruction scheduling parameters for machine type |
| <var>cpu_type</var>, but do not set the architecture type or register usage, |
| as <samp>-mcpu=<var>cpu_type</var></samp> does. The same |
| values for <var>cpu_type</var> are used for <samp>-mtune</samp> as for |
| <samp>-mcpu</samp>. If both are specified, the code generated uses the |
| architecture and registers set by <samp>-mcpu</samp>, but the |
| scheduling parameters set by <samp>-mtune</samp>. |
| </p> |
| </dd> |
| <dt><code>-mcmodel=small</code></dt> |
| <dd><a name="index-mcmodel_003dsmall-1"></a> |
| <p>Generate PowerPC64 code for the small model: The TOC is limited to |
| 64k. |
| </p> |
| </dd> |
| <dt><code>-mcmodel=medium</code></dt> |
| <dd><a name="index-mcmodel_003dmedium"></a> |
| <p>Generate PowerPC64 code for the medium model: The TOC and other static |
| data may be up to a total of 4G in size. |
| </p> |
| </dd> |
| <dt><code>-mcmodel=large</code></dt> |
| <dd><a name="index-mcmodel_003dlarge-1"></a> |
| <p>Generate PowerPC64 code for the large model: The TOC may be up to 4G |
| in size. Other data and code is only limited by the 64-bit address |
| space. |
| </p> |
| </dd> |
| <dt><code>-maltivec</code></dt> |
| <dt><code>-mno-altivec</code></dt> |
| <dd><a name="index-maltivec"></a> |
| <a name="index-mno_002daltivec"></a> |
| <p>Generate code that uses (does not use) AltiVec instructions, and also |
| enable the use of built-in functions that allow more direct access to |
| the AltiVec instruction set. You may also need to set |
| <samp>-mabi=altivec</samp> to adjust the current ABI with AltiVec ABI |
| enhancements. |
| </p> |
| <p>When <samp>-maltivec</samp> is used, rather than <samp>-maltivec=le</samp> or |
| <samp>-maltivec=be</samp>, the element order for Altivec intrinsics such |
| as <code>vec_splat</code>, <code>vec_extract</code>, and <code>vec_insert</code> |
| match array element order corresponding to the endianness of the |
| target. That is, element zero identifies the leftmost element in a |
| vector register when targeting a big-endian platform, and identifies |
| the rightmost element in a vector register when targeting a |
| little-endian platform. |
| </p> |
| </dd> |
| <dt><code>-maltivec=be</code></dt> |
| <dd><a name="index-maltivec_003dbe"></a> |
| <p>Generate Altivec instructions using big-endian element order, |
| regardless of whether the target is big- or little-endian. This is |
| the default when targeting a big-endian platform. |
| </p> |
| <p>The element order is used to interpret element numbers in Altivec |
| intrinsics such as <code>vec_splat</code>, <code>vec_extract</code>, and |
| <code>vec_insert</code>. By default, these match array element order |
| corresponding to the endianness for the target. |
| </p> |
| </dd> |
| <dt><code>-maltivec=le</code></dt> |
| <dd><a name="index-maltivec_003dle"></a> |
| <p>Generate Altivec instructions using little-endian element order, |
| regardless of whether the target is big- or little-endian. This is |
| the default when targeting a little-endian platform. This option is |
| currently ignored when targeting a big-endian platform. |
| </p> |
| <p>The element order is used to interpret element numbers in Altivec |
| intrinsics such as <code>vec_splat</code>, <code>vec_extract</code>, and |
| <code>vec_insert</code>. By default, these match array element order |
| corresponding to the endianness for the target. |
| </p> |
| </dd> |
| <dt><code>-mvrsave</code></dt> |
| <dt><code>-mno-vrsave</code></dt> |
| <dd><a name="index-mvrsave"></a> |
| <a name="index-mno_002dvrsave"></a> |
| <p>Generate VRSAVE instructions when generating AltiVec code. |
| </p> |
| </dd> |
| <dt><code>-mgen-cell-microcode</code></dt> |
| <dd><a name="index-mgen_002dcell_002dmicrocode"></a> |
| <p>Generate Cell microcode instructions. |
| </p> |
| </dd> |
| <dt><code>-mwarn-cell-microcode</code></dt> |
| <dd><a name="index-mwarn_002dcell_002dmicrocode"></a> |
| <p>Warn when a Cell microcode instruction is emitted. An example |
| of a Cell microcode instruction is a variable shift. |
| </p> |
| </dd> |
| <dt><code>-msecure-plt</code></dt> |
| <dd><a name="index-msecure_002dplt"></a> |
| <p>Generate code that allows <code>ld</code> and <code>ld.so</code> |
| to build executables and shared |
| libraries with non-executable <code>.plt</code> and <code>.got</code> sections. |
| This is a PowerPC |
| 32-bit SYSV ABI option. |
| </p> |
| </dd> |
| <dt><code>-mbss-plt</code></dt> |
| <dd><a name="index-mbss_002dplt"></a> |
| <p>Generate code that uses a BSS <code>.plt</code> section that <code>ld.so</code> |
| fills in, and |
| requires <code>.plt</code> and <code>.got</code> |
| sections that are both writable and executable. |
| This is a PowerPC 32-bit SYSV ABI option. |
| </p> |
| </dd> |
| <dt><code>-misel</code></dt> |
| <dt><code>-mno-isel</code></dt> |
| <dd><a name="index-misel"></a> |
| <a name="index-mno_002disel"></a> |
| <p>This switch enables or disables the generation of ISEL instructions. |
| </p> |
| </dd> |
| <dt><code>-misel=<var>yes/no</var></code></dt> |
| <dd><p>This switch has been deprecated. Use <samp>-misel</samp> and |
| <samp>-mno-isel</samp> instead. |
| </p> |
| </dd> |
| <dt><code>-mspe</code></dt> |
| <dt><code>-mno-spe</code></dt> |
| <dd><a name="index-mspe"></a> |
| <a name="index-mno_002dspe"></a> |
| <p>This switch enables or disables the generation of SPE simd |
| instructions. |
| </p> |
| </dd> |
| <dt><code>-mpaired</code></dt> |
| <dt><code>-mno-paired</code></dt> |
| <dd><a name="index-mpaired"></a> |
| <a name="index-mno_002dpaired"></a> |
| <p>This switch enables or disables the generation of PAIRED simd |
| instructions. |
| </p> |
| </dd> |
| <dt><code>-mspe=<var>yes/no</var></code></dt> |
| <dd><p>This option has been deprecated. Use <samp>-mspe</samp> and |
| <samp>-mno-spe</samp> instead. |
| </p> |
| </dd> |
| <dt><code>-mvsx</code></dt> |
| <dt><code>-mno-vsx</code></dt> |
| <dd><a name="index-mvsx"></a> |
| <a name="index-mno_002dvsx"></a> |
| <p>Generate code that uses (does not use) vector/scalar (VSX) |
| instructions, and also enable the use of built-in functions that allow |
| more direct access to the VSX instruction set. |
| </p> |
| </dd> |
| <dt><code>-mcrypto</code></dt> |
| <dt><code>-mno-crypto</code></dt> |
| <dd><a name="index-mcrypto"></a> |
| <a name="index-mno_002dcrypto"></a> |
| <p>Enable the use (disable) of the built-in functions that allow direct |
| access to the cryptographic instructions that were added in version |
| 2.07 of the PowerPC ISA. |
| </p> |
| </dd> |
| <dt><code>-mdirect-move</code></dt> |
| <dt><code>-mno-direct-move</code></dt> |
| <dd><a name="index-mdirect_002dmove"></a> |
| <a name="index-mno_002ddirect_002dmove"></a> |
| <p>Generate code that uses (does not use) the instructions to move data |
| between the general purpose registers and the vector/scalar (VSX) |
| registers that were added in version 2.07 of the PowerPC ISA. |
| </p> |
| </dd> |
| <dt><code>-mpower8-fusion</code></dt> |
| <dt><code>-mno-power8-fusion</code></dt> |
| <dd><a name="index-mpower8_002dfusion"></a> |
| <a name="index-mno_002dpower8_002dfusion"></a> |
| <p>Generate code that keeps (does not keeps) some integer operations |
| adjacent so that the instructions can be fused together on power8 and |
| later processors. |
| </p> |
| </dd> |
| <dt><code>-mpower8-vector</code></dt> |
| <dt><code>-mno-power8-vector</code></dt> |
| <dd><a name="index-mpower8_002dvector"></a> |
| <a name="index-mno_002dpower8_002dvector"></a> |
| <p>Generate code that uses (does not use) the vector and scalar |
| instructions that were added in version 2.07 of the PowerPC ISA. Also |
| enable the use of built-in functions that allow more direct access to |
| the vector instructions. |
| </p> |
| </dd> |
| <dt><code>-mquad-memory</code></dt> |
| <dt><code>-mno-quad-memory</code></dt> |
| <dd><a name="index-mquad_002dmemory"></a> |
| <a name="index-mno_002dquad_002dmemory"></a> |
| <p>Generate code that uses (does not use) the non-atomic quad word memory |
| instructions. The <samp>-mquad-memory</samp> option requires use of |
| 64-bit mode. |
| </p> |
| </dd> |
| <dt><code>-mquad-memory-atomic</code></dt> |
| <dt><code>-mno-quad-memory-atomic</code></dt> |
| <dd><a name="index-mquad_002dmemory_002datomic"></a> |
| <a name="index-mno_002dquad_002dmemory_002datomic"></a> |
| <p>Generate code that uses (does not use) the atomic quad word memory |
| instructions. The <samp>-mquad-memory-atomic</samp> option requires use of |
| 64-bit mode. |
| </p> |
| </dd> |
| <dt><code>-mupper-regs-df</code></dt> |
| <dt><code>-mno-upper-regs-df</code></dt> |
| <dd><a name="index-mupper_002dregs_002ddf"></a> |
| <a name="index-mno_002dupper_002dregs_002ddf"></a> |
| <p>Generate code that uses (does not use) the scalar double precision |
| instructions that target all 64 registers in the vector/scalar |
| floating point register set that were added in version 2.06 of the |
| PowerPC ISA. <samp>-mupper-regs-df</samp> is turned on by default if you |
| use any of the <samp>-mcpu=power7</samp>, <samp>-mcpu=power8</samp>, or |
| <samp>-mvsx</samp> options. |
| </p> |
| </dd> |
| <dt><code>-mupper-regs-sf</code></dt> |
| <dt><code>-mno-upper-regs-sf</code></dt> |
| <dd><a name="index-mupper_002dregs_002dsf"></a> |
| <a name="index-mno_002dupper_002dregs_002dsf"></a> |
| <p>Generate code that uses (does not use) the scalar single precision |
| instructions that target all 64 registers in the vector/scalar |
| floating point register set that were added in version 2.07 of the |
| PowerPC ISA. <samp>-mupper-regs-sf</samp> is turned on by default if you |
| use either of the <samp>-mcpu=power8</samp> or <samp>-mpower8-vector</samp> |
| options. |
| </p> |
| </dd> |
| <dt><code>-mupper-regs</code></dt> |
| <dt><code>-mno-upper-regs</code></dt> |
| <dd><a name="index-mupper_002dregs"></a> |
| <a name="index-mno_002dupper_002dregs"></a> |
| <p>Generate code that uses (does not use) the scalar |
| instructions that target all 64 registers in the vector/scalar |
| floating point register set, depending on the model of the machine. |
| </p> |
| <p>If the <samp>-mno-upper-regs</samp> option is used, it turns off both |
| <samp>-mupper-regs-sf</samp> and <samp>-mupper-regs-df</samp> options. |
| </p> |
| </dd> |
| <dt><code>-mfloat-gprs=<var>yes/single/double/no</var></code></dt> |
| <dt><code>-mfloat-gprs</code></dt> |
| <dd><a name="index-mfloat_002dgprs"></a> |
| <p>This switch enables or disables the generation of floating-point |
| operations on the general-purpose registers for architectures that |
| support it. |
| </p> |
| <p>The argument ‘<samp>yes</samp>’ or ‘<samp>single</samp>’ enables the use of |
| single-precision floating-point operations. |
| </p> |
| <p>The argument ‘<samp>double</samp>’ enables the use of single and |
| double-precision floating-point operations. |
| </p> |
| <p>The argument ‘<samp>no</samp>’ disables floating-point operations on the |
| general-purpose registers. |
| </p> |
| <p>This option is currently only available on the MPC854x. |
| </p> |
| </dd> |
| <dt><code>-m32</code></dt> |
| <dt><code>-m64</code></dt> |
| <dd><a name="index-m32-1"></a> |
| <a name="index-m64-1"></a> |
| <p>Generate code for 32-bit or 64-bit environments of Darwin and SVR4 |
| targets (including GNU/Linux). The 32-bit environment sets int, long |
| and pointer to 32 bits and generates code that runs on any PowerPC |
| variant. The 64-bit environment sets int to 32 bits and long and |
| pointer to 64 bits, and generates code for PowerPC64, as for |
| <samp>-mpowerpc64</samp>. |
| </p> |
| </dd> |
| <dt><code>-mfull-toc</code></dt> |
| <dt><code>-mno-fp-in-toc</code></dt> |
| <dt><code>-mno-sum-in-toc</code></dt> |
| <dt><code>-mminimal-toc</code></dt> |
| <dd><a name="index-mfull_002dtoc"></a> |
| <a name="index-mno_002dfp_002din_002dtoc"></a> |
| <a name="index-mno_002dsum_002din_002dtoc"></a> |
| <a name="index-mminimal_002dtoc"></a> |
| <p>Modify generation of the TOC (Table Of Contents), which is created for |
| every executable file. The <samp>-mfull-toc</samp> option is selected by |
| default. In that case, GCC allocates at least one TOC entry for |
| each unique non-automatic variable reference in your program. GCC |
| also places floating-point constants in the TOC. However, only |
| 16,384 entries are available in the TOC. |
| </p> |
| <p>If you receive a linker error message that saying you have overflowed |
| the available TOC space, you can reduce the amount of TOC space used |
| with the <samp>-mno-fp-in-toc</samp> and <samp>-mno-sum-in-toc</samp> options. |
| <samp>-mno-fp-in-toc</samp> prevents GCC from putting floating-point |
| constants in the TOC and <samp>-mno-sum-in-toc</samp> forces GCC to |
| generate code to calculate the sum of an address and a constant at |
| run time instead of putting that sum into the TOC. You may specify one |
| or both of these options. Each causes GCC to produce very slightly |
| slower and larger code at the expense of conserving TOC space. |
| </p> |
| <p>If you still run out of space in the TOC even when you specify both of |
| these options, specify <samp>-mminimal-toc</samp> instead. This option causes |
| GCC to make only one TOC entry for every file. When you specify this |
| option, GCC produces code that is slower and larger but which |
| uses extremely little TOC space. You may wish to use this option |
| only on files that contain less frequently-executed code. |
| </p> |
| </dd> |
| <dt><code>-maix64</code></dt> |
| <dt><code>-maix32</code></dt> |
| <dd><a name="index-maix64"></a> |
| <a name="index-maix32"></a> |
| <p>Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit |
| <code>long</code> type, and the infrastructure needed to support them. |
| Specifying <samp>-maix64</samp> implies <samp>-mpowerpc64</samp>, |
| while <samp>-maix32</samp> disables the 64-bit ABI and |
| implies <samp>-mno-powerpc64</samp>. GCC defaults to <samp>-maix32</samp>. |
| </p> |
| </dd> |
| <dt><code>-mxl-compat</code></dt> |
| <dt><code>-mno-xl-compat</code></dt> |
| <dd><a name="index-mxl_002dcompat"></a> |
| <a name="index-mno_002dxl_002dcompat"></a> |
| <p>Produce code that conforms more closely to IBM XL compiler semantics |
| when using AIX-compatible ABI. Pass floating-point arguments to |
| prototyped functions beyond the register save area (RSA) on the stack |
| in addition to argument FPRs. Do not assume that most significant |
| double in 128-bit long double value is properly rounded when comparing |
| values and converting to double. Use XL symbol names for long double |
| support routines. |
| </p> |
| <p>The AIX calling convention was extended but not initially documented to |
| handle an obscure K&R C case of calling a function that takes the |
| address of its arguments with fewer arguments than declared. IBM XL |
| compilers access floating-point arguments that do not fit in the |
| RSA from the stack when a subroutine is compiled without |
| optimization. Because always storing floating-point arguments on the |
| stack is inefficient and rarely needed, this option is not enabled by |
| default and only is necessary when calling subroutines compiled by IBM |
| XL compilers without optimization. |
| </p> |
| </dd> |
| <dt><code>-mpe</code></dt> |
| <dd><a name="index-mpe"></a> |
| <p>Support <em>IBM RS/6000 SP</em> <em>Parallel Environment</em> (PE). Link an |
| application written to use message passing with special startup code to |
| enable the application to run. The system must have PE installed in the |
| standard location (<samp>/usr/lpp/ppe.poe/</samp>), or the <samp>specs</samp> file |
| must be overridden with the <samp>-specs=</samp> option to specify the |
| appropriate directory location. The Parallel Environment does not |
| support threads, so the <samp>-mpe</samp> option and the <samp>-pthread</samp> |
| option are incompatible. |
| </p> |
| </dd> |
| <dt><code>-malign-natural</code></dt> |
| <dt><code>-malign-power</code></dt> |
| <dd><a name="index-malign_002dnatural"></a> |
| <a name="index-malign_002dpower"></a> |
| <p>On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option |
| <samp>-malign-natural</samp> overrides the ABI-defined alignment of larger |
| types, such as floating-point doubles, on their natural size-based boundary. |
| The option <samp>-malign-power</samp> instructs GCC to follow the ABI-specified |
| alignment rules. GCC defaults to the standard alignment defined in the ABI. |
| </p> |
| <p>On 64-bit Darwin, natural alignment is the default, and <samp>-malign-power</samp> |
| is not supported. |
| </p> |
| </dd> |
| <dt><code>-msoft-float</code></dt> |
| <dt><code>-mhard-float</code></dt> |
| <dd><a name="index-msoft_002dfloat-8"></a> |
| <a name="index-mhard_002dfloat-4"></a> |
| <p>Generate code that does not use (uses) the floating-point register set. |
| Software floating-point emulation is provided if you use the |
| <samp>-msoft-float</samp> option, and pass the option to GCC when linking. |
| </p> |
| </dd> |
| <dt><code>-msingle-float</code></dt> |
| <dt><code>-mdouble-float</code></dt> |
| <dd><a name="index-msingle_002dfloat-1"></a> |
| <a name="index-mdouble_002dfloat-1"></a> |
| <p>Generate code for single- or double-precision floating-point operations. |
| <samp>-mdouble-float</samp> implies <samp>-msingle-float</samp>. |
| </p> |
| </dd> |
| <dt><code>-msimple-fpu</code></dt> |
| <dd><a name="index-msimple_002dfpu"></a> |
| <p>Do not generate <code>sqrt</code> and <code>div</code> instructions for hardware |
| floating-point unit. |
| </p> |
| </dd> |
| <dt><code>-mfpu=<var>name</var></code></dt> |
| <dd><a name="index-mfpu-2"></a> |
| <p>Specify type of floating-point unit. Valid values for <var>name</var> are |
| ‘<samp>sp_lite</samp>’ (equivalent to <samp>-msingle-float -msimple-fpu</samp>), |
| ‘<samp>dp_lite</samp>’ (equivalent to <samp>-mdouble-float -msimple-fpu</samp>), |
| ‘<samp>sp_full</samp>’ (equivalent to <samp>-msingle-float</samp>), |
| and ‘<samp>dp_full</samp>’ (equivalent to <samp>-mdouble-float</samp>). |
| </p> |
| </dd> |
| <dt><code>-mxilinx-fpu</code></dt> |
| <dd><a name="index-mxilinx_002dfpu"></a> |
| <p>Perform optimizations for the floating-point unit on Xilinx PPC 405/440. |
| </p> |
| </dd> |
| <dt><code>-mmultiple</code></dt> |
| <dt><code>-mno-multiple</code></dt> |
| <dd><a name="index-mmultiple"></a> |
| <a name="index-mno_002dmultiple"></a> |
| <p>Generate code that uses (does not use) the load multiple word |
| instructions and the store multiple word instructions. These |
| instructions are generated by default on POWER systems, and not |
| generated on PowerPC systems. Do not use <samp>-mmultiple</samp> on little-endian |
| PowerPC systems, since those instructions do not work when the |
| processor is in little-endian mode. The exceptions are PPC740 and |
| PPC750 which permit these instructions in little-endian mode. |
| </p> |
| </dd> |
| <dt><code>-mstring</code></dt> |
| <dt><code>-mno-string</code></dt> |
| <dd><a name="index-mstring"></a> |
| <a name="index-mno_002dstring"></a> |
| <p>Generate code that uses (does not use) the load string instructions |
| and the store string word instructions to save multiple registers and |
| do small block moves. These instructions are generated by default on |
| POWER systems, and not generated on PowerPC systems. Do not use |
| <samp>-mstring</samp> on little-endian PowerPC systems, since those |
| instructions do not work when the processor is in little-endian mode. |
| The exceptions are PPC740 and PPC750 which permit these instructions |
| in little-endian mode. |
| </p> |
| </dd> |
| <dt><code>-mupdate</code></dt> |
| <dt><code>-mno-update</code></dt> |
| <dd><a name="index-mupdate"></a> |
| <a name="index-mno_002dupdate"></a> |
| <p>Generate code that uses (does not use) the load or store instructions |
| that update the base register to the address of the calculated memory |
| location. These instructions are generated by default. If you use |
| <samp>-mno-update</samp>, there is a small window between the time that the |
| stack pointer is updated and the address of the previous frame is |
| stored, which means code that walks the stack frame across interrupts or |
| signals may get corrupted data. |
| </p> |
| </dd> |
| <dt><code>-mavoid-indexed-addresses</code></dt> |
| <dt><code>-mno-avoid-indexed-addresses</code></dt> |
| <dd><a name="index-mavoid_002dindexed_002daddresses"></a> |
| <a name="index-mno_002davoid_002dindexed_002daddresses"></a> |
| <p>Generate code that tries to avoid (not avoid) the use of indexed load |
| or store instructions. These instructions can incur a performance |
| penalty on Power6 processors in certain situations, such as when |
| stepping through large arrays that cross a 16M boundary. This option |
| is enabled by default when targeting Power6 and disabled otherwise. |
| </p> |
| </dd> |
| <dt><code>-mfused-madd</code></dt> |
| <dt><code>-mno-fused-madd</code></dt> |
| <dd><a name="index-mfused_002dmadd-2"></a> |
| <a name="index-mno_002dfused_002dmadd-2"></a> |
| <p>Generate code that uses (does not use) the floating-point multiply and |
| accumulate instructions. These instructions are generated by default |
| if hardware floating point is used. The machine-dependent |
| <samp>-mfused-madd</samp> option is now mapped to the machine-independent |
| <samp>-ffp-contract=fast</samp> option, and <samp>-mno-fused-madd</samp> is |
| mapped to <samp>-ffp-contract=off</samp>. |
| </p> |
| </dd> |
| <dt><code>-mmulhw</code></dt> |
| <dt><code>-mno-mulhw</code></dt> |
| <dd><a name="index-mmulhw"></a> |
| <a name="index-mno_002dmulhw"></a> |
| <p>Generate code that uses (does not use) the half-word multiply and |
| multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. |
| These instructions are generated by default when targeting those |
| processors. |
| </p> |
| </dd> |
| <dt><code>-mdlmzb</code></dt> |
| <dt><code>-mno-dlmzb</code></dt> |
| <dd><a name="index-mdlmzb"></a> |
| <a name="index-mno_002ddlmzb"></a> |
| <p>Generate code that uses (does not use) the string-search ‘<samp>dlmzb</samp>’ |
| instruction on the IBM 405, 440, 464 and 476 processors. This instruction is |
| generated by default when targeting those processors. |
| </p> |
| </dd> |
| <dt><code>-mno-bit-align</code></dt> |
| <dt><code>-mbit-align</code></dt> |
| <dd><a name="index-mno_002dbit_002dalign"></a> |
| <a name="index-mbit_002dalign"></a> |
| <p>On System V.4 and embedded PowerPC systems do not (do) force structures |
| and unions that contain bit-fields to be aligned to the base type of the |
| bit-field. |
| </p> |
| <p>For example, by default a structure containing nothing but 8 |
| <code>unsigned</code> bit-fields of length 1 is aligned to a 4-byte |
| boundary and has a size of 4 bytes. By using <samp>-mno-bit-align</samp>, |
| the structure is aligned to a 1-byte boundary and is 1 byte in |
| size. |
| </p> |
| </dd> |
| <dt><code>-mno-strict-align</code></dt> |
| <dt><code>-mstrict-align</code></dt> |
| <dd><a name="index-mno_002dstrict_002dalign-1"></a> |
| <a name="index-mstrict_002dalign-2"></a> |
| <p>On System V.4 and embedded PowerPC systems do not (do) assume that |
| unaligned memory references are handled by the system. |
| </p> |
| </dd> |
| <dt><code>-mrelocatable</code></dt> |
| <dt><code>-mno-relocatable</code></dt> |
| <dd><a name="index-mrelocatable"></a> |
| <a name="index-mno_002drelocatable"></a> |
| <p>Generate code that allows (does not allow) a static executable to be |
| relocated to a different address at run time. A simple embedded |
| PowerPC system loader should relocate the entire contents of |
| <code>.got2</code> and 4-byte locations listed in the <code>.fixup</code> section, |
| a table of 32-bit addresses generated by this option. For this to |
| work, all objects linked together must be compiled with |
| <samp>-mrelocatable</samp> or <samp>-mrelocatable-lib</samp>. |
| <samp>-mrelocatable</samp> code aligns the stack to an 8-byte boundary. |
| </p> |
| </dd> |
| <dt><code>-mrelocatable-lib</code></dt> |
| <dt><code>-mno-relocatable-lib</code></dt> |
| <dd><a name="index-mrelocatable_002dlib"></a> |
| <a name="index-mno_002drelocatable_002dlib"></a> |
| <p>Like <samp>-mrelocatable</samp>, <samp>-mrelocatable-lib</samp> generates a |
| <code>.fixup</code> section to allow static executables to be relocated at |
| run time, but <samp>-mrelocatable-lib</samp> does not use the smaller stack |
| alignment of <samp>-mrelocatable</samp>. Objects compiled with |
| <samp>-mrelocatable-lib</samp> may be linked with objects compiled with |
| any combination of the <samp>-mrelocatable</samp> options. |
| </p> |
| </dd> |
| <dt><code>-mno-toc</code></dt> |
| <dt><code>-mtoc</code></dt> |
| <dd><a name="index-mno_002dtoc"></a> |
| <a name="index-mtoc"></a> |
| <p>On System V.4 and embedded PowerPC systems do not (do) assume that |
| register 2 contains a pointer to a global area pointing to the addresses |
| used in the program. |
| </p> |
| </dd> |
| <dt><code>-mlittle</code></dt> |
| <dt><code>-mlittle-endian</code></dt> |
| <dd><a name="index-mlittle"></a> |
| <a name="index-mlittle_002dendian-8"></a> |
| <p>On System V.4 and embedded PowerPC systems compile code for the |
| processor in little-endian mode. The <samp>-mlittle-endian</samp> option is |
| the same as <samp>-mlittle</samp>. |
| </p> |
| </dd> |
| <dt><code>-mbig</code></dt> |
| <dt><code>-mbig-endian</code></dt> |
| <dd><a name="index-mbig"></a> |
| <a name="index-mbig_002dendian-8"></a> |
| <p>On System V.4 and embedded PowerPC systems compile code for the |
| processor in big-endian mode. The <samp>-mbig-endian</samp> option is |
| the same as <samp>-mbig</samp>. |
| </p> |
| </dd> |
| <dt><code>-mdynamic-no-pic</code></dt> |
| <dd><a name="index-mdynamic_002dno_002dpic"></a> |
| <p>On Darwin and Mac OS X systems, compile code so that it is not |
| relocatable, but that its external references are relocatable. The |
| resulting code is suitable for applications, but not shared |
| libraries. |
| </p> |
| </dd> |
| <dt><code>-msingle-pic-base</code></dt> |
| <dd><a name="index-msingle_002dpic_002dbase-1"></a> |
| <p>Treat the register used for PIC addressing as read-only, rather than |
| loading it in the prologue for each function. The runtime system is |
| responsible for initializing this register with an appropriate value |
| before execution begins. |
| </p> |
| </dd> |
| <dt><code>-mprioritize-restricted-insns=<var>priority</var></code></dt> |
| <dd><a name="index-mprioritize_002drestricted_002dinsns"></a> |
| <p>This option controls the priority that is assigned to |
| dispatch-slot restricted instructions during the second scheduling |
| pass. The argument <var>priority</var> takes the value ‘<samp>0</samp>’, ‘<samp>1</samp>’, |
| or ‘<samp>2</samp>’ to assign no, highest, or second-highest (respectively) |
| priority to dispatch-slot restricted |
| instructions. |
| </p> |
| </dd> |
| <dt><code>-msched-costly-dep=<var>dependence_type</var></code></dt> |
| <dd><a name="index-msched_002dcostly_002ddep"></a> |
| <p>This option controls which dependences are considered costly |
| by the target during instruction scheduling. The argument |
| <var>dependence_type</var> takes one of the following values: |
| </p> |
| <dl compact="compact"> |
| <dt>‘<samp>no</samp>’</dt> |
| <dd><p>No dependence is costly. |
| </p> |
| </dd> |
| <dt>‘<samp>all</samp>’</dt> |
| <dd><p>All dependences are costly. |
| </p> |
| </dd> |
| <dt>‘<samp>true_store_to_load</samp>’</dt> |
| <dd><p>A true dependence from store to load is costly. |
| </p> |
| </dd> |
| <dt>‘<samp>store_to_load</samp>’</dt> |
| <dd><p>Any dependence from store to load is costly. |
| </p> |
| </dd> |
| <dt><var>number</var></dt> |
| <dd><p>Any dependence for which the latency is greater than or equal to |
| <var>number</var> is costly. |
| </p></dd> |
| </dl> |
| |
| </dd> |
| <dt><code>-minsert-sched-nops=<var>scheme</var></code></dt> |
| <dd><a name="index-minsert_002dsched_002dnops"></a> |
| <p>This option controls which NOP insertion scheme is used during |
| the second scheduling pass. The argument <var>scheme</var> takes one of the |
| following values: |
| </p> |
| <dl compact="compact"> |
| <dt>‘<samp>no</samp>’</dt> |
| <dd><p>Don’t insert NOPs. |
| </p> |
| </dd> |
| <dt>‘<samp>pad</samp>’</dt> |
| <dd><p>Pad with NOPs any dispatch group that has vacant issue slots, |
| according to the scheduler’s grouping. |
| </p> |
| </dd> |
| <dt>‘<samp>regroup_exact</samp>’</dt> |
| <dd><p>Insert NOPs to force costly dependent insns into |
| separate groups. Insert exactly as many NOPs as needed to force an insn |
| to a new group, according to the estimated processor grouping. |
| </p> |
| </dd> |
| <dt><var>number</var></dt> |
| <dd><p>Insert NOPs to force costly dependent insns into |
| separate groups. Insert <var>number</var> NOPs to force an insn to a new group. |
| </p></dd> |
| </dl> |
| |
| </dd> |
| <dt><code>-mcall-sysv</code></dt> |
| <dd><a name="index-mcall_002dsysv"></a> |
| <p>On System V.4 and embedded PowerPC systems compile code using calling |
| conventions that adhere to the March 1995 draft of the System V |
| Application Binary Interface, PowerPC processor supplement. This is the |
| default unless you configured GCC using ‘<samp>powerpc-*-eabiaix</samp>’. |
| </p> |
| </dd> |
| <dt><code>-mcall-sysv-eabi</code></dt> |
| <dt><code>-mcall-eabi</code></dt> |
| <dd><a name="index-mcall_002dsysv_002deabi"></a> |
| <a name="index-mcall_002deabi"></a> |
| <p>Specify both <samp>-mcall-sysv</samp> and <samp>-meabi</samp> options. |
| </p> |
| </dd> |
| <dt><code>-mcall-sysv-noeabi</code></dt> |
| <dd><a name="index-mcall_002dsysv_002dnoeabi"></a> |
| <p>Specify both <samp>-mcall-sysv</samp> and <samp>-mno-eabi</samp> options. |
| </p> |
| </dd> |
| <dt><code>-mcall-aixdesc</code></dt> |
| <dd><a name="index-m"></a> |
| <p>On System V.4 and embedded PowerPC systems compile code for the AIX |
| operating system. |
| </p> |
| </dd> |
| <dt><code>-mcall-linux</code></dt> |
| <dd><a name="index-mcall_002dlinux"></a> |
| <p>On System V.4 and embedded PowerPC systems compile code for the |
| Linux-based GNU system. |
| </p> |
| </dd> |
| <dt><code>-mcall-freebsd</code></dt> |
| <dd><a name="index-mcall_002dfreebsd"></a> |
| <p>On System V.4 and embedded PowerPC systems compile code for the |
| FreeBSD operating system. |
| </p> |
| </dd> |
| <dt><code>-mcall-netbsd</code></dt> |
| <dd><a name="index-mcall_002dnetbsd"></a> |
| <p>On System V.4 and embedded PowerPC systems compile code for the |
| NetBSD operating system. |
| </p> |
| </dd> |
| <dt><code>-mcall-openbsd</code></dt> |
| <dd><a name="index-mcall_002dnetbsd-1"></a> |
| <p>On System V.4 and embedded PowerPC systems compile code for the |
| OpenBSD operating system. |
| </p> |
| </dd> |
| <dt><code>-maix-struct-return</code></dt> |
| <dd><a name="index-maix_002dstruct_002dreturn"></a> |
| <p>Return all structures in memory (as specified by the AIX ABI). |
| </p> |
| </dd> |
| <dt><code>-msvr4-struct-return</code></dt> |
| <dd><a name="index-msvr4_002dstruct_002dreturn"></a> |
| <p>Return structures smaller than 8 bytes in registers (as specified by the |
| SVR4 ABI). |
| </p> |
| </dd> |
| <dt><code>-mabi=<var>abi-type</var></code></dt> |
| <dd><a name="index-mabi-2"></a> |
| <p>Extend the current ABI with a particular extension, or remove such extension. |
| Valid values are ‘<samp>altivec</samp>’, ‘<samp>no-altivec</samp>’, ‘<samp>spe</samp>’, |
| ‘<samp>no-spe</samp>’, ‘<samp>ibmlongdouble</samp>’, ‘<samp>ieeelongdouble</samp>’, |
| ‘<samp>elfv1</samp>’, ‘<samp>elfv2</samp>’. |
| </p> |
| </dd> |
| <dt><code>-mabi=spe</code></dt> |
| <dd><a name="index-mabi_003dspe"></a> |
| <p>Extend the current ABI with SPE ABI extensions. This does not change |
| the default ABI, instead it adds the SPE ABI extensions to the current |
| ABI. |
| </p> |
| </dd> |
| <dt><code>-mabi=no-spe</code></dt> |
| <dd><a name="index-mabi_003dno_002dspe"></a> |
| <p>Disable Book-E SPE ABI extensions for the current ABI. |
| </p> |
| </dd> |
| <dt><code>-mabi=ibmlongdouble</code></dt> |
| <dd><a name="index-mabi_003dibmlongdouble"></a> |
| <p>Change the current ABI to use IBM extended-precision long double. |
| This is a PowerPC 32-bit SYSV ABI option. |
| </p> |
| </dd> |
| <dt><code>-mabi=ieeelongdouble</code></dt> |
| <dd><a name="index-mabi_003dieeelongdouble"></a> |
| <p>Change the current ABI to use IEEE extended-precision long double. |
| This is a PowerPC 32-bit Linux ABI option. |
| </p> |
| </dd> |
| <dt><code>-mabi=elfv1</code></dt> |
| <dd><a name="index-mabi_003delfv1"></a> |
| <p>Change the current ABI to use the ELFv1 ABI. |
| This is the default ABI for big-endian PowerPC 64-bit Linux. |
| Overriding the default ABI requires special system support and is |
| likely to fail in spectacular ways. |
| </p> |
| </dd> |
| <dt><code>-mabi=elfv2</code></dt> |
| <dd><a name="index-mabi_003delfv2"></a> |
| <p>Change the current ABI to use the ELFv2 ABI. |
| This is the default ABI for little-endian PowerPC 64-bit Linux. |
| Overriding the default ABI requires special system support and is |
| likely to fail in spectacular ways. |
| </p> |
| </dd> |
| <dt><code>-mprototype</code></dt> |
| <dt><code>-mno-prototype</code></dt> |
| <dd><a name="index-mprototype"></a> |
| <a name="index-mno_002dprototype"></a> |
| <p>On System V.4 and embedded PowerPC systems assume that all calls to |
| variable argument functions are properly prototyped. Otherwise, the |
| compiler must insert an instruction before every non-prototyped call to |
| set or clear bit 6 of the condition code register (<code>CR</code>) to |
| indicate whether floating-point values are passed in the floating-point |
| registers in case the function takes variable arguments. With |
| <samp>-mprototype</samp>, only calls to prototyped variable argument functions |
| set or clear the bit. |
| </p> |
| </dd> |
| <dt><code>-msim</code></dt> |
| <dd><a name="index-msim-7"></a> |
| <p>On embedded PowerPC systems, assume that the startup module is called |
| <samp>sim-crt0.o</samp> and that the standard C libraries are <samp>libsim.a</samp> and |
| <samp>libc.a</samp>. This is the default for ‘<samp>powerpc-*-eabisim</samp>’ |
| configurations. |
| </p> |
| </dd> |
| <dt><code>-mmvme</code></dt> |
| <dd><a name="index-mmvme"></a> |
| <p>On embedded PowerPC systems, assume that the startup module is called |
| <samp>crt0.o</samp> and the standard C libraries are <samp>libmvme.a</samp> and |
| <samp>libc.a</samp>. |
| </p> |
| </dd> |
| <dt><code>-mads</code></dt> |
| <dd><a name="index-mads"></a> |
| <p>On embedded PowerPC systems, assume that the startup module is called |
| <samp>crt0.o</samp> and the standard C libraries are <samp>libads.a</samp> and |
| <samp>libc.a</samp>. |
| </p> |
| </dd> |
| <dt><code>-myellowknife</code></dt> |
| <dd><a name="index-myellowknife"></a> |
| <p>On embedded PowerPC systems, assume that the startup module is called |
| <samp>crt0.o</samp> and the standard C libraries are <samp>libyk.a</samp> and |
| <samp>libc.a</samp>. |
| </p> |
| </dd> |
| <dt><code>-mvxworks</code></dt> |
| <dd><a name="index-mvxworks"></a> |
| <p>On System V.4 and embedded PowerPC systems, specify that you are |
| compiling for a VxWorks system. |
| </p> |
| </dd> |
| <dt><code>-memb</code></dt> |
| <dd><a name="index-memb"></a> |
| <p>On embedded PowerPC systems, set the <code>PPC_EMB</code> bit in the ELF flags |
| header to indicate that ‘<samp>eabi</samp>’ extended relocations are used. |
| </p> |
| </dd> |
| <dt><code>-meabi</code></dt> |
| <dt><code>-mno-eabi</code></dt> |
| <dd><a name="index-meabi"></a> |
| <a name="index-mno_002deabi"></a> |
| <p>On System V.4 and embedded PowerPC systems do (do not) adhere to the |
| Embedded Applications Binary Interface (EABI), which is a set of |
| modifications to the System V.4 specifications. Selecting <samp>-meabi</samp> |
| means that the stack is aligned to an 8-byte boundary, a function |
| <code>__eabi</code> is called from <code>main</code> to set up the EABI |
| environment, and the <samp>-msdata</samp> option can use both <code>r2</code> and |
| <code>r13</code> to point to two separate small data areas. Selecting |
| <samp>-mno-eabi</samp> means that the stack is aligned to a 16-byte boundary, |
| no EABI initialization function is called from <code>main</code>, and the |
| <samp>-msdata</samp> option only uses <code>r13</code> to point to a single |
| small data area. The <samp>-meabi</samp> option is on by default if you |
| configured GCC using one of the ‘<samp>powerpc*-*-eabi*</samp>’ options. |
| </p> |
| </dd> |
| <dt><code>-msdata=eabi</code></dt> |
| <dd><a name="index-msdata_003deabi"></a> |
| <p>On System V.4 and embedded PowerPC systems, put small initialized |
| <code>const</code> global and static data in the <code>.sdata2</code> section, which |
| is pointed to by register <code>r2</code>. Put small initialized |
| non-<code>const</code> global and static data in the <code>.sdata</code> section, |
| which is pointed to by register <code>r13</code>. Put small uninitialized |
| global and static data in the <code>.sbss</code> section, which is adjacent to |
| the <code>.sdata</code> section. The <samp>-msdata=eabi</samp> option is |
| incompatible with the <samp>-mrelocatable</samp> option. The |
| <samp>-msdata=eabi</samp> option also sets the <samp>-memb</samp> option. |
| </p> |
| </dd> |
| <dt><code>-msdata=sysv</code></dt> |
| <dd><a name="index-msdata_003dsysv"></a> |
| <p>On System V.4 and embedded PowerPC systems, put small global and static |
| data in the <code>.sdata</code> section, which is pointed to by register |
| <code>r13</code>. Put small uninitialized global and static data in the |
| <code>.sbss</code> section, which is adjacent to the <code>.sdata</code> section. |
| The <samp>-msdata=sysv</samp> option is incompatible with the |
| <samp>-mrelocatable</samp> option. |
| </p> |
| </dd> |
| <dt><code>-msdata=default</code></dt> |
| <dt><code>-msdata</code></dt> |
| <dd><a name="index-msdata_003ddefault-1"></a> |
| <a name="index-msdata-1"></a> |
| <p>On System V.4 and embedded PowerPC systems, if <samp>-meabi</samp> is used, |
| compile code the same as <samp>-msdata=eabi</samp>, otherwise compile code the |
| same as <samp>-msdata=sysv</samp>. |
| </p> |
| </dd> |
| <dt><code>-msdata=data</code></dt> |
| <dd><a name="index-msdata_003ddata"></a> |
| <p>On System V.4 and embedded PowerPC systems, put small global |
| data in the <code>.sdata</code> section. Put small uninitialized global |
| data in the <code>.sbss</code> section. Do not use register <code>r13</code> |
| to address small data however. This is the default behavior unless |
| other <samp>-msdata</samp> options are used. |
| </p> |
| </dd> |
| <dt><code>-msdata=none</code></dt> |
| <dt><code>-mno-sdata</code></dt> |
| <dd><a name="index-msdata_003dnone-2"></a> |
| <a name="index-mno_002dsdata-2"></a> |
| <p>On embedded PowerPC systems, put all initialized global and static data |
| in the <code>.data</code> section, and all uninitialized data in the |
| <code>.bss</code> section. |
| </p> |
| </dd> |
| <dt><code>-mblock-move-inline-limit=<var>num</var></code></dt> |
| <dd><a name="index-mblock_002dmove_002dinline_002dlimit"></a> |
| <p>Inline all block moves (such as calls to <code>memcpy</code> or structure |
| copies) less than or equal to <var>num</var> bytes. The minimum value for |
| <var>num</var> is 32 bytes on 32-bit targets and 64 bytes on 64-bit |
| targets. The default value is target-specific. |
| </p> |
| </dd> |
| <dt><code>-G <var>num</var></code></dt> |
| <dd><a name="index-G-3"></a> |
| <a name="index-smaller-data-references-_0028PowerPC_0029"></a> |
| <a name="index-_002esdata_002f_002esdata2-references-_0028PowerPC_0029"></a> |
| <p>On embedded PowerPC systems, put global and static items less than or |
| equal to <var>num</var> bytes into the small data or BSS sections instead of |
| the normal data or BSS section. By default, <var>num</var> is 8. The |
| <samp>-G <var>num</var></samp> switch is also passed to the linker. |
| All modules should be compiled with the same <samp>-G <var>num</var></samp> value. |
| </p> |
| </dd> |
| <dt><code>-mregnames</code></dt> |
| <dt><code>-mno-regnames</code></dt> |
| <dd><a name="index-mregnames"></a> |
| <a name="index-mno_002dregnames"></a> |
| <p>On System V.4 and embedded PowerPC systems do (do not) emit register |
| names in the assembly language output using symbolic forms. |
| </p> |
| </dd> |
| <dt><code>-mlongcall</code></dt> |
| <dt><code>-mno-longcall</code></dt> |
| <dd><a name="index-mlongcall"></a> |
| <a name="index-mno_002dlongcall"></a> |
| <p>By default assume that all calls are far away so that a longer and more |
| expensive calling sequence is required. This is required for calls |
| farther than 32 megabytes (33,554,432 bytes) from the current location. |
| A short call is generated if the compiler knows |
| the call cannot be that far away. This setting can be overridden by |
| the <code>shortcall</code> function attribute, or by <code>#pragma |
| longcall(0)</code>. |
| </p> |
| <p>Some linkers are capable of detecting out-of-range calls and generating |
| glue code on the fly. On these systems, long calls are unnecessary and |
| generate slower code. As of this writing, the AIX linker can do this, |
| as can the GNU linker for PowerPC/64. It is planned to add this feature |
| to the GNU linker for 32-bit PowerPC systems as well. |
| </p> |
| <p>On Darwin/PPC systems, <code>#pragma longcall</code> generates <code>jbsr |
| callee, L42</code>, plus a <em>branch island</em> (glue code). The two target |
| addresses represent the callee and the branch island. The |
| Darwin/PPC linker prefers the first address and generates a <code>bl |
| callee</code> if the PPC <code>bl</code> instruction reaches the callee directly; |
| otherwise, the linker generates <code>bl L42</code> to call the branch |
| island. The branch island is appended to the body of the |
| calling function; it computes the full 32-bit address of the callee |
| and jumps to it. |
| </p> |
| <p>On Mach-O (Darwin) systems, this option directs the compiler emit to |
| the glue for every direct call, and the Darwin linker decides whether |
| to use or discard it. |
| </p> |
| <p>In the future, GCC may ignore all longcall specifications |
| when the linker is known to generate glue. |
| </p> |
| </dd> |
| <dt><code>-mtls-markers</code></dt> |
| <dt><code>-mno-tls-markers</code></dt> |
| <dd><a name="index-mtls_002dmarkers"></a> |
| <a name="index-mno_002dtls_002dmarkers"></a> |
| <p>Mark (do not mark) calls to <code>__tls_get_addr</code> with a relocation |
| specifying the function argument. The relocation allows the linker to |
| reliably associate function call with argument setup instructions for |
| TLS optimization, which in turn allows GCC to better schedule the |
| sequence. |
| </p> |
| </dd> |
| <dt><code>-pthread</code></dt> |
| <dd><a name="index-pthread"></a> |
| <p>Adds support for multithreading with the <em>pthreads</em> library. |
| This option sets flags for both the preprocessor and linker. |
| </p> |
| </dd> |
| <dt><code>-mrecip</code></dt> |
| <dt><code>-mno-recip</code></dt> |
| <dd><a name="index-mrecip"></a> |
| <p>This option enables use of the reciprocal estimate and |
| reciprocal square root estimate instructions with additional |
| Newton-Raphson steps to increase precision instead of doing a divide or |
| square root and divide for floating-point arguments. You should use |
| the <samp>-ffast-math</samp> option when using <samp>-mrecip</samp> (or at |
| least <samp>-funsafe-math-optimizations</samp>, |
| <samp>-finite-math-only</samp>, <samp>-freciprocal-math</samp> and |
| <samp>-fno-trapping-math</samp>). Note that while the throughput of the |
| sequence is generally higher than the throughput of the non-reciprocal |
| instruction, the precision of the sequence can be decreased by up to 2 |
| ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square |
| roots. |
| </p> |
| </dd> |
| <dt><code>-mrecip=<var>opt</var></code></dt> |
| <dd><a name="index-mrecip_003dopt"></a> |
| <p>This option controls which reciprocal estimate instructions |
| may be used. <var>opt</var> is a comma-separated list of options, which may |
| be preceded by a <code>!</code> to invert the option: |
| </p> |
| <dl compact="compact"> |
| <dt>‘<samp>all</samp>’</dt> |
| <dd><p>Enable all estimate instructions. |
| </p> |
| </dd> |
| <dt>‘<samp>default</samp>’</dt> |
| <dd><p>Enable the default instructions, equivalent to <samp>-mrecip</samp>. |
| </p> |
| </dd> |
| <dt>‘<samp>none</samp>’</dt> |
| <dd><p>Disable all estimate instructions, equivalent to <samp>-mno-recip</samp>. |
| </p> |
| </dd> |
| <dt>‘<samp>div</samp>’</dt> |
| <dd><p>Enable the reciprocal approximation instructions for both |
| single and double precision. |
| </p> |
| </dd> |
| <dt>‘<samp>divf</samp>’</dt> |
| <dd><p>Enable the single-precision reciprocal approximation instructions. |
| </p> |
| </dd> |
| <dt>‘<samp>divd</samp>’</dt> |
| <dd><p>Enable the double-precision reciprocal approximation instructions. |
| </p> |
| </dd> |
| <dt>‘<samp>rsqrt</samp>’</dt> |
| <dd><p>Enable the reciprocal square root approximation instructions for both |
| single and double precision. |
| </p> |
| </dd> |
| <dt>‘<samp>rsqrtf</samp>’</dt> |
| <dd><p>Enable the single-precision reciprocal square root approximation instructions. |
| </p> |
| </dd> |
| <dt>‘<samp>rsqrtd</samp>’</dt> |
| <dd><p>Enable the double-precision reciprocal square root approximation instructions. |
| </p> |
| </dd> |
| </dl> |
| |
| <p>So, for example, <samp>-mrecip=all,!rsqrtd</samp> enables |
| all of the reciprocal estimate instructions, except for the |
| <code>FRSQRTE</code>, <code>XSRSQRTEDP</code>, and <code>XVRSQRTEDP</code> instructions |
| which handle the double-precision reciprocal square root calculations. |
| </p> |
| </dd> |
| <dt><code>-mrecip-precision</code></dt> |
| <dt><code>-mno-recip-precision</code></dt> |
| <dd><a name="index-mrecip_002dprecision"></a> |
| <p>Assume (do not assume) that the reciprocal estimate instructions |
| provide higher-precision estimates than is mandated by the PowerPC |
| ABI. Selecting <samp>-mcpu=power6</samp>, <samp>-mcpu=power7</samp> or |
| <samp>-mcpu=power8</samp> automatically selects <samp>-mrecip-precision</samp>. |
| The double-precision square root estimate instructions are not generated by |
| default on low-precision machines, since they do not provide an |
| estimate that converges after three steps. |
| </p> |
| </dd> |
| <dt><code>-mveclibabi=<var>type</var></code></dt> |
| <dd><a name="index-mveclibabi"></a> |
| <p>Specifies the ABI type to use for vectorizing intrinsics using an |
| external library. The only type supported at present is ‘<samp>mass</samp>’, |
| which specifies to use IBM’s Mathematical Acceleration Subsystem |
| (MASS) libraries for vectorizing intrinsics using external libraries. |
| GCC currently emits calls to <code>acosd2</code>, <code>acosf4</code>, |
| <code>acoshd2</code>, <code>acoshf4</code>, <code>asind2</code>, <code>asinf4</code>, |
| <code>asinhd2</code>, <code>asinhf4</code>, <code>atan2d2</code>, <code>atan2f4</code>, |
| <code>atand2</code>, <code>atanf4</code>, <code>atanhd2</code>, <code>atanhf4</code>, |
| <code>cbrtd2</code>, <code>cbrtf4</code>, <code>cosd2</code>, <code>cosf4</code>, |
| <code>coshd2</code>, <code>coshf4</code>, <code>erfcd2</code>, <code>erfcf4</code>, |
| <code>erfd2</code>, <code>erff4</code>, <code>exp2d2</code>, <code>exp2f4</code>, |
| <code>expd2</code>, <code>expf4</code>, <code>expm1d2</code>, <code>expm1f4</code>, |
| <code>hypotd2</code>, <code>hypotf4</code>, <code>lgammad2</code>, <code>lgammaf4</code>, |
| <code>log10d2</code>, <code>log10f4</code>, <code>log1pd2</code>, <code>log1pf4</code>, |
| <code>log2d2</code>, <code>log2f4</code>, <code>logd2</code>, <code>logf4</code>, |
| <code>powd2</code>, <code>powf4</code>, <code>sind2</code>, <code>sinf4</code>, <code>sinhd2</code>, |
| <code>sinhf4</code>, <code>sqrtd2</code>, <code>sqrtf4</code>, <code>tand2</code>, |
| <code>tanf4</code>, <code>tanhd2</code>, and <code>tanhf4</code> when generating code |
| for power7. Both <samp>-ftree-vectorize</samp> and |
| <samp>-funsafe-math-optimizations</samp> must also be enabled. The MASS |
| libraries must be specified at link time. |
| </p> |
| </dd> |
| <dt><code>-mfriz</code></dt> |
| <dt><code>-mno-friz</code></dt> |
| <dd><a name="index-mfriz"></a> |
| <p>Generate (do not generate) the <code>friz</code> instruction when the |
| <samp>-funsafe-math-optimizations</samp> option is used to optimize |
| rounding of floating-point values to 64-bit integer and back to floating |
| point. The <code>friz</code> instruction does not return the same value if |
| the floating-point number is too large to fit in an integer. |
| </p> |
| </dd> |
| <dt><code>-mpointers-to-nested-functions</code></dt> |
| <dt><code>-mno-pointers-to-nested-functions</code></dt> |
| <dd><a name="index-mpointers_002dto_002dnested_002dfunctions"></a> |
| <p>Generate (do not generate) code to load up the static chain register |
| (<code>r11</code>) when calling through a pointer on AIX and 64-bit Linux |
| systems where a function pointer points to a 3-word descriptor giving |
| the function address, TOC value to be loaded in register <code>r2</code>, and |
| static chain value to be loaded in register <code>r11</code>. The |
| <samp>-mpointers-to-nested-functions</samp> is on by default. You cannot |
| call through pointers to nested functions or pointers |
| to functions compiled in other languages that use the static chain if |
| you use <samp>-mno-pointers-to-nested-functions</samp>. |
| </p> |
| </dd> |
| <dt><code>-msave-toc-indirect</code></dt> |
| <dt><code>-mno-save-toc-indirect</code></dt> |
| <dd><a name="index-msave_002dtoc_002dindirect"></a> |
| <p>Generate (do not generate) code to save the TOC value in the reserved |
| stack location in the function prologue if the function calls through |
| a pointer on AIX and 64-bit Linux systems. If the TOC value is not |
| saved in the prologue, it is saved just before the call through the |
| pointer. The <samp>-mno-save-toc-indirect</samp> option is the default. |
| </p> |
| </dd> |
| <dt><code>-mcompat-align-parm</code></dt> |
| <dt><code>-mno-compat-align-parm</code></dt> |
| <dd><a name="index-mcompat_002dalign_002dparm"></a> |
| <p>Generate (do not generate) code to pass structure parameters with a |
| maximum alignment of 64 bits, for compatibility with older versions |
| of GCC. |
| </p> |
| <p>Older versions of GCC (prior to 4.9.0) incorrectly did not align a |
| structure parameter on a 128-bit boundary when that structure contained |
| a member requiring 128-bit alignment. This is corrected in more |
| recent versions of GCC. This option may be used to generate code |
| that is compatible with functions compiled with older versions of |
| GCC. |
| </p> |
| <p>The <samp>-mno-compat-align-parm</samp> option is the default. |
| </p></dd> |
| </dl> |
| |
| <hr> |
| <div class="header"> |
| <p> |
| Next: <a href="RX-Options.html#RX-Options" accesskey="n" rel="next">RX Options</a>, Previous: <a href="RL78-Options.html#RL78-Options" accesskey="p" rel="prev">RL78 Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p> |
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