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This is as.info, produced by makeinfo version 5.2 from as.texinfo.
This file documents the GNU Assembler "as".
Copyright (C) 1991-2014 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3 or
any later version published by the Free Software Foundation; with no
Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
Texts. A copy of the license is included in the section entitled "GNU
Free Documentation License".
INFO-DIR-SECTION Software development
START-INFO-DIR-ENTRY
* As: (as). The GNU assembler.
* Gas: (as). The GNU assembler.
END-INFO-DIR-ENTRY

File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent
9.6.3 Directives
----------------
The following directives are provided for compatibility with the VDSP
assembler.
'.byte2'
Initializes a two byte data object.
This maps to the '.short' directive.
'.byte4'
Initializes a four byte data object.
This maps to the '.int' directive.
'.db'
Initializes a single byte data object.
This directive is a synonym for '.byte'.
'.dw'
Initializes a two byte data object.
This directive is a synonym for '.byte2'.
'.dd'
Initializes a four byte data object.
This directive is a synonym for '.byte4'.
'.var'
Define and initialize a 32 bit data object.

File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies
9.7 CR16 Dependent Features
===========================
* Menu:
* CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers
* CR16 Syntax:: Syntax for the CR16

File: as.info, Node: CR16 Operand Qualifiers, Next: CR16 Syntax, Up: CR16-Dependent
9.7.1 CR16 Operand Qualifiers
-----------------------------
The National Semiconductor CR16 target of 'as' has a few machine
dependent operand qualifiers.
Operand expression type qualifier is an optional field in the
instruction operand, to determines the type of the expression field of
an operand. The '@' is required. CR16 architecture uses one of the
following expression qualifiers:
's'
- 'Specifies expression operand type as small'
'm'
- 'Specifies expression operand type as medium'
'l'
- 'Specifies expression operand type as large'
'c'
- 'Specifies the CR16 Assembler generates a relocation entry for
the operand, where pc has implied bit, the expression is adjusted
accordingly. The linker uses the relocation entry to update the
operand address at link time.'
'got/GOT'
- 'Specifies the CR16 Assembler generates a relocation entry for
the operand, offset from Global Offset Table. The linker uses this
relocation entry to update the operand address at link time'
'cgot/cGOT'
- 'Specifies the CompactRISC Assembler generates a relocation entry
for the operand, where pc has implied bit, the expression is
adjusted accordingly. The linker uses the relocation entry to
update the operand address at link time.'
CR16 target operand qualifiers and its size (in bits):
'Immediate Operand: s'
4 bits.
'Immediate Operand: m'
16 bits, for movb and movw instructions.
'Immediate Operand: m'
20 bits, movd instructions.
'Immediate Operand: l'
32 bits.
'Absolute Operand: s'
Illegal specifier for this operand.
'Absolute Operand: m'
20 bits, movd instructions.
'Displacement Operand: s'
8 bits.
'Displacement Operand: m'
16 bits.
'Displacement Operand: l'
24 bits.
For example:
1 movw $_myfun@c,r1
This loads the address of _myfun, shifted right by 1, into r1.
2 movd $_myfun@c,(r2,r1)
This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
3 _myfun_ptr:
.long _myfun@c
loadd _myfun_ptr, (r1,r0)
jal (r1,r0)
This .long directive, the address of _myfunc, shifted right by 1 at link time.
4 loadd _data1@GOT(r12), (r1,r0)
This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1.
5 loadd _myfunc@cGOT(r12), (r1,r0)
This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.

File: as.info, Node: CR16 Syntax, Prev: CR16 Operand Qualifiers, Up: CR16-Dependent
9.7.2 CR16 Syntax
-----------------
* Menu:
* CR16-Chars:: Special Characters

File: as.info, Node: CR16-Chars, Up: CR16 Syntax
9.7.2.1 Special Characters
..........................
The presence of a '#' on a line indicates the start of a comment that
extends to the end of the current line. If the '#' appears as the first
character of a line, the whole line is treated as a comment, but in this
case the line can also be a logical line number directive (*note
Comments::) or a preprocessor control command (*note Preprocessing::).
The ';' character can be used to separate statements on the same
line.

File: as.info, Node: CRIS-Dependent, Next: D10V-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies
9.8 CRIS Dependent Features
===========================
* Menu:
* CRIS-Opts:: Command-line Options
* CRIS-Expand:: Instruction expansion
* CRIS-Symbols:: Symbols
* CRIS-Syntax:: Syntax

File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent
9.8.1 Command-line Options
--------------------------
The CRIS version of 'as' has these machine-dependent command-line
options.
The format of the generated object files can be either ELF or a.out,
specified by the command-line options '--emulation=crisaout' and
'--emulation=criself'. The default is ELF (criself), unless 'as' has
been configured specifically for a.out by using the configuration name
'cris-axis-aout'.
There are two different link-incompatible ELF object file variants
for CRIS, for use in environments where symbols are expected to be
prefixed by a leading '_' character and for environments without such a
symbol prefix. The variant used for GNU/Linux port has no symbol
prefix. Which variant to produce is specified by either of the options
'--underscore' and '--no-underscore'. The default is '--underscore'.
Since symbols in CRIS a.out objects are expected to have a '_' prefix,
specifying '--no-underscore' when generating a.out objects is an error.
Besides the object format difference, the effect of this option is to
parse register names differently (*note crisnous::). The
'--no-underscore' option makes a '$' register prefix mandatory.
The option '--pic' must be passed to 'as' in order to recognize the
symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note
crispic::). This will also affect expansion of instructions. The
expansion with '--pic' will use PC-relative rather than (slightly
faster) absolute addresses in those expansions. This option is only
valid when generating ELF format object files.
The option '--march=ARCHITECTURE' specifies the recognized
instruction set and recognized register names. It also controls the
architecture type of the object file. Valid values for ARCHITECTURE
are:
'v0_v10'
All instructions and register names for any architecture variant in
the set v0...v10 are recognized. This is the default if the target
is configured as cris-*.
'v10'
Only instructions and register names for CRIS v10 (as found in
ETRAX 100 LX) are recognized. This is the default if the target is
configured as crisv10-*.
'v32'
Only instructions and register names for CRIS v32 (code name
Guinness) are recognized. This is the default if the target is
configured as crisv32-*. This value implies '--no-mul-bug-abort'.
(A subsequent '--mul-bug-abort' will turn it back on.)
'common_v10_v32'
Only instructions with register names and addressing modes with
opcodes common to the v10 and v32 are recognized.
When '-N' is specified, 'as' will emit a warning when a 16-bit branch
instruction is expanded into a 32-bit multiple-instruction construct
(*note CRIS-Expand::).
Some versions of the CRIS v10, for example in the Etrax 100 LX,
contain a bug that causes destabilizing memory accesses when a multiply
instruction is executed with certain values in the first operand just
before a cache-miss. When the '--mul-bug-abort' command line option is
active (the default value), 'as' will refuse to assemble a file
containing a multiply instruction at a dangerous offset, one that could
be the last on a cache-line, or is in a section with insufficient
alignment. This placement checking does not catch any case where the
multiply instruction is dangerously placed because it is located in a
delay-slot. The '--mul-bug-abort' command line option turns off the
checking.

File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent
9.8.2 Instruction expansion
---------------------------
'as' will silently choose an instruction that fits the operand size for
'[register+constant]' operands. For example, the offset '127' in
'move.d [r3+127],r4' fits in an instruction using a signed-byte offset.
Similarly, 'move.d [r2+32767],r1' will generate an instruction using a
16-bit offset. For symbolic expressions and constants that do not fit
in 16 bits including the sign bit, a 32-bit offset is generated.
For branches, 'as' will expand from a 16-bit branch instruction into
a sequence of instructions that can reach a full 32-bit address. Since
this does not correspond to a single instruction, such expansions can
optionally be warned about. *Note CRIS-Opts::.
If the operand is found to fit the range, a 'lapc' mnemonic will
translate to a 'lapcq' instruction. Use 'lapc.d' to force the 32-bit
'lapc' instruction.
Similarly, the 'addo' mnemonic will translate to the shortest fitting
instruction of 'addoq', 'addo.w' and 'addo.d', when used with a operand
that is a constant known at assembly time.

File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent
9.8.3 Symbols
-------------
Some symbols are defined by the assembler. They're intended to be used
in conditional assembly, for example:
.if ..asm.arch.cris.v32
CODE FOR CRIS V32
.elseif ..asm.arch.cris.common_v10_v32
CODE COMMON TO CRIS V32 AND CRIS V10
.elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
CODE FOR V10
.else
.error "Code needs to be added here."
.endif
These symbols are defined in the assembler, reflecting command-line
options, either when specified or the default. They are always defined,
to 0 or 1.
'..asm.arch.cris.any_v0_v10'
This symbol is non-zero when '--march=v0_v10' is specified or the
default.
'..asm.arch.cris.common_v10_v32'
Set according to the option '--march=common_v10_v32'.
'..asm.arch.cris.v10'
Reflects the option '--march=v10'.
'..asm.arch.cris.v32'
Corresponds to '--march=v10'.
Speaking of symbols, when a symbol is used in code, it can have a
suffix modifying its value for use in position-independent code. *Note
CRIS-Pic::.

File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent
9.8.4 Syntax
------------
There are different aspects of the CRIS assembly syntax.
* Menu:
* CRIS-Chars:: Special Characters
* CRIS-Pic:: Position-Independent Code Symbols
* CRIS-Regs:: Register Names
* CRIS-Pseudos:: Assembler Directives

File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax
9.8.4.1 Special Characters
..........................
The character '#' is a line comment character. It starts a comment if
and only if it is placed at the beginning of a line.
A ';' character starts a comment anywhere on the line, causing all
characters up to the end of the line to be ignored.
A '@' character is handled as a line separator equivalent to a
logical new-line character (except in a comment), so separate
instructions can be specified on a single line.

File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax
9.8.4.2 Symbols in position-independent code
............................................
When generating position-independent code (SVR4 PIC) for use in
cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol
suffixes are used to specify what kind of run-time symbol lookup will be
used, expressed in the object as different _relocation types_. Usually,
all absolute symbol values must be located in a table, the _global
offset table_, leaving the code position-independent; independent of
values of global symbols and independent of the address of the code.
The suffix modifies the value of the symbol, into for example an index
into the global offset table where the real symbol value is entered, or
a PC-relative value, or a value relative to the start of the global
offset table. All symbol suffixes start with the character ':' (omitted
in the list below). Every symbol use in code or a read-only section
must therefore have a PIC suffix to enable a useful shared library to be
created. Usually, these constructs must not be used with an additive
constant offset as is usually allowed, i.e. no 4 as in 'symbol + 4' is
allowed. This restriction is checked at link-time, not at
assembly-time.
'GOT'
Attaching this suffix to a symbol in an instruction causes the
symbol to be entered into the global offset table. The value is a
32-bit index for that symbol into the global offset table. The
name of the corresponding relocation is 'R_CRIS_32_GOT'. Example:
'move.d [$r0+extsym:GOT],$r9'
'GOT16'
Same as for 'GOT', but the value is a 16-bit index into the global
offset table. The corresponding relocation is 'R_CRIS_16_GOT'.
Example: 'move.d [$r0+asymbol:GOT16],$r10'
'PLT'
This suffix is used for function symbols. It causes a _procedure
linkage table_, an array of code stubs, to be created at the time
the shared object is created or linked against, together with a
global offset table entry. The value is a pc-relative offset to
the corresponding stub code in the procedure linkage table. This
arrangement causes the run-time symbol resolver to be called to
look up and set the value of the symbol the first time the function
is called (at latest; depending environment variables). It is only
safe to leave the symbol unresolved this way if all references are
function calls. The name of the relocation is
'R_CRIS_32_PLT_PCREL'. Example: 'add.d fnname:PLT,$pc'
'PLTG'
Like PLT, but the value is relative to the beginning of the global
offset table. The relocation is 'R_CRIS_32_PLT_GOTREL'. Example:
'move.d fnname:PLTG,$r3'
'GOTPLT'
Similar to 'PLT', but the value of the symbol is a 32-bit index
into the global offset table. This is somewhat of a mix between
the effect of the 'GOT' and the 'PLT' suffix; the difference to
'GOT' is that there will be a procedure linkage table entry
created, and that the symbol is assumed to be a function entry and
will be resolved by the run-time resolver as with 'PLT'. The
relocation is 'R_CRIS_32_GOTPLT'. Example: 'jsr
[$r0+fnname:GOTPLT]'
'GOTPLT16'
A variant of 'GOTPLT' giving a 16-bit value. Its relocation name
is 'R_CRIS_16_GOTPLT'. Example: 'jsr [$r0+fnname:GOTPLT16]'
'GOTOFF'
This suffix must only be attached to a local symbol, but may be
used in an expression adding an offset. The value is the address
of the symbol relative to the start of the global offset table.
The relocation name is 'R_CRIS_32_GOTREL'. Example: 'move.d
[$r0+localsym:GOTOFF],r3'

File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax
9.8.4.3 Register names
......................
A '$' character may always prefix a general or special register name in
an instruction operand but is mandatory when the option
'--no-underscore' is specified or when the '.syntax register_prefix'
directive is in effect (*note crisnous::). Register names are
case-insensitive.

File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax
9.8.4.4 Assembler Directives
............................
There are a few CRIS-specific pseudo-directives in addition to the
generic ones. *Note Pseudo Ops::. Constants emitted by
pseudo-directives are in little-endian order for CRIS. There is no
support for floating-point-specific directives for CRIS.
'.dword EXPRESSIONS'
The '.dword' directive is a synonym for '.int', expecting zero or
more EXPRESSIONS, separated by commas. For each expression, a
32-bit little-endian constant is emitted.
'.syntax ARGUMENT'
The '.syntax' directive takes as ARGUMENT one of the following
case-sensitive choices.
'no_register_prefix'
The '.syntax no_register_prefix' directive makes a '$'
character prefix on all registers optional. It overrides a
previous setting, including the corresponding effect of the
option '--no-underscore'. If this directive is used when
ordinary symbols do not have a '_' character prefix, care must
be taken to avoid ambiguities whether an operand is a register
or a symbol; using symbols with names the same as general or
special registers then invoke undefined behavior.
'register_prefix'
This directive makes a '$' character prefix on all registers
mandatory. It overrides a previous setting, including the
corresponding effect of the option '--underscore'.
'leading_underscore'
This is an assertion directive, emitting an error if the
'--no-underscore' option is in effect.
'no_leading_underscore'
This is the opposite of the '.syntax leading_underscore'
directive and emits an error if the option '--underscore' is
in effect.
'.arch ARGUMENT'
This is an assertion directive, giving an error if the specified
ARGUMENT is not the same as the specified or default value for the
'--march=ARCHITECTURE' option (*note march-option::).

File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies
9.9 D10V Dependent Features
===========================
* Menu:
* D10V-Opts:: D10V Options
* D10V-Syntax:: Syntax
* D10V-Float:: Floating Point
* D10V-Opcodes:: Opcodes

File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent
9.9.1 D10V Options
------------------
The Mitsubishi D10V version of 'as' has a few machine dependent options.
'-O'
The D10V can often execute two sub-instructions in parallel. When
this option is used, 'as' will attempt to optimize its output by
detecting when instructions can be executed in parallel.
'--nowarnswap'
To optimize execution performance, 'as' will sometimes swap the
order of instructions. Normally this generates a warning. When
this option is used, no warning will be generated when instructions
are swapped.
'--gstabs-packing'
'--no-gstabs-packing'
'as' packs adjacent short instructions into a single packed
instruction. '--no-gstabs-packing' turns instruction packing off
if '--gstabs' is specified as well; '--gstabs-packing' (the
default) turns instruction packing on even when '--gstabs' is
specified.

File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent
9.9.2 Syntax
------------
The D10V syntax is based on the syntax in Mitsubishi's D10V architecture
manual. The differences are detailed below.
* Menu:
* D10V-Size:: Size Modifiers
* D10V-Subs:: Sub-Instructions
* D10V-Chars:: Special Characters
* D10V-Regs:: Register Names
* D10V-Addressing:: Addressing Modes
* D10V-Word:: @WORD Modifier

File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax
9.9.2.1 Size Modifiers
......................
The D10V version of 'as' uses the instruction names in the D10V
Architecture Manual. However, the names in the manual are sometimes
ambiguous. There are instruction names that can assemble to a short or
long form opcode. How does the assembler pick the correct form? 'as'
will always pick the smallest form if it can. When dealing with a
symbol that is not defined yet when a line is being assembled, it will
always use the long form. If you need to force the assembler to use
either the short or long form of the instruction, you can append either
'.s' (short) or '.l' (long) to it. For example, if you are writing an
assembly program and you want to do a branch to a symbol that is defined
later in your program, you can write 'bra.s foo'. Objdump and GDB will
always append '.s' or '.l' to instructions which have both short and
long forms.

File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax
9.9.2.2 Sub-Instructions
........................
The D10V assembler takes as input a series of instructions, either
one-per-line, or in the special two-per-line format described in the
next section. Some of these instructions will be short-form or
sub-instructions. These sub-instructions can be packed into a single
instruction. The assembler will do this automatically. It will also
detect when it should not pack instructions. For example, when a label
is defined, the next instruction will never be packaged with the
previous one. Whenever a branch and link instruction is called, it will
not be packaged with the next instruction so the return address will be
valid. Nops are automatically inserted when necessary.
If you do not want the assembler automatically making these
decisions, you can control the packaging and execution type (parallel or
sequential) with the special execution symbols described in the next
section.

File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax
9.9.2.3 Special Characters
..........................
A semicolon (';') can be used anywhere on a line to start a comment that
extends to the end of the line.
If a '#' appears as the first character of a line, the whole line is
treated as a comment, but in this case the line could also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
Sub-instructions may be executed in order, in reverse-order, or in
parallel. Instructions listed in the standard one-per-line format will
be executed sequentially. To specify the executing order, use the
following symbols:
'->'
Sequential with instruction on the left first.
'<-'
Sequential with instruction on the right first.
'||'
Parallel
The D10V syntax allows either one instruction per line, one
instruction per line with the execution symbol, or two instructions per
line. For example
'abs a1 -> abs r0'
Execute these sequentially. The instruction on the right is in the
right container and is executed second.
'abs r0 <- abs a1'
Execute these reverse-sequentially. The instruction on the right
is in the right container, and is executed first.
'ld2w r2,@r8+ || mac a0,r0,r7'
Execute these in parallel.
'ld2w r2,@r8+ ||'
'mac a0,r0,r7'
Two-line format. Execute these in parallel.
'ld2w r2,@r8+'
'mac a0,r0,r7'
Two-line format. Execute these sequentially. Assembler will put
them in the proper containers.
'ld2w r2,@r8+ ->'
'mac a0,r0,r7'
Two-line format. Execute these sequentially. Same as above but
second instruction will always go into right container.
Since '$' has no special meaning, you may use it in symbol names.

File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax
9.9.2.4 Register Names
......................
You can use the predefined symbols 'r0' through 'r15' to refer to the
D10V registers. You can also use 'sp' as an alias for 'r15'. The
accumulators are 'a0' and 'a1'. There are special register-pair names
that may optionally be used in opcodes that require even-numbered
registers. Register names are not case sensitive.
Register Pairs
'r0-r1'
'r2-r3'
'r4-r5'
'r6-r7'
'r8-r9'
'r10-r11'
'r12-r13'
'r14-r15'
The D10V also has predefined symbols for these control registers and
status bits:
'psw'
Processor Status Word
'bpsw'
Backup Processor Status Word
'pc'
Program Counter
'bpc'
Backup Program Counter
'rpt_c'
Repeat Count
'rpt_s'
Repeat Start address
'rpt_e'
Repeat End address
'mod_s'
Modulo Start address
'mod_e'
Modulo End address
'iba'
Instruction Break Address
'f0'
Flag 0
'f1'
Flag 1
'c'
Carry flag

File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax
9.9.2.5 Addressing Modes
........................
'as' understands the following addressing modes for the D10V. 'RN' in
the following refers to any of the numbered registers, but _not_ the
control registers.
'RN'
Register direct
'@RN'
Register indirect
'@RN+'
Register indirect with post-increment
'@RN-'
Register indirect with post-decrement
'@-SP'
Register indirect with pre-decrement
'@(DISP, RN)'
Register indirect with displacement
'ADDR'
PC relative address (for branch or rep).
'#IMM'
Immediate data (the '#' is optional and ignored)

File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax
9.9.2.6 @WORD Modifier
......................
Any symbol followed by '@word' will be replaced by the symbol's value
shifted right by 2. This is used in situations such as loading a
register with the address of a function (or any other code fragment).
For example, if you want to load a register with the location of the
function 'main' then jump to that function, you could do it as follows:
ldi r2, main@word
jmp r2

File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent
9.9.3 Floating Point
--------------------
The D10V has no hardware floating point, but the '.float' and '.double'
directives generates IEEE floating-point numbers for compatibility with
other development tools.

File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent
9.9.4 Opcodes
-------------
For detailed information on the D10V machine instruction set, see 'D10V
Architecture: A VLIW Microprocessor for Multimedia Applications'
(Mitsubishi Electric Corp.). 'as' implements all the standard D10V
opcodes. The only changes are those described in the section on size
modifiers

File: as.info, Node: D30V-Dependent, Next: Epiphany-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies
9.10 D30V Dependent Features
============================
* Menu:
* D30V-Opts:: D30V Options
* D30V-Syntax:: Syntax
* D30V-Float:: Floating Point
* D30V-Opcodes:: Opcodes

File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent
9.10.1 D30V Options
-------------------
The Mitsubishi D30V version of 'as' has a few machine dependent options.
'-O'
The D30V can often execute two sub-instructions in parallel. When
this option is used, 'as' will attempt to optimize its output by
detecting when instructions can be executed in parallel.
'-n'
When this option is used, 'as' will issue a warning every time it
adds a nop instruction.
'-N'
When this option is used, 'as' will issue a warning if it needs to
insert a nop after a 32-bit multiply before a load or 16-bit
multiply instruction.

File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent
9.10.2 Syntax
-------------
The D30V syntax is based on the syntax in Mitsubishi's D30V architecture
manual. The differences are detailed below.
* Menu:
* D30V-Size:: Size Modifiers
* D30V-Subs:: Sub-Instructions
* D30V-Chars:: Special Characters
* D30V-Guarded:: Guarded Execution
* D30V-Regs:: Register Names
* D30V-Addressing:: Addressing Modes

File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax
9.10.2.1 Size Modifiers
.......................
The D30V version of 'as' uses the instruction names in the D30V
Architecture Manual. However, the names in the manual are sometimes
ambiguous. There are instruction names that can assemble to a short or
long form opcode. How does the assembler pick the correct form? 'as'
will always pick the smallest form if it can. When dealing with a
symbol that is not defined yet when a line is being assembled, it will
always use the long form. If you need to force the assembler to use
either the short or long form of the instruction, you can append either
'.s' (short) or '.l' (long) to it. For example, if you are writing an
assembly program and you want to do a branch to a symbol that is defined
later in your program, you can write 'bra.s foo'. Objdump and GDB will
always append '.s' or '.l' to instructions which have both short and
long forms.

File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax
9.10.2.2 Sub-Instructions
.........................
The D30V assembler takes as input a series of instructions, either
one-per-line, or in the special two-per-line format described in the
next section. Some of these instructions will be short-form or
sub-instructions. These sub-instructions can be packed into a single
instruction. The assembler will do this automatically. It will also
detect when it should not pack instructions. For example, when a label
is defined, the next instruction will never be packaged with the
previous one. Whenever a branch and link instruction is called, it will
not be packaged with the next instruction so the return address will be
valid. Nops are automatically inserted when necessary.
If you do not want the assembler automatically making these
decisions, you can control the packaging and execution type (parallel or
sequential) with the special execution symbols described in the next
section.

File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax
9.10.2.3 Special Characters
...........................
A semicolon (';') can be used anywhere on a line to start a comment that
extends to the end of the line.
If a '#' appears as the first character of a line, the whole line is
treated as a comment, but in this case the line could also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
Sub-instructions may be executed in order, in reverse-order, or in
parallel. Instructions listed in the standard one-per-line format will
be executed sequentially unless you use the '-O' option.
To specify the executing order, use the following symbols:
'->'
Sequential with instruction on the left first.
'<-'
Sequential with instruction on the right first.
'||'
Parallel
The D30V syntax allows either one instruction per line, one
instruction per line with the execution symbol, or two instructions per
line. For example
'abs r2,r3 -> abs r4,r5'
Execute these sequentially. The instruction on the right is in the
right container and is executed second.
'abs r2,r3 <- abs r4,r5'
Execute these reverse-sequentially. The instruction on the right
is in the right container, and is executed first.
'abs r2,r3 || abs r4,r5'
Execute these in parallel.
'ldw r2,@(r3,r4) ||'
'mulx r6,r8,r9'
Two-line format. Execute these in parallel.
'mulx a0,r8,r9'
'stw r2,@(r3,r4)'
Two-line format. Execute these sequentially unless '-O' option is
used. If the '-O' option is used, the assembler will determine if
the instructions could be done in parallel (the above two
instructions can be done in parallel), and if so, emit them as
parallel instructions. The assembler will put them in the proper
containers. In the above example, the assembler will put the 'stw'
instruction in left container and the 'mulx' instruction in the
right container.
'stw r2,@(r3,r4) ->'
'mulx a0,r8,r9'
Two-line format. Execute the 'stw' instruction followed by the
'mulx' instruction sequentially. The first instruction goes in the
left container and the second instruction goes into right
container. The assembler will give an error if the machine
ordering constraints are violated.
'stw r2,@(r3,r4) <-'
'mulx a0,r8,r9'
Same as previous example, except that the 'mulx' instruction is
executed before the 'stw' instruction.
Since '$' has no special meaning, you may use it in symbol names.

File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax
9.10.2.4 Guarded Execution
..........................
'as' supports the full range of guarded execution directives for each
instruction. Just append the directive after the instruction proper.
The directives are:
'/tx'
Execute the instruction if flag f0 is true.
'/fx'
Execute the instruction if flag f0 is false.
'/xt'
Execute the instruction if flag f1 is true.
'/xf'
Execute the instruction if flag f1 is false.
'/tt'
Execute the instruction if both flags f0 and f1 are true.
'/tf'
Execute the instruction if flag f0 is true and flag f1 is false.

File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax
9.10.2.5 Register Names
.......................
You can use the predefined symbols 'r0' through 'r63' to refer to the
D30V registers. You can also use 'sp' as an alias for 'r63' and 'link'
as an alias for 'r62'. The accumulators are 'a0' and 'a1'.
The D30V also has predefined symbols for these control registers and
status bits:
'psw'
Processor Status Word
'bpsw'
Backup Processor Status Word
'pc'
Program Counter
'bpc'
Backup Program Counter
'rpt_c'
Repeat Count
'rpt_s'
Repeat Start address
'rpt_e'
Repeat End address
'mod_s'
Modulo Start address
'mod_e'
Modulo End address
'iba'
Instruction Break Address
'f0'
Flag 0
'f1'
Flag 1
'f2'
Flag 2
'f3'
Flag 3
'f4'
Flag 4
'f5'
Flag 5
'f6'
Flag 6
'f7'
Flag 7
's'
Same as flag 4 (saturation flag)
'v'
Same as flag 5 (overflow flag)
'va'
Same as flag 6 (sticky overflow flag)
'c'
Same as flag 7 (carry/borrow flag)
'b'
Same as flag 7 (carry/borrow flag)

File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax
9.10.2.6 Addressing Modes
.........................
'as' understands the following addressing modes for the D30V. 'RN' in
the following refers to any of the numbered registers, but _not_ the
control registers.
'RN'
Register direct
'@RN'
Register indirect
'@RN+'
Register indirect with post-increment
'@RN-'
Register indirect with post-decrement
'@-SP'
Register indirect with pre-decrement
'@(DISP, RN)'
Register indirect with displacement
'ADDR'
PC relative address (for branch or rep).
'#IMM'
Immediate data (the '#' is optional and ignored)

File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent
9.10.3 Floating Point
---------------------
The D30V has no hardware floating point, but the '.float' and '.double'
directives generates IEEE floating-point numbers for compatibility with
other development tools.

File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent
9.10.4 Opcodes
--------------
For detailed information on the D30V machine instruction set, see 'D30V
Architecture: A VLIW Microprocessor for Multimedia Applications'
(Mitsubishi Electric Corp.). 'as' implements all the standard D30V
opcodes. The only changes are those described in the section on size
modifiers

File: as.info, Node: Epiphany-Dependent, Next: H8/300-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies
9.11 Epiphany Dependent Features
================================
* Menu:
* Epiphany Options:: Options
* Epiphany Syntax:: Epiphany Syntax

File: as.info, Node: Epiphany Options, Next: Epiphany Syntax, Up: Epiphany-Dependent
9.11.1 Options
--------------
'as' has two additional command-line options for the Epiphany
architecture.
'-mepiphany'
Specifies that the both 32 and 16 bit instructions are allowed.
This is the default behavior.
'-mepiphany16'
Restricts the permitted instructions to just the 16 bit set.

File: as.info, Node: Epiphany Syntax, Prev: Epiphany Options, Up: Epiphany-Dependent
9.11.2 Epiphany Syntax
----------------------
* Menu:
* Epiphany-Chars:: Special Characters

File: as.info, Node: Epiphany-Chars, Up: Epiphany Syntax
9.11.2.1 Special Characters
...........................
The presence of a ';' on a line indicates the start of a comment that
extends to the end of the current line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line could also be a
logical line number directive (*note Comments::) or a preprocessor
control command (*note Preprocessing::).
The '`' character can be used to separate statements on the same
line.

File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: Epiphany-Dependent, Up: Machine Dependencies
9.12 H8/300 Dependent Features
==============================
* Menu:
* H8/300 Options:: Options
* H8/300 Syntax:: Syntax
* H8/300 Floating Point:: Floating Point
* H8/300 Directives:: H8/300 Machine Directives
* H8/300 Opcodes:: Opcodes

File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent
9.12.1 Options
--------------
The Renesas H8/300 version of 'as' has one machine-dependent option:
'-h-tick-hex'
Support H'00 style hex constants in addition to 0x00 style.

File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent
9.12.2 Syntax
-------------
* Menu:
* H8/300-Chars:: Special Characters
* H8/300-Regs:: Register Names
* H8/300-Addressing:: Addressing Modes

File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax
9.12.2.1 Special Characters
...........................
';' is the line comment character.
'$' can be used instead of a newline to separate statements.
Therefore _you may not use '$' in symbol names_ on the H8/300.

File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax
9.12.2.2 Register Names
.......................
You can use predefined symbols of the form 'rNh' and 'rNl' to refer to
the H8/300 registers as sixteen 8-bit general-purpose registers. N is a
digit from '0' to '7'); for instance, both 'r0h' and 'r7l' are valid
register names.
You can also use the eight predefined symbols 'rN' to refer to the
H8/300 registers as 16-bit registers (you must use this form for
addressing).
On the H8/300H, you can also use the eight predefined symbols 'erN'
('er0' ... 'er7') to refer to the 32-bit general purpose registers.
The two control registers are called 'pc' (program counter; a 16-bit
register, except on the H8/300H where it is 24 bits) and 'ccr'
(condition code register; an 8-bit register). 'r7' is used as the stack
pointer, and can also be called 'sp'.

File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax
9.12.2.3 Addressing Modes
.........................
as understands the following addressing modes for the H8/300:
'rN'
Register direct
'@rN'
Register indirect
'@(D, rN)'
'@(D:16, rN)'
'@(D:24, rN)'
Register indirect: 16-bit or 24-bit displacement D from register N.
(24-bit displacements are only meaningful on the H8/300H.)
'@rN+'
Register indirect with post-increment
'@-rN'
Register indirect with pre-decrement
'@AA'
'@AA:8'
'@AA:16'
'@AA:24'
Absolute address 'aa'. (The address size ':24' only makes sense on
the H8/300H.)
'#XX'
'#XX:8'
'#XX:16'
'#XX:32'
Immediate data XX. You may specify the ':8', ':16', or ':32' for
clarity, if you wish; but 'as' neither requires this nor uses
it--the data size required is taken from context.
'@@AA'
'@@AA:8'
Memory indirect. You may specify the ':8' for clarity, if you
wish; but 'as' neither requires this nor uses it.

File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent
9.12.3 Floating Point
---------------------
The H8/300 family has no hardware floating point, but the '.float'
directive generates IEEE floating-point numbers for compatibility with
other development tools.

File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent
9.12.4 H8/300 Machine Directives
--------------------------------
'as' has the following machine-dependent directives for the H8/300:
'.h8300h'
Recognize and emit additional instructions for the H8/300H variant,
and also make '.int' emit 32-bit numbers rather than the usual
(16-bit) for the H8/300 family.
'.h8300s'
Recognize and emit additional instructions for the H8S variant, and
also make '.int' emit 32-bit numbers rather than the usual (16-bit)
for the H8/300 family.
'.h8300hn'
Recognize and emit additional instructions for the H8/300H variant
in normal mode, and also make '.int' emit 32-bit numbers rather
than the usual (16-bit) for the H8/300 family.
'.h8300sn'
Recognize and emit additional instructions for the H8S variant in
normal mode, and also make '.int' emit 32-bit numbers rather than
the usual (16-bit) for the H8/300 family.
On the H8/300 family (including the H8/300H) '.word' directives
generate 16-bit numbers.

File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent
9.12.5 Opcodes
--------------
For detailed information on the H8/300 machine instruction set, see
'H8/300 Series Programming Manual'. For information specific to the
H8/300H, see 'H8/300H Series Programming Manual' (Renesas).
'as' implements all the standard H8/300 opcodes. No additional
pseudo-instructions are needed on this family.
The following table summarizes the H8/300 opcodes, and their
arguments. Entries marked '*' are opcodes used only on the H8/300H.
Legend:
Rs source register
Rd destination register
abs absolute address
imm immediate data
disp:N N-bit displacement from a register
pcrel:N N-bit displacement relative to program counter
add.b #imm,rd * andc #imm,ccr
add.b rs,rd band #imm,rd
add.w rs,rd band #imm,@rd
* add.w #imm,rd band #imm,@abs:8
* add.l rs,rd bra pcrel:8
* add.l #imm,rd * bra pcrel:16
adds #imm,rd bt pcrel:8
addx #imm,rd * bt pcrel:16
addx rs,rd brn pcrel:8
and.b #imm,rd * brn pcrel:16
and.b rs,rd bf pcrel:8
* and.w rs,rd * bf pcrel:16
* and.w #imm,rd bhi pcrel:8
* and.l #imm,rd * bhi pcrel:16
* and.l rs,rd bls pcrel:8
* bls pcrel:16 bld #imm,rd
bcc pcrel:8 bld #imm,@rd
* bcc pcrel:16 bld #imm,@abs:8
bhs pcrel:8 bnot #imm,rd
* bhs pcrel:16 bnot #imm,@rd
bcs pcrel:8 bnot #imm,@abs:8
* bcs pcrel:16 bnot rs,rd
blo pcrel:8 bnot rs,@rd
* blo pcrel:16 bnot rs,@abs:8
bne pcrel:8 bor #imm,rd
* bne pcrel:16 bor #imm,@rd
beq pcrel:8 bor #imm,@abs:8
* beq pcrel:16 bset #imm,rd
bvc pcrel:8 bset #imm,@rd
* bvc pcrel:16 bset #imm,@abs:8
bvs pcrel:8 bset rs,rd
* bvs pcrel:16 bset rs,@rd
bpl pcrel:8 bset rs,@abs:8
* bpl pcrel:16 bsr pcrel:8
bmi pcrel:8 bsr pcrel:16
* bmi pcrel:16 bst #imm,rd
bge pcrel:8 bst #imm,@rd
* bge pcrel:16 bst #imm,@abs:8
blt pcrel:8 btst #imm,rd
* blt pcrel:16 btst #imm,@rd
bgt pcrel:8 btst #imm,@abs:8
* bgt pcrel:16 btst rs,rd
ble pcrel:8 btst rs,@rd
* ble pcrel:16 btst rs,@abs:8
bclr #imm,rd bxor #imm,rd
bclr #imm,@rd bxor #imm,@rd
bclr #imm,@abs:8 bxor #imm,@abs:8
bclr rs,rd cmp.b #imm,rd
bclr rs,@rd cmp.b rs,rd
bclr rs,@abs:8 cmp.w rs,rd
biand #imm,rd cmp.w rs,rd
biand #imm,@rd * cmp.w #imm,rd
biand #imm,@abs:8 * cmp.l #imm,rd
bild #imm,rd * cmp.l rs,rd
bild #imm,@rd daa rs
bild #imm,@abs:8 das rs
bior #imm,rd dec.b rs
bior #imm,@rd * dec.w #imm,rd
bior #imm,@abs:8 * dec.l #imm,rd
bist #imm,rd divxu.b rs,rd
bist #imm,@rd * divxu.w rs,rd
bist #imm,@abs:8 * divxs.b rs,rd
bixor #imm,rd * divxs.w rs,rd
bixor #imm,@rd eepmov
bixor #imm,@abs:8 * eepmovw
* exts.w rd mov.w rs,@abs:16
* exts.l rd * mov.l #imm,rd
* extu.w rd * mov.l rs,rd
* extu.l rd * mov.l @rs,rd
inc rs * mov.l @(disp:16,rs),rd
* inc.w #imm,rd * mov.l @(disp:24,rs),rd
* inc.l #imm,rd * mov.l @rs+,rd
jmp @rs * mov.l @abs:16,rd
jmp abs * mov.l @abs:24,rd
jmp @@abs:8 * mov.l rs,@rd
jsr @rs * mov.l rs,@(disp:16,rd)
jsr abs * mov.l rs,@(disp:24,rd)
jsr @@abs:8 * mov.l rs,@-rd
ldc #imm,ccr * mov.l rs,@abs:16
ldc rs,ccr * mov.l rs,@abs:24
* ldc @abs:16,ccr movfpe @abs:16,rd
* ldc @abs:24,ccr movtpe rs,@abs:16
* ldc @(disp:16,rs),ccr mulxu.b rs,rd
* ldc @(disp:24,rs),ccr * mulxu.w rs,rd
* ldc @rs+,ccr * mulxs.b rs,rd
* ldc @rs,ccr * mulxs.w rs,rd
* mov.b @(disp:24,rs),rd neg.b rs
* mov.b rs,@(disp:24,rd) * neg.w rs
mov.b @abs:16,rd * neg.l rs
mov.b rs,rd nop
mov.b @abs:8,rd not.b rs
mov.b rs,@abs:8 * not.w rs
mov.b rs,rd * not.l rs
mov.b #imm,rd or.b #imm,rd
mov.b @rs,rd or.b rs,rd
mov.b @(disp:16,rs),rd * or.w #imm,rd
mov.b @rs+,rd * or.w rs,rd
mov.b @abs:8,rd * or.l #imm,rd
mov.b rs,@rd * or.l rs,rd
mov.b rs,@(disp:16,rd) orc #imm,ccr
mov.b rs,@-rd pop.w rs
mov.b rs,@abs:8 * pop.l rs
mov.w rs,@rd push.w rs
* mov.w @(disp:24,rs),rd * push.l rs
* mov.w rs,@(disp:24,rd) rotl.b rs
* mov.w @abs:24,rd * rotl.w rs
* mov.w rs,@abs:24 * rotl.l rs
mov.w rs,rd rotr.b rs
mov.w #imm,rd * rotr.w rs
mov.w @rs,rd * rotr.l rs
mov.w @(disp:16,rs),rd rotxl.b rs
mov.w @rs+,rd * rotxl.w rs
mov.w @abs:16,rd * rotxl.l rs
mov.w rs,@(disp:16,rd) rotxr.b rs
mov.w rs,@-rd * rotxr.w rs
* rotxr.l rs * stc ccr,@(disp:24,rd)
bpt * stc ccr,@-rd
rte * stc ccr,@abs:16
rts * stc ccr,@abs:24
shal.b rs sub.b rs,rd
* shal.w rs sub.w rs,rd
* shal.l rs * sub.w #imm,rd
shar.b rs * sub.l rs,rd
* shar.w rs * sub.l #imm,rd
* shar.l rs subs #imm,rd
shll.b rs subx #imm,rd
* shll.w rs subx rs,rd
* shll.l rs * trapa #imm
shlr.b rs xor #imm,rd
* shlr.w rs xor rs,rd
* shlr.l rs * xor.w #imm,rd
sleep * xor.w rs,rd
stc ccr,rd * xor.l #imm,rd
* stc ccr,@rs * xor.l rs,rd
* stc ccr,@(disp:16,rd) xorc #imm,ccr
Four H8/300 instructions ('add', 'cmp', 'mov', 'sub') are defined
with variants using the suffixes '.b', '.w', and '.l' to specify the
size of a memory operand. 'as' supports these suffixes, but does not
require them; since one of the operands is always a register, 'as' can
deduce the correct size.
For example, since 'r0' refers to a 16-bit register,
mov r0,@foo
is equivalent to
mov.w r0,@foo
If you use the size suffixes, 'as' issues a warning when the suffix
and the register size do not match.

File: as.info, Node: HPPA-Dependent, Next: ESA/390-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies
9.13 HPPA Dependent Features
============================
* Menu:
* HPPA Notes:: Notes
* HPPA Options:: Options
* HPPA Syntax:: Syntax
* HPPA Floating Point:: Floating Point
* HPPA Directives:: HPPA Machine Directives
* HPPA Opcodes:: Opcodes

File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent
9.13.1 Notes
------------
As a back end for GNU CC 'as' has been throughly tested and should work
extremely well. We have tested it only minimally on hand written
assembly code and no one has tested it much on the assembly output from
the HP compilers.
The format of the debugging sections has changed since the original
'as' port (version 1.3X) was released; therefore, you must rebuild all
HPPA objects and libraries with the new assembler so that you can debug
the final executable.
The HPPA 'as' port generates a small subset of the relocations
available in the SOM and ELF object file formats. Additional relocation
support will be added as it becomes necessary.

File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent
9.13.2 Options
--------------
'as' has no machine-dependent command-line options for the HPPA.

File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent
9.13.3 Syntax
-------------
The assembler syntax closely follows the HPPA instruction set reference
manual; assembler directives and general syntax closely follow the HPPA
assembly language reference manual, with a few noteworthy differences.
First, a colon may immediately follow a label definition. This is
simply for compatibility with how most assembly language programmers
write code.
Some obscure expression parsing problems may affect hand written code
which uses the 'spop' instructions, or code which makes significant use
of the '!' line separator.
'as' is much less forgiving about missing arguments and other similar
oversights than the HP assembler. 'as' notifies you of missing
arguments as syntax errors; this is regarded as a feature, not a bug.
Finally, 'as' allows you to use an external symbol without explicitly
importing the symbol. _Warning:_ in the future this will be an error
for HPPA targets.
Special characters for HPPA targets include:
';' is the line comment character.
'!' can be used instead of a newline to separate statements.
Since '$' has no special meaning, you may use it in symbol names.

File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent
9.13.4 Floating Point
---------------------
The HPPA family uses IEEE floating-point numbers.

File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent
9.13.5 HPPA Assembler Directives
--------------------------------
'as' for the HPPA supports many additional directives for compatibility
with the native assembler. This section describes them only briefly.
For detailed information on HPPA-specific assembler directives, see
'HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001).
'as' does _not_ support the following assembler directives described
in the HP manual:
.endm .liston
.enter .locct
.leave .macro
.listoff
Beyond those implemented for compatibility, 'as' supports one
additional assembler directive for the HPPA: '.param'. It conveys
register argument locations for static functions. Its syntax closely
follows the '.export' directive.
These are the additional directives in 'as' for the HPPA:
'.block N'
'.blockz N'
Reserve N bytes of storage, and initialize them to zero.
'.call'
Mark the beginning of a procedure call. Only the special case with
_no arguments_ is allowed.
'.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]'
Specify a number of parameters and flags that define the
environment for a procedure.
PARAM may be any of 'frame' (frame size), 'entry_gr' (end of
general register range), 'entry_fr' (end of float register range),
'entry_sr' (end of space register range).
The values for FLAG are 'calls' or 'caller' (proc has subroutines),
'no_calls' (proc does not call subroutines), 'save_rp' (preserve
return pointer), 'save_sp' (proc preserves stack pointer),
'no_unwind' (do not unwind this proc), 'hpux_int' (proc is
interrupt routine).
'.code'
Assemble into the standard section called '$TEXT$', subsection
'$CODE$'.
'.copyright "STRING"'
In the SOM object format, insert STRING into the object code,
marked as a copyright string.
'.copyright "STRING"'
In the ELF object format, insert STRING into the object code,
marked as a version string.
'.enter'
Not yet supported; the assembler rejects programs containing this
directive.
'.entry'
Mark the beginning of a procedure.
'.exit'
Mark the end of a procedure.
'.export NAME [ ,TYP ] [ ,PARAM=R ]'
Make a procedure NAME available to callers. TYP, if present, must
be one of 'absolute', 'code' (ELF only, not SOM), 'data', 'entry',
'data', 'entry', 'millicode', 'plabel', 'pri_prog', or 'sec_prog'.
PARAM, if present, provides either relocation information for the
procedure arguments and result, or a privilege level. PARAM may be
'argwN' (where N ranges from '0' to '3', and indicates one of four
one-word arguments); 'rtnval' (the procedure's result); or
'priv_lev' (privilege level). For arguments or the result, R
specifies how to relocate, and must be one of 'no' (not
relocatable), 'gr' (argument is in general register), 'fr' (in
floating point register), or 'fu' (upper half of float register).
For 'priv_lev', R is an integer.
'.half N'
Define a two-byte integer constant N; synonym for the portable 'as'
directive '.short'.
'.import NAME [ ,TYP ]'
Converse of '.export'; make a procedure available to call. The
arguments use the same conventions as the first two arguments for
'.export'.
'.label NAME'
Define NAME as a label for the current assembly location.
'.leave'
Not yet supported; the assembler rejects programs containing this
directive.
'.origin LC'
Advance location counter to LC. Synonym for the 'as' portable
directive '.org'.
'.param NAME [ ,TYP ] [ ,PARAM=R ]'
Similar to '.export', but used for static procedures.
'.proc'
Use preceding the first statement of a procedure.
'.procend'
Use following the last statement of a procedure.
'LABEL .reg EXPR'
Synonym for '.equ'; define LABEL with the absolute expression EXPR
as its value.
'.space SECNAME [ ,PARAMS ]'
Switch to section SECNAME, creating a new section by that name if
necessary. You may only use PARAMS when creating a new section,
not when switching to an existing one. SECNAME may identify a
section by number rather than by name.
If specified, the list PARAMS declares attributes of the section,
identified by keywords. The keywords recognized are 'spnum=EXP'
(identify this section by the number EXP, an absolute expression),
'sort=EXP' (order sections according to this sort key when linking;
EXP is an absolute expression), 'unloadable' (section contains no
loadable data), 'notdefined' (this section defined elsewhere), and
'private' (data in this section not available to other programs).
'.spnum SECNAM'
Allocate four bytes of storage, and initialize them with the
section number of the section named SECNAM. (You can define the
section number with the HPPA '.space' directive.)
'.string "STR"'
Copy the characters in the string STR to the object file. *Note
Strings: Strings, for information on escape sequences you can use
in 'as' strings.
_Warning!_ The HPPA version of '.string' differs from the usual
'as' definition: it does _not_ write a zero byte after copying STR.
'.stringz "STR"'
Like '.string', but appends a zero byte after copying STR to object
file.
'.subspa NAME [ ,PARAMS ]'
'.nsubspa NAME [ ,PARAMS ]'
Similar to '.space', but selects a subsection NAME within the
current section. You may only specify PARAMS when you create a
subsection (in the first instance of '.subspa' for this NAME).
If specified, the list PARAMS declares attributes of the
subsection, identified by keywords. The keywords recognized are
'quad=EXPR' ("quadrant" for this subsection), 'align=EXPR'
(alignment for beginning of this subsection; a power of two),
'access=EXPR' (value for "access rights" field), 'sort=EXPR'
(sorting order for this subspace in link), 'code_only' (subsection
contains only code), 'unloadable' (subsection cannot be loaded into
memory), 'comdat' (subsection is comdat), 'common' (subsection is
common block), 'dup_comm' (subsection may have duplicate names), or
'zero' (subsection is all zeros, do not write in object file).
'.nsubspa' always creates a new subspace with the given name, even
if one with the same name already exists.
'comdat', 'common' and 'dup_comm' can be used to implement various
flavors of one-only support when using the SOM linker. The SOM
linker only supports specific combinations of these flags. The
details are not documented. A brief description is provided here.
'comdat' provides a form of linkonce support. It is useful for
both code and data subspaces. A 'comdat' subspace has a key symbol
marked by the 'is_comdat' flag or 'ST_COMDAT'. Only the first
subspace for any given key is selected. The key symbol becomes
universal in shared links. This is similar to the behavior of
'secondary_def' symbols.
'common' provides Fortran named common support. It is only useful
for data subspaces. Symbols with the flag 'is_common' retain this
flag in shared links. Referencing a 'is_common' symbol in a shared
library from outside the library doesn't work. Thus, 'is_common'
symbols must be output whenever they are needed.
'common' and 'dup_comm' together provide Cobol common support. The
subspaces in this case must all be the same length. Otherwise,
this support is similar to the Fortran common support.
'dup_comm' by itself provides a type of one-only support for code.
Only the first 'dup_comm' subspace is selected. There is a rather
complex algorithm to compare subspaces. Code symbols marked with
the 'dup_common' flag are hidden. This support was intended for
"C++ duplicate inlines".
A simplified technique is used to mark the flags of symbols based
on the flags of their subspace. A symbol with the scope
SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with
the corresponding settings of 'comdat', 'common' and 'dup_comm'
from the subspace, respectively. This avoids having to introduce
additional directives to mark these symbols. The HP assembler sets
'is_common' from 'common'. However, it doesn't set the
'dup_common' from 'dup_comm'. It doesn't have 'comdat' support.
'.version "STR"'
Write STR as version identifier in object code.

File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent
9.13.6 Opcodes
--------------
For detailed information on the HPPA machine instruction set, see
'PA-RISC Architecture and Instruction Set Reference Manual' (HP
09740-90039).

File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies
9.14 ESA/390 Dependent Features
===============================
* Menu:
* ESA/390 Notes:: Notes
* ESA/390 Options:: Options
* ESA/390 Syntax:: Syntax
* ESA/390 Floating Point:: Floating Point
* ESA/390 Directives:: ESA/390 Machine Directives
* ESA/390 Opcodes:: Opcodes

File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent
9.14.1 Notes
------------
The ESA/390 'as' port is currently intended to be a back-end for the GNU
CC compiler. It is not HLASM compatible, although it does support a
subset of some of the HLASM directives. The only supported binary file
format is ELF; none of the usual MVS/VM/OE/USS object file formats, such
as ESD or XSD, are supported.
When used with the GNU CC compiler, the ESA/390 'as' will produce
correct, fully relocated, functional binaries, and has been used to
compile and execute large projects. However, many aspects should still
be considered experimental; these include shared library support,
dynamically loadable objects, and any relocation other than the 31-bit
relocation.

File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent
9.14.2 Options
--------------
'as' has no machine-dependent command-line options for the ESA/390.

File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent
9.14.3 Syntax
-------------
The opcode/operand syntax follows the ESA/390 Principles of Operation
manual; assembler directives and general syntax are loosely based on the
prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives
are _not_ supported for the most part, with the exception of those
described herein.
A leading dot in front of directives is optional, and the case of
directives is ignored; thus for example, .using and USING have the same
effect.
A colon may immediately follow a label definition. This is simply
for compatibility with how most assembly language programmers write
code.
'#' is the line comment character.
';' can be used instead of a newline to separate statements.
Since '$' has no special meaning, you may use it in symbol names.
Registers can be given the symbolic names r0..r15, fp0, fp2, fp4,
fp6. By using thesse symbolic names, 'as' can detect simple syntax
errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for
r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
for r3 and rpgt or r.pgt for r4.
'*' is the current location counter. Unlike '.' it is always
relative to the last USING directive. Note that this means that
expressions cannot use multiplication, as any occurrence of '*' will be
interpreted as a location counter.
All labels are relative to the last USING. Thus, branches to a label
always imply the use of base+displacement.
Many of the usual forms of address constants / address literals are
supported. Thus,
.using *,r3
L r15,=A(some_routine)
LM r6,r7,=V(some_longlong_extern)
A r1,=F'12'
AH r0,=H'42'
ME r6,=E'3.1416'
MD r6,=D'3.14159265358979'
O r6,=XL4'cacad0d0'
.ltorg
should all behave as expected: that is, an entry in the literal pool
will be created (or reused if it already exists), and the instruction
operands will be the displacement into the literal pool using the
current base register (as last declared with the '.using' directive).

File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent
9.14.4 Floating Point
---------------------
The assembler generates only IEEE floating-point numbers. The older
floating point formats are not supported.

File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent
9.14.5 ESA/390 Assembler Directives
-----------------------------------
'as' for the ESA/390 supports all of the standard ELF/SVR4 assembler
directives that are documented in the main part of this documentation.
Several additional directives are supported in order to implement the
ESA/390 addressing model. The most important of these are '.using' and
'.ltorg'
These are the additional directives in 'as' for the ESA/390:
'.dc'
A small subset of the usual DC directive is supported.
'.drop REGNO'
Stop using REGNO as the base register. The REGNO must have been
previously declared with a '.using' directive in the same section
as the current section.
'.ebcdic STRING'
Emit the EBCDIC equivalent of the indicated string. The emitted
string will be null terminated. Note that the directives '.string'
etc. emit ascii strings by default.
'EQU'
The standard HLASM-style EQU directive is not supported; however,
the standard 'as' directive .equ can be used to the same effect.
'.ltorg'
Dump the literal pool accumulated so far; begin a new literal pool.
The literal pool will be written in the current section; in order
to generate correct assembly, a '.using' must have been previously
specified in the same section.
'.using EXPR,REGNO'
Use REGNO as the base register for all subsequent RX, RS, and SS
form instructions. The EXPR will be evaluated to obtain the base
address; usually, EXPR will merely be '*'.
This assembler allows two '.using' directives to be simultaneously
outstanding, one in the '.text' section, and one in another section
(typically, the '.data' section). This feature allows dynamically
loaded objects to be implemented in a relatively straightforward
way. A '.using' directive must always be specified in the '.text'
section; this will specify the base register that will be used for
branches in the '.text' section. A second '.using' may be
specified in another section; this will specify the base register
that is used for non-label address literals. When a second
'.using' is specified, then the subsequent '.ltorg' must be put in
the same section; otherwise an error will result.
Thus, for example, the following code uses 'r3' to address branch
targets and 'r4' to address the literal pool, which has been
written to the '.data' section. The is, the constants
'=A(some_routine)', '=H'42'' and '=E'3.1416'' will all appear in
the '.data' section.
.data
.using LITPOOL,r4
.text
BASR r3,0
.using *,r3
B START
.long LITPOOL
START:
L r4,4(,r3)
L r15,=A(some_routine)
LTR r15,r15
BNE LABEL
AH r0,=H'42'
LABEL:
ME r6,=E'3.1416'
.data
LITPOOL:
.ltorg
Note that this dual-'.using' directive semantics extends and is not
compatible with HLASM semantics. Note that this assembler
directive does not support the full range of HLASM semantics.

File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent
9.14.6 Opcodes
--------------
For detailed information on the ESA/390 machine instruction set, see
'ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004).

File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies
9.15 80386 Dependent Features
=============================
The i386 version 'as' supports both the original Intel 386 architecture
in both 16 and 32-bit mode as well as AMD x86-64 architecture extending
the Intel architecture to 64-bits.
* Menu:
* i386-Options:: Options
* i386-Directives:: X86 specific directives
* i386-Syntax:: Syntactical considerations
* i386-Mnemonics:: Instruction Naming
* i386-Regs:: Register Naming
* i386-Prefixes:: Instruction Prefixes
* i386-Memory:: Memory References
* i386-Jumps:: Handling of Jump Instructions
* i386-Float:: Floating Point
* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
* i386-LWP:: AMD's Lightweight Profiling Instructions
* i386-BMI:: Bit Manipulation Instruction
* i386-TBM:: AMD's Trailing Bit Manipulation Instructions
* i386-16bit:: Writing 16-bit Code
* i386-Arch:: Specifying an x86 CPU architecture
* i386-Bugs:: AT&T Syntax bugs
* i386-Notes:: Notes

File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent
9.15.1 Options
--------------
The i386 version of 'as' has a few machine dependent options:
'--32 | --x32 | --64'
Select the word size, either 32 bits or 64 bits. '--32' implies
Intel i386 architecture, while '--x32' and '--64' imply AMD x86-64
architecture with 32-bit or 64-bit word-size respectively.
These options are only available with the ELF object file format,
and require that the necessary BFD support has been included (on a
32-bit platform you have to add -enable-64-bit-bfd to configure
enable 64-bit usage and use x86-64 as target platform).
'-n'
By default, x86 GAS replaces multiple nop instructions used for
alignment within code sections with multi-byte nop instructions
such as leal 0(%esi,1),%esi. This switch disables the
optimization.
'--divide'
On SVR4-derived platforms, the character '/' is treated as a
comment character, which means that it cannot be used in
expressions. The '--divide' option turns '/' into a normal
character. This does not disable '/' at the beginning of a line
starting a comment, or affect using '#' for starting a comment.
'-march=CPU[+EXTENSION...]'
This option specifies the target processor. The assembler will
issue an error message if an attempt is made to assemble an
instruction which will not execute on the target processor. The
following processor names are recognized: 'i8086', 'i186', 'i286',
'i386', 'i486', 'i586', 'i686', 'pentium', 'pentiumpro',
'pentiumii', 'pentiumiii', 'pentium4', 'prescott', 'nocona',
'core', 'core2', 'corei7', 'l1om', 'k1om', 'k6', 'k6_2', 'athlon',
'opteron', 'k8', 'amdfam10', 'bdver1', 'bdver2', 'bdver3',
'bdver4', 'btver1', 'btver2', 'generic32' and 'generic64'.
In addition to the basic instruction set, the assembler can be told
to accept various extension mnemonics. For example,
'-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The
following extensions are currently supported: '8087', '287', '387',
'no87', 'mmx', 'nommx', 'sse', 'sse2', 'sse3', 'ssse3', 'sse4.1',
'sse4.2', 'sse4', 'nosse', 'avx', 'avx2', 'adx', 'rdseed',
'prfchw', 'smap', 'mpx', 'sha', 'prefetchwt1', 'clflushopt', 'se1',
'clwb', 'pcommit', 'avx512f', 'avx512cd', 'avx512er', 'avx512pf',
'avx512vl', 'avx512bw', 'avx512dq', 'avx512ifma', 'avx512vbmi',
'noavx', 'vmx', 'vmfunc', 'smx', 'xsave', 'xsaveopt', 'xsavec',
'xsaves', 'aes', 'pclmul', 'fsgsbase', 'rdrnd', 'f16c', 'bmi2',
'fma', 'movbe', 'ept', 'lzcnt', 'hle', 'rtm', 'invpcid', 'clflush',
'lwp', 'fma4', 'xop', 'cx16', 'syscall', 'rdtscp', '3dnow',
'3dnowa', 'sse4a', 'sse5', 'svme', 'abm' and 'padlock'. Note that
rather than extending a basic instruction set, the extension
mnemonics starting with 'no' revoke the respective functionality.
When the '.arch' directive is used with '-march', the '.arch'
directive will take precedent.
'-mtune=CPU'
This option specifies a processor to optimize for. When used in
conjunction with the '-march' option, only instructions of the
processor specified by the '-march' option will be generated.
Valid CPU values are identical to the processor list of
'-march=CPU'.
'-msse2avx'
This option specifies that the assembler should encode SSE
instructions with VEX prefix.
'-msse-check=NONE'
'-msse-check=WARNING'
'-msse-check=ERROR'
These options control if the assembler should check SSE
instructions. '-msse-check=NONE' will make the assembler not to
check SSE instructions, which is the default.
'-msse-check=WARNING' will make the assembler issue a warning for
any SSE instruction. '-msse-check=ERROR' will make the assembler
issue an error for any SSE instruction.
'-mavxscalar=128'
'-mavxscalar=256'
These options control how the assembler should encode scalar AVX
instructions. '-mavxscalar=128' will encode scalar AVX
instructions with 128bit vector length, which is the default.
'-mavxscalar=256' will encode scalar AVX instructions with 256bit
vector length.
'-mevexlig=128'
'-mevexlig=256'
'-mevexlig=512'
These options control how the assembler should encode
length-ignored (LIG) EVEX instructions. '-mevexlig=128' will
encode LIG EVEX instructions with 128bit vector length, which is
the default. '-mevexlig=256' and '-mevexlig=512' will encode LIG
EVEX instructions with 256bit and 512bit vector length,
respectively.
'-mevexwig=0'
'-mevexwig=1'
These options control how the assembler should encode w-ignored
(WIG) EVEX instructions. '-mevexwig=0' will encode WIG EVEX
instructions with evex.w = 0, which is the default. '-mevexwig=1'
will encode WIG EVEX instructions with evex.w = 1.
'-mmnemonic=ATT'
'-mmnemonic=INTEL'
This option specifies instruction mnemonic for matching
instructions. The '.att_mnemonic' and '.intel_mnemonic' directives
will take precedent.
'-msyntax=ATT'
'-msyntax=INTEL'
This option specifies instruction syntax when processing
instructions. The '.att_syntax' and '.intel_syntax' directives
will take precedent.
'-mnaked-reg'
This opetion specifies that registers don't require a '%' prefix.
The '.att_syntax' and '.intel_syntax' directives will take
precedent.
'-madd-bnd-prefix'
This option forces the assembler to add BND prefix to all branches,
even if such prefix was not explicitly specified in the source
code.
'-mbig-obj'
On x86-64 PE/COFF target this option forces the use of big object
file format, which allows more than 32768 sections.
'-momit-lock-prefix=NO'
'-momit-lock-prefix=YES'
These options control how the assembler should encode lock prefix.
This option is intended as a workaround for processors, that fail
on lock prefix. This option can only be safely used with
single-core, single-thread computers '-momit-lock-prefix=YES' will
omit all lock prefixes. '-momit-lock-prefix=NO' will encode lock
prefix as usual, which is the default.
'-mevexrcig=RNE'
'-mevexrcig=RD'
'-mevexrcig=RU'
'-mevexrcig=RZ'
These options control how the assembler should encode SAE-only EVEX
instructions. '-mevexrcig=RNE' will encode RC bits of EVEX
instruction with 00, which is the default. '-mevexrcig=RD',
'-mevexrcig=RU' and '-mevexrcig=RZ' will encode SAE-only EVEX
instructions with 01, 10 and 11 RC bits, respectively.

File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent
9.15.2 x86 specific Directives
------------------------------
'.lcomm SYMBOL , LENGTH[, ALIGNMENT]'
Reserve LENGTH (an absolute expression) bytes for a local common
denoted by SYMBOL. The section and value of SYMBOL are those of
the new local common. The addresses are allocated in the bss
section, so that at run-time the bytes start off zeroed. Since
SYMBOL is not declared global, it is normally not visible to 'ld'.
The optional third parameter, ALIGNMENT, specifies the desired
alignment of the symbol in the bss section.
This directive is only available for COFF based x86 targets.

File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent
9.15.3 i386 Syntactical Considerations
--------------------------------------
* Menu:
* i386-Variations:: AT&T Syntax versus Intel Syntax
* i386-Chars:: Special Characters

File: as.info, Node: i386-Variations, Next: i386-Chars, Up: i386-Syntax
9.15.3.1 AT&T Syntax versus Intel Syntax
........................................
'as' now supports assembly using Intel assembler syntax.
'.intel_syntax' selects Intel mode, and '.att_syntax' switches back to
the usual AT&T mode for compatibility with the output of 'gcc'. Either
of these directives may have an optional argument, 'prefix', or
'noprefix' specifying whether registers require a '%' prefix. AT&T
System V/386 assembler syntax is quite different from Intel syntax. We
mention these differences because almost all 80386 documents use Intel
syntax. Notable differences between the two syntaxes are:
* AT&T immediate operands are preceded by '$'; Intel immediate
operands are undelimited (Intel 'push 4' is AT&T 'pushl $4'). AT&T
register operands are preceded by '%'; Intel register operands are
undelimited. AT&T absolute (as opposed to PC relative) jump/call
operands are prefixed by '*'; they are undelimited in Intel syntax.
* AT&T and Intel syntax use the opposite order for source and
destination operands. Intel 'add eax, 4' is 'addl $4, %eax'. The
'source, dest' convention is maintained for compatibility with
previous Unix assemblers. Note that 'bound', 'invlpga', and
instructions with 2 immediate operands, such as the 'enter'
instruction, do _not_ have reversed order. *note i386-Bugs::.
* In AT&T syntax the size of memory operands is determined from the
last character of the instruction mnemonic. Mnemonic suffixes of
'b', 'w', 'l' and 'q' specify byte (8-bit), word (16-bit), long
(32-bit) and quadruple word (64-bit) memory references. Intel
syntax accomplishes this by prefixing memory operands (_not_ the
instruction mnemonics) with 'byte ptr', 'word ptr', 'dword ptr' and
'qword ptr'. Thus, Intel 'mov al, byte ptr FOO' is 'movb FOO, %al'
in AT&T syntax.
In 64-bit code, 'movabs' can be used to encode the 'mov'
instruction with the 64-bit displacement or immediate operand.
* Immediate form long jumps and calls are 'lcall/ljmp $SECTION,
$OFFSET' in AT&T syntax; the Intel syntax is 'call/jmp far
SECTION:OFFSET'. Also, the far return instruction is 'lret
$STACK-ADJUST' in AT&T syntax; Intel syntax is 'ret far
STACK-ADJUST'.
* The AT&T assembler does not provide support for multiple section
programs. Unix style systems expect all programs to be single
sections.

File: as.info, Node: i386-Chars, Prev: i386-Variations, Up: i386-Syntax
9.15.3.2 Special Characters
...........................
The presence of a '#' appearing anywhere on a line indicates the start
of a comment that extends to the end of that line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
If the '--divide' command line option has not been specified then the
'/' character appearing anywhere on a line also introduces a line
comment.
The ';' character can be used to separate statements on the same
line.

File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent
9.15.4 Instruction Naming
-------------------------
Instruction mnemonics are suffixed with one character modifiers which
specify the size of operands. The letters 'b', 'w', 'l' and 'q' specify
byte, word, long and quadruple word operands. If no suffix is specified
by an instruction then 'as' tries to fill in the missing suffix based on
the destination register operand (the last one by convention). Thus,
'mov %ax, %bx' is equivalent to 'movw %ax, %bx'; also, 'mov $1, %bx' is
equivalent to 'movw $1, bx'. Note that this is incompatible with the
AT&T Unix assembler which assumes that a missing mnemonic suffix implies
long operand size. (This incompatibility does not affect compiler
output since compilers always explicitly specify the mnemonic suffix.)
Almost all instructions have the same names in AT&T and Intel format.
There are a few exceptions. The sign extend and zero extend
instructions need two sizes to specify them. They need a size to
sign/zero extend _from_ and a size to zero extend _to_. This is
accomplished by using two instruction mnemonic suffixes in AT&T syntax.
Base names for sign extend and zero extend are 'movs...' and 'movz...'
in AT&T syntax ('movsx' and 'movzx' in Intel syntax). The instruction
mnemonic suffixes are tacked on to this base name, the _from_ suffix
before the _to_ suffix. Thus, 'movsbl %al, %edx' is AT&T syntax for
"move sign extend _from_ %al _to_ %edx." Possible suffixes, thus, are
'bl' (from byte to long), 'bw' (from byte to word), 'wl' (from word to
long), 'bq' (from byte to quadruple word), 'wq' (from word to quadruple
word), and 'lq' (from long to quadruple word).
Different encoding options can be specified via optional mnemonic
suffix. '.s' suffix swaps 2 register operands in encoding when moving
from one register to another. '.d8' or '.d32' suffix prefers 8bit or
32bit displacement in encoding.
The Intel-syntax conversion instructions
* 'cbw' -- sign-extend byte in '%al' to word in '%ax',
* 'cwde' -- sign-extend word in '%ax' to long in '%eax',
* 'cwd' -- sign-extend word in '%ax' to long in '%dx:%ax',
* 'cdq' -- sign-extend dword in '%eax' to quad in '%edx:%eax',
* 'cdqe' -- sign-extend dword in '%eax' to quad in '%rax' (x86-64
only),
* 'cqo' -- sign-extend quad in '%rax' to octuple in '%rdx:%rax'
(x86-64 only),
are called 'cbtw', 'cwtl', 'cwtd', 'cltd', 'cltq', and 'cqto' in AT&T
naming. 'as' accepts either naming for these instructions.
Far call/jump instructions are 'lcall' and 'ljmp' in AT&T syntax, but
are 'call far' and 'jump far' in Intel convention.
9.15.5 AT&T Mnemonic versus Intel Mnemonic
------------------------------------------
'as' supports assembly using Intel mnemonic. '.intel_mnemonic' selects
Intel mnemonic with Intel syntax, and '.att_mnemonic' switches back to
the usual AT&T mnemonic with AT&T syntax for compatibility with the
output of 'gcc'. Several x87 instructions, 'fadd', 'fdiv', 'fdivp',
'fdivr', 'fdivrp', 'fmul', 'fsub', 'fsubp', 'fsubr' and 'fsubrp', are
implemented in AT&T System V/386 assembler with different mnemonics from
those in Intel IA32 specification. 'gcc' generates those instructions
with AT&T mnemonic.

File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent
9.15.6 Register Naming
----------------------
Register operands are always prefixed with '%'. The 80386 registers
consist of
* the 8 32-bit registers '%eax' (the accumulator), '%ebx', '%ecx',
'%edx', '%edi', '%esi', '%ebp' (the frame pointer), and '%esp' (the
stack pointer).
* the 8 16-bit low-ends of these: '%ax', '%bx', '%cx', '%dx', '%di',
'%si', '%bp', and '%sp'.
* the 8 8-bit registers: '%ah', '%al', '%bh', '%bl', '%ch', '%cl',
'%dh', and '%dl' (These are the high-bytes and low-bytes of '%ax',
'%bx', '%cx', and '%dx')
* the 6 section registers '%cs' (code section), '%ds' (data section),
'%ss' (stack section), '%es', '%fs', and '%gs'.
* the 3 processor control registers '%cr0', '%cr2', and '%cr3'.
* the 6 debug registers '%db0', '%db1', '%db2', '%db3', '%db6', and
'%db7'.
* the 2 test registers '%tr6' and '%tr7'.
* the 8 floating point register stack '%st' or equivalently '%st(0)',
'%st(1)', '%st(2)', '%st(3)', '%st(4)', '%st(5)', '%st(6)', and
'%st(7)'. These registers are overloaded by 8 MMX registers
'%mm0', '%mm1', '%mm2', '%mm3', '%mm4', '%mm5', '%mm6' and '%mm7'.
* the 8 SSE registers registers '%xmm0', '%xmm1', '%xmm2', '%xmm3',
'%xmm4', '%xmm5', '%xmm6' and '%xmm7'.
The AMD x86-64 architecture extends the register set by:
* enhancing the 8 32-bit registers to 64-bit: '%rax' (the
accumulator), '%rbx', '%rcx', '%rdx', '%rdi', '%rsi', '%rbp' (the
frame pointer), '%rsp' (the stack pointer)
* the 8 extended registers '%r8'-'%r15'.
* the 8 32-bit low ends of the extended registers: '%r8d'-'%r15d'
* the 8 16-bit low ends of the extended registers: '%r8w'-'%r15w'
* the 8 8-bit low ends of the extended registers: '%r8b'-'%r15b'
* the 4 8-bit registers: '%sil', '%dil', '%bpl', '%spl'.
* the 8 debug registers: '%db8'-'%db15'.
* the 8 SSE registers: '%xmm8'-'%xmm15'.

File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent
9.15.7 Instruction Prefixes
---------------------------
Instruction prefixes are used to modify the following instruction. They
are used to repeat string instructions, to provide section overrides, to
perform bus lock operations, and to change operand and address sizes.
(Most instructions that normally operate on 32-bit operands will use
16-bit operands if the instruction has an "operand size" prefix.)
Instruction prefixes are best written on the same line as the
instruction they act upon. For example, the 'scas' (scan string)
instruction is repeated with:
repne scas %es:(%edi),%al
You may also place prefixes on the lines immediately preceding the
instruction, but this circumvents checks that 'as' does with prefixes,
and will not work with all prefixes.
Here is a list of instruction prefixes:
* Section override prefixes 'cs', 'ds', 'ss', 'es', 'fs', 'gs'.
These are automatically added by specifying using the
SECTION:MEMORY-OPERAND form for memory references.
* Operand/Address size prefixes 'data16' and 'addr16' change 32-bit
operands/addresses into 16-bit operands/addresses, while 'data32'
and 'addr32' change 16-bit ones (in a '.code16' section) into
32-bit operands/addresses. These prefixes _must_ appear on the
same line of code as the instruction they modify. For example, in
a 16-bit '.code16' section, you might write:
addr32 jmpl *(%ebx)
* The bus lock prefix 'lock' inhibits interrupts during execution of
the instruction it precedes. (This is only valid with certain
instructions; see a 80386 manual for details).
* The wait for coprocessor prefix 'wait' waits for the coprocessor to
complete the current instruction. This should never be needed for
the 80386/80387 combination.
* The 'rep', 'repe', and 'repne' prefixes are added to string
instructions to make them repeat '%ecx' times ('%cx' times if the
current address size is 16-bits).
* The 'rex' family of prefixes is used by x86-64 to encode extensions
to i386 instruction set. The 'rex' prefix has four bits -- an
operand size overwrite ('64') used to change operand size from
32-bit to 64-bit and X, Y and Z extensions bits used to extend the
register set.
You may write the 'rex' prefixes directly. The 'rex64xyz'
instruction emits 'rex' prefix with all the bits set. By omitting
the '64', 'x', 'y' or 'z' you may write other prefixes as well.
Normally, there is no need to write the prefixes explicitly, since
gas will automatically generate them based on the instruction
operands.

File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent
9.15.8 Memory References
------------------------
An Intel syntax indirect memory reference of the form
SECTION:[BASE + INDEX*SCALE + DISP]
is translated into the AT&T syntax
SECTION:DISP(BASE, INDEX, SCALE)
where BASE and INDEX are the optional 32-bit base and index registers,
DISP is the optional displacement, and SCALE, taking the values 1, 2, 4,
and 8, multiplies INDEX to calculate the address of the operand. If no
SCALE is specified, SCALE is taken to be 1. SECTION specifies the
optional section register for the memory operand, and may override the
default section register (see a 80386 manual for section register
defaults). Note that section overrides in AT&T syntax _must_ be
preceded by a '%'. If you specify a section override which coincides
with the default section register, 'as' does _not_ output any section
register override prefixes to assemble the given instruction. Thus,
section overrides can be specified to emphasize which section register
is used for a given memory operand.
Here are some examples of Intel and AT&T style memory references:
AT&T: '-4(%ebp)', Intel: '[ebp - 4]'
BASE is '%ebp'; DISP is '-4'. SECTION is missing, and the default
section is used ('%ss' for addressing with '%ebp' as the base
register). INDEX, SCALE are both missing.
AT&T: 'foo(,%eax,4)', Intel: '[foo + eax*4]'
INDEX is '%eax' (scaled by a SCALE 4); DISP is 'foo'. All other
fields are missing. The section register here defaults to '%ds'.
AT&T: 'foo(,1)'; Intel '[foo]'
This uses the value pointed to by 'foo' as a memory operand. Note
that BASE and INDEX are both missing, but there is only _one_ ','.
This is a syntactic exception.
AT&T: '%gs:foo'; Intel 'gs:foo'
This selects the contents of the variable 'foo' with section
register SECTION being '%gs'.
Absolute (as opposed to PC relative) call and jump operands must be
prefixed with '*'. If no '*' is specified, 'as' always chooses PC
relative addressing for jump/call labels.
Any instruction that has a memory operand, but no register operand,
_must_ specify its size (byte, word, long, or quadruple) with an
instruction mnemonic suffix ('b', 'w', 'l' or 'q', respectively).
The x86-64 architecture adds an RIP (instruction pointer relative)
addressing. This addressing mode is specified by using 'rip' as a base
register. Only constant offsets are valid. For example:
AT&T: '1234(%rip)', Intel: '[rip + 1234]'
Points to the address 1234 bytes past the end of the current
instruction.
AT&T: 'symbol(%rip)', Intel: '[rip + symbol]'
Points to the 'symbol' in RIP relative way, this is shorter than
the default absolute addressing.
Other addressing modes remain unchanged in x86-64 architecture,
except registers used are 64-bit instead of 32-bit.

File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent
9.15.9 Handling of Jump Instructions
------------------------------------
Jump instructions are always optimized to use the smallest possible
displacements. This is accomplished by using byte (8-bit) displacement
jumps whenever the target is sufficiently close. If a byte displacement
is insufficient a long displacement is used. We do not support word
(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
instruction with the 'data16' instruction prefix), since the 80386
insists upon masking '%eip' to 16 bits after the word displacement is
added. (See also *note i386-Arch::)
Note that the 'jcxz', 'jecxz', 'loop', 'loopz', 'loope', 'loopnz' and
'loopne' instructions only come in byte displacements, so that if you
use these instructions ('gcc' does not use them) you may get an error
message (and incorrect code). The AT&T 80386 assembler tries to get
around this problem by expanding 'jcxz foo' to
jcxz cx_zero
jmp cx_nonzero
cx_zero: jmp foo
cx_nonzero:

File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent
9.15.10 Floating Point
----------------------
All 80387 floating point types except packed BCD are supported. (BCD
support may be added without much difficulty). These data types are
16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit),
and extended (80-bit) precision floating point. Each supported type has
an instruction mnemonic suffix and a constructor associated with it.
Instruction mnemonic suffixes specify the operand's data type.
Constructors build these data types into memory.
* Floating point constructors are '.float' or '.single', '.double',
and '.tfloat' for 32-, 64-, and 80-bit formats. These correspond
to instruction mnemonic suffixes 's', 'l', and 't'. 't' stands for
80-bit (ten byte) real. The 80387 only supports this format via
the 'fldt' (load 80-bit real to stack top) and 'fstpt' (store
80-bit real and pop stack) instructions.
* Integer constructors are '.word', '.long' or '.int', and '.quad'
for the 16-, 32-, and 64-bit integer formats. The corresponding
instruction mnemonic suffixes are 's' (single), 'l' (long), and 'q'
(quad). As with the 80-bit real format, the 64-bit 'q' format is
only present in the 'fildq' (load quad integer to stack top) and
'fistpq' (store quad integer and pop stack) instructions.
Register to register operations should not use instruction mnemonic
suffixes. 'fstl %st, %st(1)' will give a warning, and be assembled as
if you wrote 'fst %st, %st(1)', since all register to register
operations use 80-bit floating point operands. (Contrast this with
'fstl %st, mem', which converts '%st' from 80-bit to 64-bit floating
point format, then stores the result in the 4 byte location 'mem')

File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent
9.15.11 Intel's MMX and AMD's 3DNow! SIMD Operations
----------------------------------------------------
'as' supports Intel's MMX instruction set (SIMD instructions for integer
data), available on Intel's Pentium MMX processors and Pentium II
processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and
probably others. It also supports AMD's 3DNow! instruction set (SIMD
instructions for 32-bit floating point data) available on AMD's K6-2
processor and possibly others in the future.
Currently, 'as' does not support Intel's floating point SIMD, Katmai
(KNI).
The eight 64-bit MMX operands, also used by 3DNow!, are called
'%mm0', '%mm1', ... '%mm7'. They contain eight 8-bit integers, four
16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
floating point values. The MMX registers cannot be used at the same
time as the floating point stack.
See Intel and AMD documentation, keeping in mind that the operand
order in instructions is reversed from the Intel syntax.

File: as.info, Node: i386-LWP, Next: i386-BMI, Prev: i386-SIMD, Up: i386-Dependent
9.15.12 AMD's Lightweight Profiling Instructions
------------------------------------------------
'as' supports AMD's Lightweight Profiling (LWP) instruction set,
available on AMD's Family 15h (Orochi) processors.
LWP enables applications to collect and manage performance data, and
react to performance events. The collection of performance data
requires no context switches. LWP runs in the context of a thread and
so several counters can be used independently across multiple threads.
LWP can be used in both 64-bit and legacy 32-bit modes.
For detailed information on the LWP instruction set, see the 'AMD
Lightweight Profiling Specification' available at Lightweight Profiling
Specification (http://developer.amd.com/cpu/LWP).

File: as.info, Node: i386-BMI, Next: i386-TBM, Prev: i386-LWP, Up: i386-Dependent
9.15.13 Bit Manipulation Instructions
-------------------------------------
'as' supports the Bit Manipulation (BMI) instruction set.
BMI instructions provide several instructions implementing individual
bit manipulation operations such as isolation, masking, setting, or
resetting.

File: as.info, Node: i386-TBM, Next: i386-16bit, Prev: i386-BMI, Up: i386-Dependent
9.15.14 AMD's Trailing Bit Manipulation Instructions
----------------------------------------------------
'as' supports AMD's Trailing Bit Manipulation (TBM) instruction set,
available on AMD's BDVER2 processors (Trinity and Viperfish).
TBM instructions provide instructions implementing individual bit
manipulation operations such as isolating, masking, setting, resetting,
complementing, and operations on trailing zeros and ones.

File: as.info, Node: i386-16bit, Next: i386-Bugs, Prev: i386-TBM, Up: i386-Dependent
9.15.15 Writing 16-bit Code
---------------------------
While 'as' normally writes only "pure" 32-bit i386 code or 64-bit x86-64
code depending on the default configuration, it also supports writing
code to run in real mode or in 16-bit protected mode code segments. To
do this, put a '.code16' or '.code16gcc' directive before the assembly
language instructions to be run in 16-bit mode. You can switch 'as' to
writing 32-bit code with the '.code32' directive or 64-bit code with the
'.code64' directive.
'.code16gcc' provides experimental support for generating 16-bit code
from gcc, and differs from '.code16' in that 'call', 'ret', 'enter',
'leave', 'push', 'pop', 'pusha', 'popa', 'pushf', and 'popf'
instructions default to 32-bit size. This is so that the stack pointer
is manipulated in the same way over function calls, allowing access to
function parameters at the same stack offsets as in 32-bit mode.
'.code16gcc' also automatically adds address size prefixes where
necessary to use the 32-bit addressing modes that gcc generates.
The code which 'as' generates in 16-bit mode will not necessarily run
on a 16-bit pre-80386 processor. To write code that runs on such a
processor, you must refrain from using _any_ 32-bit constructs which
require 'as' to output address or operand size prefixes.
Note that writing 16-bit code instructions by explicitly specifying a
prefix or an instruction mnemonic suffix within a 32-bit code section
generates different machine instructions than those generated for a
16-bit code segment. In a 32-bit code section, the following code
generates the machine opcode bytes '66 6a 04', which pushes the value
'4' onto the stack, decrementing '%esp' by 2.
pushw $4
The same code in a 16-bit code section would generate the machine
opcode bytes '6a 04' (i.e., without the operand size prefix), which is
correct since the processor default operand size is assumed to be 16
bits in a 16-bit code section.

File: as.info, Node: i386-Bugs, Next: i386-Arch, Prev: i386-16bit, Up: i386-Dependent
9.15.16 AT&T Syntax bugs
------------------------
The UnixWare assembler, and probably other AT&T derived ix86 Unix
assemblers, generate floating point instructions with reversed source
and destination registers in certain cases. Unfortunately, gcc and
possibly many other programs use this reversed syntax, so we're stuck
with it.
For example
fsub %st,%st(3)
results in '%st(3)' being updated to '%st - %st(3)' rather than the
expected '%st(3) - %st'. This happens with all the non-commutative
arithmetic floating point operations with two register operands where
the source register is '%st' and the destination register is '%st(i)'.

File: as.info, Node: i386-Arch, Next: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent
9.15.17 Specifying CPU Architecture
-----------------------------------
'as' may be told to assemble for a particular CPU (sub-)architecture
with the '.arch CPU_TYPE' directive. This directive enables a warning
when gas detects an instruction that is not supported on the CPU
specified. The choices for CPU_TYPE are:
'i8086' 'i186' 'i286' 'i386'
'i486' 'i586' 'i686' 'pentium'
'pentiumpro' 'pentiumii' 'pentiumiii' 'pentium4'
'prescott' 'nocona' 'core' 'core2'
'corei7' 'l1om' 'k1om'
'k6' 'k6_2' 'athlon' 'k8'
'amdfam10' 'bdver1' 'bdver2' 'bdver3'
'bdver4' 'btver1' 'btver2'
'generic32' 'generic64'
'.mmx' '.sse' '.sse2' '.sse3'
'.ssse3' '.sse4.1' '.sse4.2' '.sse4'
'.avx' '.vmx' '.smx' '.ept'
'.clflush' '.movbe' '.xsave' '.xsaveopt'
'.aes' '.pclmul' '.fma' '.fsgsbase'
'.rdrnd' '.f16c' '.avx2' '.bmi2'
'.lzcnt' '.invpcid' '.vmfunc' '.hle'
'.rtm' '.adx' '.rdseed' '.prfchw'
'.smap' '.mpx' '.sha' '.prefetchwt1'
'.clflushopt' '.xsavec' '.xsaves' '.se1'
'.avx512f' '.avx512cd' '.avx512er' '.avx512pf'
'.avx512vl' '.avx512bw' '.avx512dq' '.avx512ifma'
'.avx512vbmi' '.clwb' '.pcommit'
'.3dnow' '.3dnowa' '.sse4a' '.sse5'
'.syscall' '.rdtscp' '.svme' '.abm'
'.lwp' '.fma4' '.xop' '.cx16'
'.padlock'
Apart from the warning, there are only two other effects on 'as'
operation; Firstly, if you specify a CPU other than 'i486', then shift
by one instructions such as 'sarl $1, %eax' will automatically use a two
byte opcode sequence. The larger three byte opcode sequence is used on
the 486 (and when no architecture is specified) because it executes
faster on the 486. Note that you can explicitly request the two byte
opcode by writing 'sarl %eax'. Secondly, if you specify 'i8086',
'i186', or 'i286', _and_ '.code16' or '.code16gcc' then byte offset
conditional jumps will be promoted when necessary to a two instruction
sequence consisting of a conditional jump of the opposite sense around
an unconditional jump to the target.
Following the CPU architecture (but not a sub-architecture, which are
those starting with a dot), you may specify 'jumps' or 'nojumps' to
control automatic promotion of conditional jumps. 'jumps' is the
default, and enables jump promotion; All external jumps will be of the
long variety, and file-local jumps will be promoted as necessary.
(*note i386-Jumps::) 'nojumps' leaves external conditional jumps as byte
offset jumps, and warns about file-local conditional jumps that 'as'
promotes. Unconditional jumps are treated as for 'jumps'.
For example
.arch i8086,nojumps

File: as.info, Node: i386-Notes, Prev: i386-Arch, Up: i386-Dependent
9.15.18 Notes
-------------
There is some trickery concerning the 'mul' and 'imul' instructions that
deserves mention. The 16-, 32-, 64- and 128-bit expanding multiplies
(base opcode '0xf6'; extension 4 for 'mul' and 5 for 'imul') can be
output only in the one operand form. Thus, 'imul %ebx, %eax' does _not_
select the expanding multiply; the expanding multiply would clobber the
'%edx' register, and this would confuse 'gcc' output. Use 'imul %ebx'
to get the 64-bit product in '%edx:%eax'.
We have added a two operand form of 'imul' when the first operand is
an immediate mode expression and the second operand is a register. This
is just a shorthand, so that, multiplying '%eax' by 69, for example, can
be done with 'imul $69, %eax' rather than 'imul $69, %eax, %eax'.

File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies
9.16 Intel i860 Dependent Features
==================================
* Menu:
* Notes-i860:: i860 Notes
* Options-i860:: i860 Command-line Options
* Directives-i860:: i860 Machine Directives
* Opcodes for i860:: i860 Opcodes
* Syntax of i860:: i860 Syntax

File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent
9.16.1 i860 Notes
-----------------
This is a fairly complete i860 assembler which is compatible with the
UNIX System V/860 Release 4 assembler. However, it does not currently
support SVR4 PIC (i.e., '@GOT, @GOTOFF, @PLT').
Like the SVR4/860 assembler, the output object format is ELF32.
Currently, this is the only supported object format. If there is
sufficient interest, other formats such as COFF may be implemented.
Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter
being the default. One difference is that AT&T syntax requires the '%'
prefix on register names while Intel syntax does not. Another
difference is in the specification of relocatable expressions. The
Intel syntax is 'ha%expression' whereas the SVR4 syntax is
'[expression]@ha' (and similarly for the "l" and "h" selectors).

File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent
9.16.2 i860 Command-line Options
--------------------------------
9.16.2.1 SVR4 compatibility options
...................................
'-V'
Print assembler version.
'-Qy'
Ignored.
'-Qn'
Ignored.
9.16.2.2 Other options
......................
'-EL'
Select little endian output (this is the default).
'-EB'
Select big endian output. Note that the i860 always reads
instructions as little endian data, so this option only effects
data and not instructions.
'-mwarn-expand'
Emit a warning message if any pseudo-instruction expansions
occurred. For example, a 'or' instruction with an immediate larger
than 16-bits will be expanded into two instructions. This is a
very undesirable feature to rely on, so this flag can help detect
any code where it happens. One use of it, for instance, has been
to find and eliminate any place where 'gcc' may emit these
pseudo-instructions.
'-mxp'
Enable support for the i860XP instructions and control registers.
By default, this option is disabled so that only the base
instruction set (i.e., i860XR) is supported.
'-mintel-syntax'
The i860 assembler defaults to AT&T/SVR4 syntax. This option
enables the Intel syntax.

File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent
9.16.3 i860 Machine Directives
------------------------------
'.dual'
Enter dual instruction mode. While this directive is supported,
the preferred way to use dual instruction mode is to explicitly
code the dual bit with the 'd.' prefix.
'.enddual'
Exit dual instruction mode. While this directive is supported, the
preferred way to use dual instruction mode is to explicitly code
the dual bit with the 'd.' prefix.
'.atmp'
Change the temporary register used when expanding pseudo
operations. The default register is 'r31'.
The '.dual', '.enddual', and '.atmp' directives are available only in
the Intel syntax mode.
Both syntaxes allow for the standard '.align' directive. However,
the Intel syntax additionally allows keywords for the alignment
parameter: "'.align type'", where 'type' is one of '.short', '.long',
'.quad', '.single', '.double' representing alignments of 2, 4, 16, 4,
and 8, respectively.

File: as.info, Node: Opcodes for i860, Next: Syntax of i860, Prev: Directives-i860, Up: i860-Dependent
9.16.4 i860 Opcodes
-------------------
All of the Intel i860XR and i860XP machine instructions are supported.
Please see either _i860 Microprocessor Programmer's Reference Manual_ or
_i860 Microprocessor Architecture_ for more information.
9.16.4.1 Other instruction support (pseudo-instructions)
........................................................
For compatibility with some other i860 assemblers, a number of
pseudo-instructions are supported. While these are supported, they are
a very undesirable feature that should be avoided - in particular, when
they result in an expansion to multiple actual i860 instructions. Below
are the pseudo-instructions that result in expansions.
* Load large immediate into general register:
The pseudo-instruction 'mov imm,%rn' (where the immediate does not
fit within a signed 16-bit field) will be expanded into:
orh large_imm@h,%r0,%rn
or large_imm@l,%rn,%rn
* Load/store with relocatable address expression:
For example, the pseudo-instruction 'ld.b addr_exp(%rx),%rn' will
be expanded into:
orh addr_exp@ha,%rx,%r31
ld.l addr_exp@l(%r31),%rn
The analogous expansions apply to 'ld.x, st.x, fld.x, pfld.x,
fst.x', and 'pst.x' as well.
* Signed large immediate with add/subtract:
If any of the arithmetic operations 'adds, addu, subs, subu' are
used with an immediate larger than 16-bits (signed), then they will
be expanded. For instance, the pseudo-instruction 'adds
large_imm,%rx,%rn' expands to:
orh large_imm@h,%r0,%r31
or large_imm@l,%r31,%r31
adds %r31,%rx,%rn
* Unsigned large immediate with logical operations:
Logical operations ('or, andnot, or, xor') also result in
expansions. The pseudo-instruction 'or large_imm,%rx,%rn' results
in:
orh large_imm@h,%rx,%r31
or large_imm@l,%r31,%rn
Similarly for the others, except for 'and' which expands to:
andnot (-1 - large_imm)@h,%rx,%r31
andnot (-1 - large_imm)@l,%r31,%rn

File: as.info, Node: Syntax of i860, Prev: Opcodes for i860, Up: i860-Dependent
9.16.5 i860 Syntax
------------------
* Menu:
* i860-Chars:: Special Characters

File: as.info, Node: i860-Chars, Up: Syntax of i860
9.16.5.1 Special Characters
...........................
The presence of a '#' appearing anywhere on a line indicates the start
of a comment that extends to the end of that line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
The ';' character can be used to separate statements on the same
line.

File: as.info, Node: i960-Dependent, Next: IA-64-Dependent, Prev: i860-Dependent, Up: Machine Dependencies
9.17 Intel 80960 Dependent Features
===================================
* Menu:
* Options-i960:: i960 Command-line Options
* Floating Point-i960:: Floating Point
* Directives-i960:: i960 Machine Directives
* Opcodes for i960:: i960 Opcodes
* Syntax of i960:: i960 Syntax

File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent
9.17.1 i960 Command-line Options
--------------------------------
'-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
Select the 80960 architecture. Instructions or features not
supported by the selected architecture cause fatal errors.
'-ACA' is equivalent to '-ACA_A'; '-AKC' is equivalent to '-AMC'.
Synonyms are provided for compatibility with other tools.
If you do not specify any of these options, 'as' generates code for
any instruction or feature that is supported by _some_ version of
the 960 (even if this means mixing architectures!). In principle,
'as' attempts to deduce the minimal sufficient processor type if
none is specified; depending on the object code format, the
processor type may be recorded in the object file. If it is
critical that the 'as' output match a specific architecture,
specify that architecture explicitly.
'-b'
Add code to collect information about conditional branches taken,
for later optimization using branch prediction bits. (The
conditional branch instructions have branch prediction bits in the
CA, CB, and CC architectures.) If BR represents a conditional
branch instruction, the following represents the code generated by
the assembler when '-b' is specified:
call INCREMENT ROUTINE
.word 0 # pre-counter
Label: BR
call INCREMENT ROUTINE
.word 0 # post-counter
The counter following a branch records the number of times that
branch was _not_ taken; the difference between the two counters is
the number of times the branch _was_ taken.
A table of every such 'Label' is also generated, so that the
external postprocessor 'gbr960' (supplied by Intel) can locate all
the counters. This table is always labeled '__BRANCH_TABLE__';
this is a local symbol to permit collecting statistics for many
separate object files. The table is word aligned, and begins with
a two-word header. The first word, initialized to 0, is used in
maintaining linked lists of branch tables. The second word is a
count of the number of entries in the table, which follow
immediately: each is a word, pointing to one of the labels
illustrated above.
+------------+------------+------------+ ... +------------+
| | | | | |
| *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N |
| | | | | |
+------------+------------+------------+ ... +------------+
__BRANCH_TABLE__ layout
The first word of the header is used to locate multiple branch
tables, since each object file may contain one. Normally the links
are maintained with a call to an initialization routine, placed at
the beginning of each function in the file. The GNU C compiler
generates these calls automatically when you give it a '-b' option.
For further details, see the documentation of 'gbr960'.
'-no-relax'
Normally, Compare-and-Branch instructions with targets that require
displacements greater than 13 bits (or that have external targets)
are replaced with the corresponding compare (or 'chkbit') and
branch instructions. You can use the '-no-relax' option to specify
that 'as' should generate errors instead, if the target
displacement is larger than 13 bits.
This option does not affect the Compare-and-Jump instructions; the
code emitted for them is _always_ adjusted when necessary
(depending on displacement size), regardless of whether you use
'-no-relax'.

File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent
9.17.2 Floating Point
---------------------
'as' generates IEEE floating-point numbers for the directives '.float',
'.double', '.extended', and '.single'.

File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent
9.17.3 i960 Machine Directives
------------------------------
'.bss SYMBOL, LENGTH, ALIGN'
Reserve LENGTH bytes in the bss section for a local SYMBOL, aligned
to the power of two specified by ALIGN. LENGTH and ALIGN must be
positive absolute expressions. This directive differs from
'.lcomm' only in that it permits you to specify an alignment.
*Note '.lcomm': Lcomm.
'.extended FLONUMS'
'.extended' expects zero or more flonums, separated by commas; for
each flonum, '.extended' emits an IEEE extended-format (80-bit)
floating-point number.
'.leafproc CALL-LAB, BAL-LAB'
You can use the '.leafproc' directive in conjunction with the
optimized 'callj' instruction to enable faster calls of leaf
procedures. If a procedure is known to call no other procedures,
you may define an entry point that skips procedure prolog code (and
that does not depend on system-supplied saved context), and declare
it as the BAL-LAB using '.leafproc'. If the procedure also has an
entry point that goes through the normal prolog, you can specify
that entry point as CALL-LAB.
A '.leafproc' declaration is meant for use in conjunction with the
optimized call instruction 'callj'; the directive records the data
needed later to choose between converting the 'callj' into a 'bal'
or a 'call'.
CALL-LAB is optional; if only one argument is present, or if the
two arguments are identical, the single argument is assumed to be
the 'bal' entry point.
'.sysproc NAME, INDEX'
The '.sysproc' directive defines a name for a system procedure.
After you define it using '.sysproc', you can use NAME to refer to
the system procedure identified by INDEX when calling procedures
with the optimized call instruction 'callj'.
Both arguments are required; INDEX must be between 0 and 31
(inclusive).

File: as.info, Node: Opcodes for i960, Next: Syntax of i960, Prev: Directives-i960, Up: i960-Dependent
9.17.4 i960 Opcodes
-------------------
All Intel 960 machine instructions are supported; *note i960
Command-line Options: Options-i960. for a discussion of selecting the
instruction subset for a particular 960 architecture.
Some opcodes are processed beyond simply emitting a single
corresponding instruction: 'callj', and Compare-and-Branch or
Compare-and-Jump instructions with target displacements larger than 13
bits.
* Menu:
* callj-i960:: 'callj'
* Compare-and-branch-i960:: Compare-and-Branch

File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960
9.17.4.1 'callj'
................
You can write 'callj' to have the assembler or the linker determine the
most appropriate form of subroutine call: 'call', 'bal', or 'calls'. If
the assembly source contains enough information--a '.leafproc' or
'.sysproc' directive defining the operand--then 'as' translates the
'callj'; if not, it simply emits the 'callj', leaving it for the linker
to resolve.

File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960
9.17.4.2 Compare-and-Branch
...........................
The 960 architectures provide combined Compare-and-Branch instructions
that permit you to store the branch target in the lower 13 bits of the
instruction word itself. However, if you specify a branch target far
enough away that its address won't fit in 13 bits, the assembler can
either issue an error, or convert your Compare-and-Branch instruction
into separate instructions to do the compare and the branch.
Whether 'as' gives an error or expands the instruction depends on two
choices you can make: whether you use the '-no-relax' option, and
whether you use a "Compare and Branch" instruction or a "Compare and
Jump" instruction. The "Jump" instructions are _always_ expanded if
necessary; the "Branch" instructions are expanded when necessary
_unless_ you specify '-no-relax'--in which case 'as' gives an error
instead.
These are the Compare-and-Branch instructions, their "Jump" variants,
and the instruction pairs they may expand into:
Compare and
Branch Jump Expanded to
------ ------ ------------
bbc chkbit; bno
bbs chkbit; bo
cmpibe cmpije cmpi; be
cmpibg cmpijg cmpi; bg
cmpibge cmpijge cmpi; bge
cmpibl cmpijl cmpi; bl
cmpible cmpijle cmpi; ble
cmpibno cmpijno cmpi; bno
cmpibne cmpijne cmpi; bne
cmpibo cmpijo cmpi; bo
cmpobe cmpoje cmpo; be
cmpobg cmpojg cmpo; bg
cmpobge cmpojge cmpo; bge
cmpobl cmpojl cmpo; bl
cmpoble cmpojle cmpo; ble
cmpobne cmpojne cmpo; bne

File: as.info, Node: Syntax of i960, Prev: Opcodes for i960, Up: i960-Dependent
9.17.5 Syntax for the i960
--------------------------
* Menu:
* i960-Chars:: Special Characters

File: as.info, Node: i960-Chars, Up: Syntax of i960
9.17.5.1 Special Characters
...........................
The presence of a '#' on a line indicates the start of a comment that
extends to the end of the current line.
If a '#' appears as the first character of a line, the whole line is
treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
The ';' character can be used to separate statements on the same
line.

File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies
9.18 IA-64 Dependent Features
=============================
* Menu:
* IA-64 Options:: Options
* IA-64 Syntax:: Syntax
* IA-64 Opcodes:: Opcodes

File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent
9.18.1 Options
--------------
'-mconstant-gp'
This option instructs the assembler to mark the resulting object
file as using the "constant GP" model. With this model, it is
assumed that the entire program uses a single global pointer (GP)
value. Note that this option does not in any fashion affect the
machine code emitted by the assembler. All it does is turn on the
EF_IA_64_CONS_GP flag in the ELF file header.
'-mauto-pic'
This option instructs the assembler to mark the resulting object
file as using the "constant GP without function descriptor" data
model. This model is like the "constant GP" model, except that it
additionally does away with function descriptors. What this means
is that the address of a function refers directly to the function's
code entry-point. Normally, such an address would refer to a
function descriptor, which contains both the code entry-point and
the GP-value needed by the function. Note that this option does
not in any fashion affect the machine code emitted by the
assembler. All it does is turn on the EF_IA_64_NOFUNCDESC_CONS_GP
flag in the ELF file header.
'-milp32'
'-milp64'
'-mlp64'
'-mp64'
These options select the data model. The assembler defaults to
'-mlp64' (LP64 data model).
'-mle'
'-mbe'
These options select the byte order. The '-mle' option selects
little-endian byte order (default) and '-mbe' selects big-endian
byte order. Note that IA-64 machine code always uses little-endian
byte order.
'-mtune=itanium1'
'-mtune=itanium2'
Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default
is ITANIUM2.
'-munwind-check=warning'
'-munwind-check=error'
These options control what the assembler will do when performing
consistency checks on unwind directives. '-munwind-check=warning'
will make the assembler issue a warning when an unwind directive
check fails. This is the default. '-munwind-check=error' will
make the assembler issue an error when an unwind directive check
fails.
'-mhint.b=ok'
'-mhint.b=warning'
'-mhint.b=error'
These options control what the assembler will do when the 'hint.b'
instruction is used. '-mhint.b=ok' will make the assembler accept
'hint.b'. '-mint.b=warning' will make the assembler issue a
warning when 'hint.b' is used. '-mhint.b=error' will make the
assembler treat 'hint.b' as an error, which is the default.
'-x'
'-xexplicit'
These options turn on dependency violation checking.
'-xauto'
This option instructs the assembler to automatically insert stop
bits where necessary to remove dependency violations. This is the
default mode.
'-xnone'
This option turns off dependency violation checking.
'-xdebug'
This turns on debug output intended to help tracking down bugs in
the dependency violation checker.
'-xdebugn'
This is a shortcut for -xnone -xdebug.
'-xdebugx'
This is a shortcut for -xexplicit -xdebug.

File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent
9.18.2 Syntax
-------------
The assembler syntax closely follows the IA-64 Assembly Language
Reference Guide.
* Menu:
* IA-64-Chars:: Special Characters
* IA-64-Regs:: Register Names
* IA-64-Bits:: Bit Names
* IA-64-Relocs:: Relocations

File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax
9.18.2.1 Special Characters
...........................
'//' is the line comment token.
';' can be used instead of a newline to separate statements.

File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax
9.18.2.2 Register Names
.......................
The 128 integer registers are referred to as 'rN'. The 128
floating-point registers are referred to as 'fN'. The 128 application
registers are referred to as 'arN'. The 128 control registers are
referred to as 'crN'. The 64 one-bit predicate registers are referred
to as 'pN'. The 8 branch registers are referred to as 'bN'. In
addition, the assembler defines a number of aliases: 'gp' ('r1'), 'sp'
('r12'), 'rp' ('b0'), 'ret0' ('r8'), 'ret1' ('r9'), 'ret2' ('r10'),
'ret3' ('r9'), 'fargN' ('f8+N'), and 'fretN' ('f8+N').
For convenience, the assembler also defines aliases for all named
application and control registers. For example, 'ar.bsp' refers to the
register backing store pointer ('ar17'). Similarly, 'cr.eoi' refers to
the end-of-interrupt register ('cr67').

File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax
9.18.2.3 IA-64 Processor-Status-Register (PSR) Bit Names
........................................................
The assembler defines bit masks for each of the bits in the IA-64
processor status register. For example, 'psr.ic' corresponds to a value
of 0x2000. These masks are primarily intended for use with the
'ssm'/'sum' and 'rsm'/'rum' instructions, but they can be used anywhere
else where an integer constant is expected.

File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax
9.18.2.4 Relocations
....................
In addition to the standard IA-64 relocations, the following relocations
are implemented by 'as':
'@slotcount(V)'
Convert the address offset V into a slot count. This pseudo
function is available only on VMS. The expression V must be known
at assembly time: it can't reference undefined symbols or symbols
in different sections.

File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent
9.18.3 Opcodes
--------------
For detailed information on the IA-64 machine instruction set, see the
IA-64 Architecture Handbook
(http://developer.intel.com/design/itanium/arch_spec.htm).

File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies
9.19 IP2K Dependent Features
============================
* Menu:
* IP2K-Opts:: IP2K Options
* IP2K-Syntax:: IP2K Syntax

File: as.info, Node: IP2K-Opts, Next: IP2K-Syntax, Up: IP2K-Dependent
9.19.1 IP2K Options
-------------------
The Ubicom IP2K version of 'as' has a few machine dependent options:
'-mip2022ext'
'as' can assemble the extended IP2022 instructions, but it will
only do so if this is specifically allowed via this command line
option.
'-mip2022'
This option restores the assembler's default behaviour of not
permitting the extended IP2022 instructions to be assembled.

File: as.info, Node: IP2K-Syntax, Prev: IP2K-Opts, Up: IP2K-Dependent
9.19.2 IP2K Syntax
------------------
* Menu:
* IP2K-Chars:: Special Characters

File: as.info, Node: IP2K-Chars, Up: IP2K-Syntax
9.19.2.1 Special Characters
...........................
The presence of a ';' on a line indicates the start of a comment that
extends to the end of the current line.
If a '#' appears as the first character of a line, the whole line is
treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
The IP2K assembler does not currently support a line separator
character.

File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies
9.20 LM32 Dependent Features
============================
* Menu:
* LM32 Options:: Options
* LM32 Syntax:: Syntax
* LM32 Opcodes:: Opcodes

File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent
9.20.1 Options
--------------
'-mmultiply-enabled'
Enable multiply instructions.
'-mdivide-enabled'
Enable divide instructions.
'-mbarrel-shift-enabled'
Enable barrel-shift instructions.
'-msign-extend-enabled'
Enable sign extend instructions.
'-muser-enabled'
Enable user defined instructions.
'-micache-enabled'
Enable instruction cache related CSRs.
'-mdcache-enabled'
Enable data cache related CSRs.
'-mbreak-enabled'
Enable break instructions.
'-mall-enabled'
Enable all instructions and CSRs.

File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent
9.20.2 Syntax
-------------
* Menu:
* LM32-Regs:: Register Names
* LM32-Modifiers:: Relocatable Expression Modifiers
* LM32-Chars:: Special Characters

File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax
9.20.2.1 Register Names
.......................
LM32 has 32 x 32-bit general purpose registers 'r0', 'r1', ... 'r31'.
The following aliases are defined: 'gp' - 'r26', 'fp' - 'r27', 'sp' -
'r28', 'ra' - 'r29', 'ea' - 'r30', 'ba' - 'r31'.
LM32 has the following Control and Status Registers (CSRs).
'IE'
Interrupt enable.
'IM'
Interrupt mask.
'IP'
Interrupt pending.
'ICC'
Instruction cache control.
'DCC'
Data cache control.
'CC'
Cycle counter.
'CFG'
Configuration.
'EBA'
Exception base address.
'DC'
Debug control.
'DEBA'
Debug exception base address.
'JTX'
JTAG transmit.
'JRX'
JTAG receive.
'BP0'
Breakpoint 0.
'BP1'
Breakpoint 1.
'BP2'
Breakpoint 2.
'BP3'
Breakpoint 3.
'WP0'
Watchpoint 0.
'WP1'
Watchpoint 1.
'WP2'
Watchpoint 2.
'WP3'
Watchpoint 3.

File: as.info, Node: LM32-Modifiers, Next: LM32-Chars, Prev: LM32-Regs, Up: LM32 Syntax
9.20.2.2 Relocatable Expression Modifiers
.........................................
The assembler supports several modifiers when using relocatable
addresses in LM32 instruction operands. The general syntax is the
following:
modifier(relocatable-expression)
'lo'
This modifier allows you to use bits 0 through 15 of an address
expression as 16 bit relocatable expression.
'hi'
This modifier allows you to use bits 16 through 23 of an address
expression as 16 bit relocatable expression.
For example
ori r4, r4, lo(sym+10)
orhi r4, r4, hi(sym+10)
'gp'
This modified creates a 16-bit relocatable expression that is the
offset of the symbol from the global pointer.
mva r4, gp(sym)
'got'
This modifier places a symbol in the GOT and creates a 16-bit
relocatable expression that is the offset into the GOT of this
symbol.
lw r4, (gp+got(sym))
'gotofflo16'
This modifier allows you to use the bits 0 through 15 of an address
which is an offset from the GOT.
'gotoffhi16'
This modifier allows you to use the bits 16 through 31 of an
address which is an offset from the GOT.
orhi r4, r4, gotoffhi16(lsym)
addi r4, r4, gotofflo16(lsym)

File: as.info, Node: LM32-Chars, Prev: LM32-Modifiers, Up: LM32 Syntax
9.20.2.3 Special Characters
...........................
The presence of a '#' on a line indicates the start of a comment that
extends to the end of the current line. Note that if a line starts with
a '#' character then it can also be a logical line number directive
(*note Comments::) or a preprocessor control command (*note
Preprocessing::).
A semicolon (';') can be used to separate multiple statements on the
same line.

File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent
9.20.3 Opcodes
--------------
For detailed information on the LM32 machine instruction set, see
<http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/>.
'as' implements all the standard LM32 opcodes.

File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies
9.21 M32C Dependent Features
============================
'as' can assemble code for several different members of the Renesas M32C
family. Normally the default is to assemble code for the M16C
microprocessor. The '-m32c' option may be used to change the default to
the M32C microprocessor.
* Menu:
* M32C-Opts:: M32C Options
* M32C-Syntax:: M32C Syntax

File: as.info, Node: M32C-Opts, Next: M32C-Syntax, Up: M32C-Dependent
9.21.1 M32C Options
-------------------
The Renesas M32C version of 'as' has these machine-dependent options:
'-m32c'
Assemble M32C instructions.
'-m16c'
Assemble M16C instructions (default).
'-relax'
Enable support for link-time relaxations.
'-h-tick-hex'
Support H'00 style hex constants in addition to 0x00 style.

File: as.info, Node: M32C-Syntax, Prev: M32C-Opts, Up: M32C-Dependent
9.21.2 M32C Syntax
------------------
* Menu:
* M32C-Modifiers:: Symbolic Operand Modifiers
* M32C-Chars:: Special Characters

File: as.info, Node: M32C-Modifiers, Next: M32C-Chars, Up: M32C-Syntax
9.21.2.1 Symbolic Operand Modifiers
...................................
The assembler supports several modifiers when using symbol addresses in
M32C instruction operands. The general syntax is the following:
%modifier(symbol)
'%dsp8'
'%dsp16'
These modifiers override the assembler's assumptions about how big
a symbol's address is. Normally, when it sees an operand like
'sym[a0]' it assumes 'sym' may require the widest displacement
field (16 bits for '-m16c', 24 bits for '-m32c'). These modifiers
tell it to assume the address will fit in an 8 or 16 bit
(respectively) unsigned displacement. Note that, of course, if it
doesn't actually fit you will get linker errors. Example:
mov.w %dsp8(sym)[a0],r1
mov.b #0,%dsp8(sym)[a0]
'%hi8'
This modifier allows you to load bits 16 through 23 of a 24 bit
address into an 8 bit register. This is useful with, for example,
the M16C 'smovf' instruction, which expects a 20 bit address in
'r1h' and 'a0'. Example:
mov.b #%hi8(sym),r1h
mov.w #%lo16(sym),a0
smovf.b
'%lo16'
Likewise, this modifier allows you to load bits 0 through 15 of a
24 bit address into a 16 bit register.
'%hi16'
This modifier allows you to load bits 16 through 31 of a 32 bit
address into a 16 bit register. While the M32C family only has 24
bits of address space, it does support addresses in pairs of 16 bit
registers (like 'a1a0' for the 'lde' instruction). This modifier
is for loading the upper half in such cases. Example:
mov.w #%hi16(sym),a1
mov.w #%lo16(sym),a0
...
lde.w [a1a0],r1

File: as.info, Node: M32C-Chars, Prev: M32C-Modifiers, Up: M32C-Syntax
9.21.2.2 Special Characters
...........................
The presence of a ';' character on a line indicates the start of a
comment that extends to the end of that line.
If a '#' appears as the first character of a line, the whole line is
treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
The '|' character can be used to separate statements on the same
line.

File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies
9.22 M32R Dependent Features
============================
* Menu:
* M32R-Opts:: M32R Options
* M32R-Directives:: M32R Directives
* M32R-Warnings:: M32R Warnings

File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent
9.22.1 M32R Options
-------------------
The Renease M32R version of 'as' has a few machine dependent options:
'-m32rx'
'as' can assemble code for several different members of the Renesas
M32R family. Normally the default is to assemble code for the M32R
microprocessor. This option may be used to change the default to
the M32RX microprocessor, which adds some more instructions to the
basic M32R instruction set, and some additional parameters to some
of the original instructions.
'-m32r2'
This option changes the target processor to the M32R2
microprocessor.
'-m32r'
This option can be used to restore the assembler's default
behaviour of assembling for the M32R microprocessor. This can be
useful if the default has been changed by a previous command line
option.
'-little'
This option tells the assembler to produce little-endian code and
data. The default is dependent upon how the toolchain was
configured.
'-EL'
This is a synonym for _-little_.
'-big'
This option tells the assembler to produce big-endian code and
data.
'-EB'
This is a synonum for _-big_.
'-KPIC'
This option specifies that the output of the assembler should be
marked as position-independent code (PIC).
'-parallel'
This option tells the assembler to attempts to combine two
sequential instructions into a single, parallel instruction, where
it is legal to do so.
'-no-parallel'
This option disables a previously enabled _-parallel_ option.
'-no-bitinst'
This option disables the support for the extended bit-field
instructions provided by the M32R2. If this support needs to be
re-enabled the _-bitinst_ switch can be used to restore it.
'-O'
This option tells the assembler to attempt to optimize the
instructions that it produces. This includes filling delay slots
and converting sequential instructions into parallel ones. This
option implies _-parallel_.
'-warn-explicit-parallel-conflicts'
Instructs 'as' to produce warning messages when questionable
parallel instructions are encountered. This option is enabled by
default, but 'gcc' disables it when it invokes 'as' directly.
Questionable instructions are those whose behaviour would be
different if they were executed sequentially. For example the code
fragment 'mv r1, r2 || mv r3, r1' produces a different result from
'mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 and then
r2 into r1, whereas the later moves r2 into r1 and r3.
'-Wp'
This is a shorter synonym for the
_-warn-explicit-parallel-conflicts_ option.
'-no-warn-explicit-parallel-conflicts'
Instructs 'as' not to produce warning messages when questionable
parallel instructions are encountered.
'-Wnp'
This is a shorter synonym for the
_-no-warn-explicit-parallel-conflicts_ option.
'-ignore-parallel-conflicts'
This option tells the assembler's to stop checking parallel
instructions for constraint violations. This ability is provided
for hardware vendors testing chip designs and should not be used
under normal circumstances.
'-no-ignore-parallel-conflicts'
This option restores the assembler's default behaviour of checking
parallel instructions to detect constraint violations.
'-Ip'
This is a shorter synonym for the _-ignore-parallel-conflicts_
option.
'-nIp'
This is a shorter synonym for the _-no-ignore-parallel-conflicts_
option.
'-warn-unmatched-high'
This option tells the assembler to produce a warning message if a
'.high' pseudo op is encountered without a matching '.low' pseudo
op. The presence of such an unmatched pseudo op usually indicates
a programming error.
'-no-warn-unmatched-high'
Disables a previously enabled _-warn-unmatched-high_ option.
'-Wuh'
This is a shorter synonym for the _-warn-unmatched-high_ option.
'-Wnuh'
This is a shorter synonym for the _-no-warn-unmatched-high_ option.

File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent
9.22.2 M32R Directives
----------------------
The Renease M32R version of 'as' has a few architecture specific
directives:
'low EXPRESSION'
The 'low' directive computes the value of its expression and places
the lower 16-bits of the result into the immediate-field of the
instruction. For example:
or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred
'high EXPRESSION'
The 'high' directive computes the value of its expression and
places the upper 16-bits of the result into the immediate-field of
the instruction. For example:
seth r0, #high(0x12345678) ; compute r0 = 0x12340000
seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred
'shigh EXPRESSION'
The 'shigh' directive is very similar to the 'high' directive. It
also computes the value of its expression and places the upper
16-bits of the result into the immediate-field of the instruction.
The difference is that 'shigh' also checks to see if the lower
16-bits could be interpreted as a signed number, and if so it
assumes that a borrow will occur from the upper-16 bits. To
compensate for this the 'shigh' directive pre-biases the upper 16
bit value by adding one to it. For example:
For example:
seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000
seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000
In the second example the lower 16-bits are 0x8000. If these are
treated as a signed value and sign extended to 32-bits then the
value becomes 0xffff8000. If this value is then added to
0x00010000 then the result is 0x00008000.
This behaviour is to allow for the different semantics of the 'or3'
and 'add3' instructions. The 'or3' instruction treats its 16-bit
immediate argument as unsigned whereas the 'add3' treats its 16-bit
immediate as a signed value. So for example:
seth r0, #shigh(0x00008000)
add3 r0, r0, #low(0x00008000)
Produces the correct result in r0, whereas:
seth r0, #shigh(0x00008000)
or3 r0, r0, #low(0x00008000)
Stores 0xffff8000 into r0.
Note - the 'shigh' directive does not know where in the assembly
source code the lower 16-bits of the value are going set, so it
cannot check to make sure that an 'or3' instruction is being used
rather than an 'add3' instruction. It is up to the programmer to
make sure that correct directives are used.
'.m32r'
The directive performs a similar thing as the _-m32r_ command line
option. It tells the assembler to only accept M32R instructions
from now on. An instructions from later M32R architectures are
refused.
'.m32rx'
The directive performs a similar thing as the _-m32rx_ command line
option. It tells the assembler to start accepting the extra
instructions in the M32RX ISA as well as the ordinary M32R ISA.
'.m32r2'
The directive performs a similar thing as the _-m32r2_ command line
option. It tells the assembler to start accepting the extra
instructions in the M32R2 ISA as well as the ordinary M32R ISA.
'.little'
The directive performs a similar thing as the _-little_ command
line option. It tells the assembler to start producing
little-endian code and data. This option should be used with care
as producing mixed-endian binary files is fraught with danger.
'.big'
The directive performs a similar thing as the _-big_ command line
option. It tells the assembler to start producing big-endian code
and data. This option should be used with care as producing
mixed-endian binary files is fraught with danger.

File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent
9.22.3 M32R Warnings
--------------------
There are several warning and error messages that can be produced by
'as' which are specific to the M32R:
'output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?'
This message is only produced if warnings for explicit parallel
conflicts have been enabled. It indicates that the assembler has
encountered a parallel instruction in which the destination
register of the left hand instruction is used as an input register
in the right hand instruction. For example in this code fragment
'mv r1, r2 || neg r3, r1' register r1 is the destination of the
move instruction and the input to the neg instruction.
'output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?'
This message is only produced if warnings for explicit parallel
conflicts have been enabled. It indicates that the assembler has
encountered a parallel instruction in which the destination
register of the right hand instruction is used as an input register
in the left hand instruction. For example in this code fragment
'mv r1, r2 || neg r2, r3' register r2 is the destination of the neg
instruction and the input to the move instruction.
'instruction '...' is for the M32RX only'
This message is produced when the assembler encounters an
instruction which is only supported by the M32Rx processor, and the
'-m32rx' command line flag has not been specified to allow assembly
of such instructions.
'unknown instruction '...''
This message is produced when the assembler encounters an
instruction which it does not recognize.
'only the NOP instruction can be issued in parallel on the m32r'
This message is produced when the assembler encounters a parallel
instruction which does not involve a NOP instruction and the
'-m32rx' command line flag has not been specified. Only the M32Rx
processor is able to execute two instructions in parallel.
'instruction '...' cannot be executed in parallel.'
This message is produced when the assembler encounters a parallel
instruction which is made up of one or two instructions which
cannot be executed in parallel.
'Instructions share the same execution pipeline'
This message is produced when the assembler encounters a parallel
instruction whoes components both use the same execution pipeline.
'Instructions write to the same destination register.'
This message is produced when the assembler encounters a parallel
instruction where both components attempt to modify the same
register. For example these code fragments will produce this
message: 'mv r1, r2 || neg r1, r3' 'jl r0 || mv r14, r1' 'st r2,
@-r1 || mv r1, r3' 'mv r1, r2 || ld r0, @r1+' 'cmp r1, r2 || addx
r3, r4' (Both write to the condition bit)

File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies
9.23 M680x0 Dependent Features
==============================
* Menu:
* M68K-Opts:: M680x0 Options
* M68K-Syntax:: Syntax
* M68K-Moto-Syntax:: Motorola Syntax
* M68K-Float:: Floating Point
* M68K-Directives:: 680x0 Machine Directives
* M68K-opcodes:: Opcodes

File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent
9.23.1 M680x0 Options
---------------------
The Motorola 680x0 version of 'as' has a few machine dependent options:
'-march=ARCHITECTURE'
This option specifies a target architecture. The following
architectures are recognized: '68000', '68010', '68020', '68030',
'68040', '68060', 'cpu32', 'isaa', 'isaaplus', 'isab', 'isac' and
'cfv4e'.
'-mcpu=CPU'
This option specifies a target cpu. When used in conjunction with
the '-march' option, the cpu must be within the specified
architecture. Also, the generic features of the architecture are
used for instruction generation, rather than those of the specific
chip.
'-m[no-]68851'
'-m[no-]68881'
'-m[no-]div'
'-m[no-]usp'
'-m[no-]float'
'-m[no-]mac'
'-m[no-]emac'
Enable or disable various architecture specific features. If a
chip or architecture by default supports an option (for instance
'-march=isaaplus' includes the '-mdiv' option), explicitly
disabling the option will override the default.
'-l'
You can use the '-l' option to shorten the size of references to
undefined symbols. If you do not use the '-l' option, references
to undefined symbols are wide enough for a full 'long' (32 bits).
(Since 'as' cannot know where these symbols end up, 'as' can only
allocate space for the linker to fill in later. Since 'as' does
not know how far away these symbols are, it allocates as much space
as it can.) If you use this option, the references are only one
word wide (16 bits). This may be useful if you want the object
file to be as small as possible, and you know that the relevant
symbols are always less than 17 bits away.
'--register-prefix-optional'
For some configurations, especially those where the compiler
normally does not prepend an underscore to the names of user
variables, the assembler requires a '%' before any use of a
register name. This is intended to let the assembler distinguish
between C variables and functions named 'a0' through 'a7', and so
on. The '%' is always accepted, but is not required for certain
configurations, notably 'sun3'. The '--register-prefix-optional'
option may be used to permit omitting the '%' even for
configurations for which it is normally required. If this is done,
it will generally be impossible to refer to C variables and
functions with the same names as register names.
'--bitwise-or'
Normally the character '|' is treated as a comment character, which
means that it can not be used in expressions. The '--bitwise-or'
option turns '|' into a normal character. In this mode, you must
either use C style comments, or start comments with a '#' character
at the beginning of a line.
'--base-size-default-16 --base-size-default-32'
If you use an addressing mode with a base register without
specifying the size, 'as' will normally use the full 32 bit value.
For example, the addressing mode '%a0@(%d0)' is equivalent to
'%a0@(%d0:l)'. You may use the '--base-size-default-16' option to
tell 'as' to default to using the 16 bit value. In this case,
'%a0@(%d0)' is equivalent to '%a0@(%d0:w)'. You may use the
'--base-size-default-32' option to restore the default behaviour.
'--disp-size-default-16 --disp-size-default-32'
If you use an addressing mode with a displacement, and the value of
the displacement is not known, 'as' will normally assume that the
value is 32 bits. For example, if the symbol 'disp' has not been
defined, 'as' will assemble the addressing mode '%a0@(disp,%d0)' as
though 'disp' is a 32 bit value. You may use the
'--disp-size-default-16' option to tell 'as' to instead assume that
the displacement is 16 bits. In this case, 'as' will assemble
'%a0@(disp,%d0)' as though 'disp' is a 16 bit value. You may use
the '--disp-size-default-32' option to restore the default
behaviour.
'--pcrel'
Always keep branches PC-relative. In the M680x0 architecture all
branches are defined as PC-relative. However, on some processors
they are limited to word displacements maximum. When 'as' needs a
long branch that is not available, it normally emits an absolute
jump instead. This option disables this substitution. When this
option is given and no long branches are available, only word
branches will be emitted. An error message will be generated if a
word branch cannot reach its target. This option has no effect on
68020 and other processors that have long branches. *note Branch
Improvement: M68K-Branch.
'-m68000'
'as' can assemble code for several different members of the
Motorola 680x0 family. The default depends upon how 'as' was
configured when it was built; normally, the default is to assemble
code for the 68020 microprocessor. The following options may be
used to change the default. These options control which
instructions and addressing modes are permitted. The members of
the 680x0 family are very similar. For detailed information about
the differences, see the Motorola manuals.
'-m68000'
'-m68ec000'
'-m68hc000'
'-m68hc001'
'-m68008'
'-m68302'
'-m68306'
'-m68307'
'-m68322'
'-m68356'
Assemble for the 68000. '-m68008', '-m68302', and so on are
synonyms for '-m68000', since the chips are the same from the
point of view of the assembler.
'-m68010'
Assemble for the 68010.
'-m68020'
'-m68ec020'
Assemble for the 68020. This is normally the default.
'-m68030'
'-m68ec030'
Assemble for the 68030.
'-m68040'
'-m68ec040'
Assemble for the 68040.
'-m68060'
'-m68ec060'
Assemble for the 68060.
'-mcpu32'
'-m68330'
'-m68331'
'-m68332'
'-m68333'
'-m68334'
'-m68336'
'-m68340'
'-m68341'
'-m68349'
'-m68360'
Assemble for the CPU32 family of chips.
'-m5200'
'-m5202'
'-m5204'
'-m5206'
'-m5206e'
'-m521x'
'-m5249'
'-m528x'
'-m5307'
'-m5407'
'-m547x'
'-m548x'
'-mcfv4'
'-mcfv4e'
Assemble for the ColdFire family of chips.
'-m68881'
'-m68882'
Assemble 68881 floating point instructions. This is the
default for the 68020, 68030, and the CPU32. The 68040 and
68060 always support floating point instructions.
'-mno-68881'
Do not assemble 68881 floating point instructions. This is
the default for 68000 and the 68010. The 68040 and 68060
always support floating point instructions, even if this
option is used.
'-m68851'
Assemble 68851 MMU instructions. This is the default for the
68020, 68030, and 68060. The 68040 accepts a somewhat
different set of MMU instructions; '-m68851' and '-m68040'
should not be used together.
'-mno-68851'
Do not assemble 68851 MMU instructions. This is the default
for the 68000, 68010, and the CPU32. The 68040 accepts a
somewhat different set of MMU instructions.

File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent
9.23.2 Syntax
-------------
This syntax for the Motorola 680x0 was developed at MIT.
The 680x0 version of 'as' uses instructions names and syntax
compatible with the Sun assembler. Intervening periods are ignored; for
example, 'movl' is equivalent to 'mov.l'.
In the following table APC stands for any of the address registers
('%a0' through '%a7'), the program counter ('%pc'), the zero-address
relative to the program counter ('%zpc'), a suppressed address register
('%za0' through '%za7'), or it may be omitted entirely. The use of SIZE
means one of 'w' or 'l', and it may be omitted, along with the leading
colon, unless a scale is also specified. The use of SCALE means one of
'1', '2', '4', or '8', and it may always be omitted along with the
leading colon.
The following addressing modes are understood:
"Immediate"
'#NUMBER'
"Data Register"
'%d0' through '%d7'
"Address Register"
'%a0' through '%a7'
'%a7' is also known as '%sp', i.e., the Stack Pointer. '%a6' is
also known as '%fp', the Frame Pointer.
"Address Register Indirect"
'%a0@' through '%a7@'
"Address Register Postincrement"
'%a0@+' through '%a7@+'
"Address Register Predecrement"
'%a0@-' through '%a7@-'
"Indirect Plus Offset"
'APC@(NUMBER)'
"Index"
'APC@(NUMBER,REGISTER:SIZE:SCALE)'
The NUMBER may be omitted.
"Postindex"
'APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)'
The ONUMBER or the REGISTER, but not both, may be omitted.
"Preindex"
'APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)'
The NUMBER may be omitted. Omitting the REGISTER produces the
Postindex addressing mode.
"Absolute"
'SYMBOL', or 'DIGITS', optionally followed by ':b', ':w', or ':l'.

File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent
9.23.3 Motorola Syntax
----------------------
The standard Motorola syntax for this chip differs from the syntax
already discussed (*note Syntax: M68K-Syntax.). 'as' can accept
Motorola syntax for operands, even if MIT syntax is used for other
operands in the same instruction. The two kinds of syntax are fully
compatible.
In the following table APC stands for any of the address registers
('%a0' through '%a7'), the program counter ('%pc'), the zero-address
relative to the program counter ('%zpc'), or a suppressed address
register ('%za0' through '%za7'). The use of SIZE means one of 'w' or
'l', and it may always be omitted along with the leading dot. The use
of SCALE means one of '1', '2', '4', or '8', and it may always be
omitted along with the leading asterisk.
The following additional addressing modes are understood:
"Address Register Indirect"
'(%a0)' through '(%a7)'
'%a7' is also known as '%sp', i.e., the Stack Pointer. '%a6' is
also known as '%fp', the Frame Pointer.
"Address Register Postincrement"
'(%a0)+' through '(%a7)+'
"Address Register Predecrement"
'-(%a0)' through '-(%a7)'
"Indirect Plus Offset"
'NUMBER(%A0)' through 'NUMBER(%A7)', or 'NUMBER(%PC)'.
The NUMBER may also appear within the parentheses, as in
'(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted
(with an address register, omitting the NUMBER produces Address
Register Indirect mode).
"Index"
'NUMBER(APC,REGISTER.SIZE*SCALE)'
The NUMBER may be omitted, or it may appear within the parentheses.
The APC may be omitted. The REGISTER and the APC may appear in
either order. If both APC and REGISTER are address registers, and
the SIZE and SCALE are omitted, then the first register is taken as
the base register, and the second as the index register.
"Postindex"
'([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)'
The ONUMBER, or the REGISTER, or both, may be omitted. Either the
NUMBER or the APC may be omitted, but not both.
"Preindex"
'([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)'
The NUMBER, or the APC, or the REGISTER, or any two of them, may be
omitted. The ONUMBER may be omitted. The REGISTER and the APC may
appear in either order. If both APC and REGISTER are address
registers, and the SIZE and SCALE are omitted, then the first
register is taken as the base register, and the second as the index
register.

File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent
9.23.4 Floating Point
---------------------
Packed decimal (P) format floating literals are not supported. Feel
free to add the code!
The floating point formats generated by directives are these.
'.float'
'Single' precision floating point constants.
'.double'
'Double' precision floating point constants.
'.extend'
'.ldouble'
'Extended' precision ('long double') floating point constants.

File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent
9.23.5 680x0 Machine Directives
-------------------------------
In order to be compatible with the Sun assembler the 680x0 assembler
understands the following directives.
'.data1'
This directive is identical to a '.data 1' directive.
'.data2'
This directive is identical to a '.data 2' directive.
'.even'
This directive is a special case of the '.align' directive; it
aligns the output to an even byte boundary.
'.skip'
This directive is identical to a '.space' directive.
'.arch NAME'
Select the target architecture and extension features. Valid
values for NAME are the same as for the '-march' command line
option. This directive cannot be specified after any instructions
have been assembled. If it is given multiple times, or in
conjunction with the '-march' option, all uses must be for the same
architecture and extension set.
'.cpu NAME'
Select the target cpu. Valid valuse for NAME are the same as for
the '-mcpu' command line option. This directive cannot be
specified after any instructions have been assembled. If it is
given multiple times, or in conjunction with the '-mopt' option,
all uses must be for the same cpu.

File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent
9.23.6 Opcodes
--------------
* Menu:
* M68K-Branch:: Branch Improvement
* M68K-Chars:: Special Characters

File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes
9.23.6.1 Branch Improvement
...........................
Certain pseudo opcodes are permitted for branch instructions. They
expand to the shortest branch instruction that reach the target.
Generally these mnemonics are made by substituting 'j' for 'b' at the
start of a Motorola mnemonic.
The following table summarizes the pseudo-operations. A '*' flags
cases that are more fully described after the table:
Displacement
+------------------------------------------------------------
| 68020 68000/10, not PC-relative OK
Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP **
+------------------------------------------------------------
jbsr |bsrs bsrw bsrl jsr
jra |bras braw bral jmp
* jXX |bXXs bXXw bXXl bNXs;jmp
* dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp
fjXX | N/A fbXXw fbXXl N/A
XX: condition
NX: negative of condition XX
'*'--see full description below
'**'--this expansion mode is disallowed by '--pcrel'
'jbsr'
'jra'
These are the simplest jump pseudo-operations; they always map to
one particular machine instruction, depending on the displacement
to the branch target. This instruction will be a byte or word
branch is that is sufficient. Otherwise, a long branch will be
emitted if available. If no long branches are available and the
'--pcrel' option is not given, an absolute long jump will be
emitted instead. If no long branches are available, the '--pcrel'
option is given, and a word branch cannot reach the target, an
error message is generated.
In addition to standard branch operands, 'as' allows these
pseudo-operations to have all operands that are allowed for jsr and
jmp, substituting these instructions if the operand given is not
valid for a branch instruction.
'jXX'
Here, 'jXX' stands for an entire family of pseudo-operations, where
XX is a conditional branch or condition-code test. The full list
of pseudo-ops in this family is:
jhi jls jcc jcs jne jeq jvc
jvs jpl jmi jge jlt jgt jle
Usually, each of these pseudo-operations expands to a single branch
instruction. However, if a word branch is not sufficient, no long
branches are available, and the '--pcrel' option is not given, 'as'
issues a longer code fragment in terms of NX, the opposite
condition to XX. For example, under these conditions:
jXX foo
gives
bNXs oof
jmp foo
oof:
'dbXX'
The full family of pseudo-operations covered here is
dbhi dbls dbcc dbcs dbne dbeq dbvc
dbvs dbpl dbmi dbge dblt dbgt dble
dbf dbra dbt
Motorola 'dbXX' instructions allow word displacements only. When a
word displacement is sufficient, each of these pseudo-operations
expands to the corresponding Motorola instruction. When a word
displacement is not sufficient and long branches are available,
when the source reads 'dbXX foo', 'as' emits
dbXX oo1
bras oo2
oo1:bral foo
oo2:
If, however, long branches are not available and the '--pcrel'
option is not given, 'as' emits
dbXX oo1
bras oo2
oo1:jmp foo
oo2:
'fjXX'
This family includes
fjne fjeq fjge fjlt fjgt fjle fjf
fjt fjgl fjgle fjnge fjngl fjngle fjngt
fjnle fjnlt fjoge fjogl fjogt fjole fjolt
fjor fjseq fjsf fjsne fjst fjueq fjuge
fjugt fjule fjult fjun
Each of these pseudo-operations always expands to a single Motorola
coprocessor branch instruction, word or long. All Motorola
coprocessor branch instructions allow both word and long
displacements.

File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes
9.23.6.2 Special Characters
...........................
Line comments are introduced by the '|' character appearing anywhere on
a line, unless the '--bitwise-or' command line option has been
specified.
An asterisk ('*') as the first character on a line marks the start of
a line comment as well.
A hash character ('#') as the first character on a line also marks
the start of a line comment, but in this case it could also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::). If the hash character appears
elsewhere on a line it is used to introduce an immediate value. (This
is for compatibility with Sun's assembler).
Multiple statements on the same line can appear if they are separated
by the ';' character.

File: as.info, Node: M68HC11-Dependent, Next: Meta-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies
9.24 M68HC11 and M68HC12 Dependent Features
===========================================
* Menu:
* M68HC11-Opts:: M68HC11 and M68HC12 Options
* M68HC11-Syntax:: Syntax
* M68HC11-Modifiers:: Symbolic Operand Modifiers
* M68HC11-Directives:: Assembler Directives
* M68HC11-Float:: Floating Point
* M68HC11-opcodes:: Opcodes

File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent
9.24.1 M68HC11 and M68HC12 Options
----------------------------------
The Motorola 68HC11 and 68HC12 version of 'as' have a few machine
dependent options.
'-m68hc11'
This option switches the assembler into the M68HC11 mode. In this
mode, the assembler only accepts 68HC11 operands and mnemonics. It
produces code for the 68HC11.
'-m68hc12'
This option switches the assembler into the M68HC12 mode. In this
mode, the assembler also accepts 68HC12 operands and mnemonics. It
produces code for the 68HC12. A few 68HC11 instructions are
replaced by some 68HC12 instructions as recommended by Motorola
specifications.
'-m68hcs12'
This option switches the assembler into the M68HCS12 mode. This
mode is similar to '-m68hc12' but specifies to assemble for the
68HCS12 series. The only difference is on the assembling of the
'movb' and 'movw' instruction when a PC-relative operand is used.
'-mm9s12x'
This option switches the assembler into the M9S12X mode. This mode
is similar to '-m68hc12' but specifies to assemble for the S12X
series which is a superset of the HCS12.
'-mm9s12xg'
This option switches the assembler into the XGATE mode for the RISC
co-processor featured on some S12X-family chips.
'--xgate-ramoffset'
This option instructs the linker to offset RAM addresses from S12X
address space into XGATE address space.
'-mshort'
This option controls the ABI and indicates to use a 16-bit integer
ABI. It has no effect on the assembled instructions. This is the
default.
'-mlong'
This option controls the ABI and indicates to use a 32-bit integer
ABI.
'-mshort-double'
This option controls the ABI and indicates to use a 32-bit float
ABI. This is the default.
'-mlong-double'
This option controls the ABI and indicates to use a 64-bit float
ABI.
'--strict-direct-mode'
You can use the '--strict-direct-mode' option to disable the
automatic translation of direct page mode addressing into extended
mode when the instruction does not support direct mode. For
example, the 'clr' instruction does not support direct page mode
addressing. When it is used with the direct page mode, 'as' will
ignore it and generate an absolute addressing. This option
prevents 'as' from doing this, and the wrong usage of the direct
page mode will raise an error.
'--short-branches'
The '--short-branches' option turns off the translation of relative
branches into absolute branches when the branch offset is out of
range. By default 'as' transforms the relative branch ('bsr',
'bgt', 'bge', 'beq', 'bne', 'ble', 'blt', 'bhi', 'bcc', 'bls',
'bcs', 'bmi', 'bvs', 'bvs', 'bra') into an absolute branch when the
offset is out of the -128 .. 127 range. In that case, the 'bsr'
instruction is translated into a 'jsr', the 'bra' instruction is
translated into a 'jmp' and the conditional branches instructions
are inverted and followed by a 'jmp'. This option disables these
translations and 'as' will generate an error if a relative branch
is out of range. This option does not affect the optimization
associated to the 'jbra', 'jbsr' and 'jbXX' pseudo opcodes.
'--force-long-branches'
The '--force-long-branches' option forces the translation of
relative branches into absolute branches. This option does not
affect the optimization associated to the 'jbra', 'jbsr' and 'jbXX'
pseudo opcodes.
'--print-insn-syntax'
You can use the '--print-insn-syntax' option to obtain the syntax
description of the instruction when an error is detected.
'--print-opcodes'
The '--print-opcodes' option prints the list of all the
instructions with their syntax. The first item of each line
represents the instruction name and the rest of the line indicates
the possible operands for that instruction. The list is printed in
alphabetical order. Once the list is printed 'as' exits.
'--generate-example'
The '--generate-example' option is similar to '--print-opcodes' but
it generates an example for each instruction instead.

File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent
9.24.2 Syntax
-------------
In the M68HC11 syntax, the instruction name comes first and it may be
followed by one or several operands (up to three). Operands are
separated by comma (','). In the normal mode, 'as' will complain if too
many operands are specified for a given instruction. In the MRI mode
(turned on with '-M' option), it will treat them as comments. Example:
inx
lda #23
bset 2,x #4
brclr *bot #8 foo
The presence of a ';' character or a '!' character anywhere on a line
indicates the start of a comment that extends to the end of that line.
A '*' or a '#' character at the start of a line also introduces a
line comment, but these characters do not work elsewhere on the line.
If the first character of the line is a '#' then as well as starting a
comment, the line could also be logical line number directive (*note
Comments::) or a preprocessor control command (*note Preprocessing::).
The M68HC11 assembler does not currently support a line separator
character.
The following addressing modes are understood for 68HC11 and 68HC12:
"Immediate"
'#NUMBER'
"Address Register"
'NUMBER,X', 'NUMBER,Y'
The NUMBER may be omitted in which case 0 is assumed.
"Direct Addressing mode"
'*SYMBOL', or '*DIGITS'
"Absolute"
'SYMBOL', or 'DIGITS'
The M68HC12 has other more complex addressing modes. All of them are
supported and they are represented below:
"Constant Offset Indexed Addressing Mode"
'NUMBER,REG'
The NUMBER may be omitted in which case 0 is assumed. The register
can be either 'X', 'Y', 'SP' or 'PC'. The assembler will use the
smaller post-byte definition according to the constant value (5-bit
constant offset, 9-bit constant offset or 16-bit constant offset).
If the constant is not known by the assembler it will use the
16-bit constant offset post-byte and the value will be resolved at
link time.
"Offset Indexed Indirect"
'[NUMBER,REG]'
The register can be either 'X', 'Y', 'SP' or 'PC'.
"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement"
'NUMBER,-REG' 'NUMBER,+REG' 'NUMBER,REG-' 'NUMBER,REG+'
The number must be in the range '-8'..'+8' and must not be 0. The
register can be either 'X', 'Y', 'SP' or 'PC'.
"Accumulator Offset"
'ACC,REG'
The accumulator register can be either 'A', 'B' or 'D'. The
register can be either 'X', 'Y', 'SP' or 'PC'.
"Accumulator D offset indexed-indirect"
'[D,REG]'
The register can be either 'X', 'Y', 'SP' or 'PC'.
For example:
ldab 1024,sp
ldd [10,x]
orab 3,+x
stab -2,y-
ldx a,pc
sty [d,sp]

File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent
9.24.3 Symbolic Operand Modifiers
---------------------------------
The assembler supports several modifiers when using symbol addresses in
68HC11 and 68HC12 instruction operands. The general syntax is the
following:
%modifier(symbol)
'%addr'
This modifier indicates to the assembler and linker to use the
16-bit physical address corresponding to the symbol. This is
intended to be used on memory window systems to map a symbol in the
memory bank window. If the symbol is in a memory expansion part,
the physical address corresponds to the symbol address within the
memory bank window. If the symbol is not in a memory expansion
part, this is the symbol address (using or not using the %addr
modifier has no effect in that case).
'%page'
This modifier indicates to use the memory page number corresponding
to the symbol. If the symbol is in a memory expansion part, its
page number is computed by the linker as a number used to map the
page containing the symbol in the memory bank window. If the
symbol is not in a memory expansion part, the page number is 0.
'%hi'
This modifier indicates to use the 8-bit high part of the physical
address of the symbol.
'%lo'
This modifier indicates to use the 8-bit low part of the physical
address of the symbol.
For example a 68HC12 call to a function 'foo_example' stored in
memory expansion part could be written as follows:
call %addr(foo_example),%page(foo_example)
and this is equivalent to
call foo_example
And for 68HC11 it could be written as follows:
ldab #%page(foo_example)
stab _page_switch
jsr %addr(foo_example)

File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent
9.24.4 Assembler Directives
---------------------------
The 68HC11 and 68HC12 version of 'as' have the following specific
assembler directives:
'.relax'
The relax directive is used by the 'GNU Compiler' to emit a
specific relocation to mark a group of instructions for linker
relaxation. The sequence of instructions within the group must be
known to the linker so that relaxation can be performed.
'.mode [mshort|mlong|mshort-double|mlong-double]'
This directive specifies the ABI. It overrides the '-mshort',
'-mlong', '-mshort-double' and '-mlong-double' options.
'.far SYMBOL'
This directive marks the symbol as a 'far' symbol meaning that it
uses a 'call/rtc' calling convention as opposed to 'jsr/rts'.
During a final link, the linker will identify references to the
'far' symbol and will verify the proper calling convention.
'.interrupt SYMBOL'
This directive marks the symbol as an interrupt entry point. This
information is then used by the debugger to correctly unwind the
frame across interrupts.
'.xrefb SYMBOL'
This directive is defined for compatibility with the 'Specification
for Motorola 8 and 16-Bit Assembly Language Input Standard' and is
ignored.

File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent
9.24.5 Floating Point
---------------------
Packed decimal (P) format floating literals are not supported. Feel
free to add the code!
The floating point formats generated by directives are these.
'.float'
'Single' precision floating point constants.
'.double'
'Double' precision floating point constants.
'.extend'
'.ldouble'
'Extended' precision ('long double') floating point constants.

File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent
9.24.6 Opcodes
--------------
* Menu:
* M68HC11-Branch:: Branch Improvement

File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes
9.24.6.1 Branch Improvement
...........................
Certain pseudo opcodes are permitted for branch instructions. They
expand to the shortest branch instruction that reach the target.
Generally these mnemonics are made by prepending 'j' to the start of
Motorola mnemonic. These pseudo opcodes are not affected by the
'--short-branches' or '--force-long-branches' options.
The following table summarizes the pseudo-operations.
Displacement Width
+-------------------------------------------------------------+
| Options |
| --short-branches --force-long-branches |
+--------------------------+----------------------------------+
Op |BYTE WORD | BYTE WORD |
+--------------------------+----------------------------------+
bsr | bsr <pc-rel> <error> | jsr <abs> |
bra | bra <pc-rel> <error> | jmp <abs> |
jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> |
jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> |
bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> |
jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> |
| jmp <abs> | |
+--------------------------+----------------------------------+
XX: condition
NX: negative of condition XX
'jbsr'
'jbra'
These are the simplest jump pseudo-operations; they always map to
one particular machine instruction, depending on the displacement
to the branch target.
'jbXX'
Here, 'jbXX' stands for an entire family of pseudo-operations,
where XX is a conditional branch or condition-code test. The full
list of pseudo-ops in this family is:
jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo
jbcs jbne jblt jble jbls jbvc jbmi
For the cases of non-PC relative displacements and long
displacements, 'as' issues a longer code fragment in terms of NX,
the opposite condition to XX. For example, for the non-PC relative
case:
jbXX foo
gives
bNXs oof
jmp foo
oof:

File: as.info, Node: Meta-Dependent, Next: MicroBlaze-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies
9.25 Meta Dependent Features
============================
* Menu:
* Meta Options:: Options
* Meta Syntax:: Meta Assembler Syntax

File: as.info, Node: Meta Options, Next: Meta Syntax, Up: Meta-Dependent
9.25.1 Options
--------------
The Imagination Technologies Meta architecture is implemented in a
number of versions, with each new version adding new features such as
instructions and registers. For precise details of what instructions
each core supports, please see the chip's technical reference manual.
The following table lists all available Meta options.
'-mcpu=metac11'
Generate code for Meta 1.1.
'-mcpu=metac12'
Generate code for Meta 1.2.
'-mcpu=metac21'
Generate code for Meta 2.1.
'-mfpu=metac21'
Allow code to use FPU hardware of Meta 2.1.

File: as.info, Node: Meta Syntax, Prev: Meta Options, Up: Meta-Dependent
9.25.2 Syntax
-------------
* Menu:
* Meta-Chars:: Special Characters
* Meta-Regs:: Register Names

File: as.info, Node: Meta-Chars, Next: Meta-Regs, Up: Meta Syntax
9.25.2.1 Special Characters
...........................
'!' is the line comment character.
You can use ';' instead of a newline to separate statements.
Since '$' has no special meaning, you may use it in symbol names.

File: as.info, Node: Meta-Regs, Prev: Meta-Chars, Up: Meta Syntax
9.25.2.2 Register Names
.......................
Registers can be specified either using their mnemonic names, such as
'D0Re0', or using the unit plus register number separated by a '.', such
as 'D0.0'.

File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: Meta-Dependent, Up: Machine Dependencies
9.26 MicroBlaze Dependent Features
==================================
The Xilinx MicroBlaze processor family includes several variants, all
using the same core instruction set. This chapter covers features of
the GNU assembler that are specific to the MicroBlaze architecture. For
details about the MicroBlaze instruction set, please see the 'MicroBlaze
Processor Reference Guide (UG081)' available at www.xilinx.com.
* Menu:
* MicroBlaze Directives:: Directives for MicroBlaze Processors.
* MicroBlaze Syntax:: Syntax for the MicroBlaze

File: as.info, Node: MicroBlaze Directives, Next: MicroBlaze Syntax, Up: MicroBlaze-Dependent
9.26.1 Directives
-----------------
A number of assembler directives are available for MicroBlaze.
'.data8 EXPRESSION,...'
This directive is an alias for '.byte'. Each expression is
assembled into an eight-bit value.
'.data16 EXPRESSION,...'
This directive is an alias for '.hword'. Each expression is
assembled into an 16-bit value.
'.data32 EXPRESSION,...'
This directive is an alias for '.word'. Each expression is
assembled into an 32-bit value.
'.ent NAME[,LABEL]'
This directive is an alias for '.func' denoting the start of
function NAME at (optional) LABEL.
'.end NAME[,LABEL]'
This directive is an alias for '.endfunc' denoting the end of
function NAME.
'.gpword LABEL,...'
This directive is an alias for '.rva'. The resolved address of
LABEL is stored in the data section.
'.weakext LABEL'
Declare that LABEL is a weak external symbol.
'.rodata'
Switch to .rodata section. Equivalent to '.section .rodata'
'.sdata2'
Switch to .sdata2 section. Equivalent to '.section .sdata2'
'.sdata'
Switch to .sdata section. Equivalent to '.section .sdata'
'.bss'
Switch to .bss section. Equivalent to '.section .bss'
'.sbss'
Switch to .sbss section. Equivalent to '.section .sbss'

File: as.info, Node: MicroBlaze Syntax, Prev: MicroBlaze Directives, Up: MicroBlaze-Dependent
9.26.2 Syntax for the MicroBlaze
--------------------------------
* Menu:
* MicroBlaze-Chars:: Special Characters

File: as.info, Node: MicroBlaze-Chars, Up: MicroBlaze Syntax
9.26.2.1 Special Characters
...........................
The presence of a '#' on a line indicates the start of a comment that
extends to the end of the current line.
If a '#' appears as the first character of a line, the whole line is
treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
The ';' character can be used to separate statements on the same
line.

File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies
9.27 MIPS Dependent Features
============================
GNU 'as' for MIPS architectures supports several different MIPS
processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For
information about the MIPS instruction set, see 'MIPS RISC
Architecture', by Kane and Heindrich (Prentice-Hall). For an overview
of MIPS assembly conventions, see "Appendix D: Assembly Language
Programming" in the same work.
* Menu:
* MIPS Options:: Assembler options
* MIPS Macros:: High-level assembly macros
* MIPS Symbol Sizes:: Directives to override the size of symbols
* MIPS Small Data:: Controlling the use of small data accesses
* MIPS ISA:: Directives to override the ISA level
* MIPS assembly options:: Directives to control code generation
* MIPS autoextend:: Directives for extending MIPS 16 bit instructions
* MIPS insn:: Directive to mark data as an instruction
* MIPS FP ABIs:: Marking which FP ABI is in use
* MIPS NaN Encodings:: Directives to record which NaN encoding is being used
* MIPS Option Stack:: Directives to save and restore options
* MIPS ASE Instruction Generation Overrides:: Directives to control
generation of MIPS ASE instructions
* MIPS Floating-Point:: Directives to override floating-point options
* MIPS Syntax:: MIPS specific syntactical considerations

File: as.info, Node: MIPS Options, Next: MIPS Macros, Up: MIPS-Dependent
9.27.1 Assembler options
------------------------
The MIPS configurations of GNU 'as' support these special options:
'-G NUM'
Set the "small data" limit to N bytes. The default limit is 8
bytes. *Note Controlling the use of small data accesses: MIPS
Small Data.
'-EB'
'-EL'
Any MIPS configuration of 'as' can select big-endian or
little-endian output at run time (unlike the other GNU development
tools, which must be configured for one or the other). Use '-EB'
to select big-endian output, and '-EL' for little-endian.
'-KPIC'
Generate SVR4-style PIC. This option tells the assembler to
generate SVR4-style position-independent macro expansions. It also
tells the assembler to mark the output file as PIC.
'-mvxworks-pic'
Generate VxWorks PIC. This option tells the assembler to generate
VxWorks-style position-independent macro expansions.
'-mips1'
'-mips2'
'-mips3'
'-mips4'
'-mips5'
'-mips32'
'-mips32r2'
'-mips32r3'
'-mips32r5'
'-mips32r6'
'-mips64'
'-mips64r2'
'-mips64r3'
'-mips64r5'
'-mips64r6'
Generate code for a particular MIPS Instruction Set Architecture
level. '-mips1' corresponds to the R2000 and R3000 processors,
'-mips2' to the R6000 processor, '-mips3' to the R4000 processor,
and '-mips4' to the R8000 and R10000 processors. '-mips5',
'-mips32', '-mips32r2', '-mips32r3', '-mips32r5', '-mips32r6',
'-mips64', '-mips64r2', '-mips64r3', '-mips64r5', and '-mips64r6'
correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32
Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, and MIPS64
Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6
ISA processors, respectively. You can also switch instruction sets
during the assembly; see *note Directives to override the ISA
level: MIPS ISA.
'-mgp32'
'-mfp32'
Some macros have different expansions for 32-bit and 64-bit
registers. The register sizes are normally inferred from the ISA
and ABI, but these flags force a certain group of registers to be
treated as 32 bits wide at all times. '-mgp32' controls the size
of general-purpose registers and '-mfp32' controls the size of
floating-point registers.
The '.set gp=32' and '.set fp=32' directives allow the size of
registers to be changed for parts of an object. The default value
is restored by '.set gp=default' and '.set fp=default'.
On some MIPS variants there is a 32-bit mode flag; when this flag
is set, 64-bit instructions generate a trap. Also, some 32-bit
OSes only save the 32-bit registers on a context switch, so it is
essential never to use the 64-bit registers.
'-mgp64'
'-mfp64'
Assume that 64-bit registers are available. This is provided in
the interests of symmetry with '-mgp32' and '-mfp32'.
The '.set gp=64' and '.set fp=64' directives allow the size of
registers to be changed for parts of an object. The default value
is restored by '.set gp=default' and '.set fp=default'.
'-mfpxx'
Make no assumptions about whether 32-bit or 64-bit floating-point
registers are available. This is provided to support having
modules compatible with either '-mfp32' or '-mfp64'. This option
can only be used with MIPS II and above.
The '.set fp=xx' directive allows a part of an object to be marked
as not making assumptions about 32-bit or 64-bit FP registers. The
default value is restored by '.set fp=default'.
'-modd-spreg'
'-mno-odd-spreg'
Enable use of floating-point operations on odd-numbered
single-precision registers when supported by the ISA. '-mfpxx'
implies '-mno-odd-spreg', otherwise the default is '-modd-spreg'
'-mips16'
'-no-mips16'
Generate code for the MIPS 16 processor. This is equivalent to
putting '.set mips16' at the start of the assembly file.
'-no-mips16' turns off this option.
'-mmicromips'
'-mno-micromips'
Generate code for the microMIPS processor. This is equivalent to
putting '.set micromips' at the start of the assembly file.
'-mno-micromips' turns off this option. This is equivalent to
putting '.set nomicromips' at the start of the assembly file.
'-msmartmips'
'-mno-smartmips'
Enables the SmartMIPS extensions to the MIPS32 instruction set,
which provides a number of new instructions which target smartcard
and cryptographic applications. This is equivalent to putting
'.set smartmips' at the start of the assembly file.
'-mno-smartmips' turns off this option.
'-mips3d'
'-no-mips3d'
Generate code for the MIPS-3D Application Specific Extension. This
tells the assembler to accept MIPS-3D instructions. '-no-mips3d'
turns off this option.
'-mdmx'
'-no-mdmx'
Generate code for the MDMX Application Specific Extension. This
tells the assembler to accept MDMX instructions. '-no-mdmx' turns
off this option.
'-mdsp'
'-mno-dsp'
Generate code for the DSP Release 1 Application Specific Extension.
This tells the assembler to accept DSP Release 1 instructions.
'-mno-dsp' turns off this option.
'-mdspr2'
'-mno-dspr2'
Generate code for the DSP Release 2 Application Specific Extension.
This option implies -mdsp. This tells the assembler to accept DSP
Release 2 instructions. '-mno-dspr2' turns off this option.
'-mmt'
'-mno-mt'
Generate code for the MT Application Specific Extension. This
tells the assembler to accept MT instructions. '-mno-mt' turns off
this option.
'-mmcu'
'-mno-mcu'
Generate code for the MCU Application Specific Extension. This
tells the assembler to accept MCU instructions. '-mno-mcu' turns
off this option.
'-mmsa'
'-mno-msa'
Generate code for the MIPS SIMD Architecture Extension. This tells
the assembler to accept MSA instructions. '-mno-msa' turns off
this option.
'-mxpa'
'-mno-xpa'
Generate code for the MIPS eXtended Physical Address (XPA)
Extension. This tells the assembler to accept XPA instructions.
'-mno-xpa' turns off this option.
'-mvirt'
'-mno-virt'
Generate code for the Virtualization Application Specific
Extension. This tells the assembler to accept Virtualization
instructions. '-mno-virt' turns off this option.
'-minsn32'
'-mno-insn32'
Only use 32-bit instruction encodings when generating code for the
microMIPS processor. This option inhibits the use of any 16-bit
instructions. This is equivalent to putting '.set insn32' at the
start of the assembly file. '-mno-insn32' turns off this option.
This is equivalent to putting '.set noinsn32' at the start of the
assembly file. By default '-mno-insn32' is selected, allowing all
instructions to be used.
'-mfix7000'
'-mno-fix7000'
Cause nops to be inserted if the read of the destination register
of an mfhi or mflo instruction occurs in the following two
instructions.
'-mfix-rm7000'
'-mno-fix-rm7000'
Cause nops to be inserted if a dmult or dmultu instruction is
followed by a load instruction.
'-mfix-loongson2f-jump'
'-mno-fix-loongson2f-jump'
Eliminate instruction fetch from outside 256M region to work around
the Loongson2F 'jump' instructions. Without it, under extreme
cases, the kernel may crash. The issue has been solved in latest
processor batches, but this fix has no side effect to them.
'-mfix-loongson2f-nop'
'-mno-fix-loongson2f-nop'
Replace nops by 'or at,at,zero' to work around the Loongson2F 'nop'
errata. Without it, under extreme cases, the CPU might deadlock.
The issue has been solved in later Loongson2F batches, but this fix
has no side effect to them.
'-mfix-vr4120'
'-mno-fix-vr4120'
Insert nops to work around certain VR4120 errata. This option is
intended to be used on GCC-generated code: it is not designed to
catch all problems in hand-written assembler code.
'-mfix-vr4130'
'-mno-fix-vr4130'
Insert nops to work around the VR4130 'mflo'/'mfhi' errata.
'-mfix-24k'
'-mno-fix-24k'
Insert nops to work around the 24K 'eret'/'deret' errata.
'-mfix-cn63xxp1'
'-mno-fix-cn63xxp1'
Replace 'pref' hints 0 - 4 and 6 - 24 with hint 28 to work around
certain CN63XXP1 errata.
'-m4010'
'-no-m4010'
Generate code for the LSI R4010 chip. This tells the assembler to
accept the R4010-specific instructions ('addciu', 'ffc', etc.), and
to not schedule 'nop' instructions around accesses to the 'HI' and
'LO' registers. '-no-m4010' turns off this option.
'-m4650'
'-no-m4650'
Generate code for the MIPS R4650 chip. This tells the assembler to
accept the 'mad' and 'madu' instruction, and to not schedule 'nop'
instructions around accesses to the 'HI' and 'LO' registers.
'-no-m4650' turns off this option.
'-m3900'
'-no-m3900'
'-m4100'
'-no-m4100'
For each option '-mNNNN', generate code for the MIPS RNNNN chip.
This tells the assembler to accept instructions specific to that
chip, and to schedule for that chip's hazards.
'-march=CPU'
Generate code for a particular MIPS CPU. It is exactly equivalent
to '-mCPU', except that there are more value of CPU understood.
Valid CPU value are:
2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130,
vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231,
rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000,
10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem,
4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc,
24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1,
34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf,
74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, p5600,
5kc, 5kf, 20kc, 25kf, sb1, sb1a, loongson2e, loongson2f,
loongson3a, octeon, octeon+, octeon2, xlr, xlp
For compatibility reasons, 'Nx' and 'Bfx' are accepted as synonyms
for 'Nf1_1'. These values are deprecated.
'-mtune=CPU'
Schedule and tune for a particular MIPS CPU. Valid CPU values are
identical to '-march=CPU'.
'-mabi=ABI'
Record which ABI the source code uses. The recognized arguments
are: '32', 'n32', 'o64', '64' and 'eabi'.
'-msym32'
'-mno-sym32'
Equivalent to adding '.set sym32' or '.set nosym32' to the
beginning of the assembler input. *Note MIPS Symbol Sizes::.
'-nocpp'
This option is ignored. It is accepted for command-line
compatibility with other assemblers, which use it to turn off C
style preprocessing. With GNU 'as', there is no need for '-nocpp',
because the GNU assembler itself never runs the C preprocessor.
'-msoft-float'
'-mhard-float'
Disable or enable floating-point instructions. Note that by
default floating-point instructions are always allowed even with
CPU targets that don't have support for these instructions.
'-msingle-float'
'-mdouble-float'
Disable or enable double-precision floating-point operations. Note
that by default double-precision floating-point operations are
always allowed even with CPU targets that don't have support for
these operations.
'--construct-floats'
'--no-construct-floats'
The '--no-construct-floats' option disables the construction of
double width floating point constants by loading the two halves of
the value into the two single width floating point registers that
make up the double width register. This feature is useful if the
processor support the FR bit in its status register, and this bit
is known (by the programmer) to be set. This bit prevents the
aliasing of the double width register by the single width
registers.
By default '--construct-floats' is selected, allowing construction
of these floating point constants.
'--relax-branch'
'--no-relax-branch'
The '--relax-branch' option enables the relaxation of out-of-range
branches. Any branches whose target cannot be reached directly are
converted to a small instruction sequence including an
inverse-condition branch to the physically next instruction, and a
jump to the original target is inserted between the two
instructions. In PIC code the jump will involve further
instructions for address calculation.
The 'BC1ANY2F', 'BC1ANY2T', 'BC1ANY4F', 'BC1ANY4T', 'BPOSGE32' and
'BPOSGE64' instructions are excluded from relaxation, because they
have no complementing counterparts. They could be relaxed with the
use of a longer sequence involving another branch, however this has
not been implemented and if their target turns out of reach, they
produce an error even if branch relaxation is enabled.
Also no MIPS16 branches are ever relaxed.
By default '--no-relax-branch' is selected, causing any
out-of-range branches to produce an error.
'-mnan=ENCODING'
This option indicates whether the source code uses the IEEE 2008
NaN encoding ('-mnan=2008') or the original MIPS encoding
('-mnan=legacy'). It is equivalent to adding a '.nan' directive to
the beginning of the source file. *Note MIPS NaN Encodings::.
'-mnan=legacy' is the default if no '-mnan' option or '.nan'
directive is used.
'--trap'
'--no-break'
'as' automatically macro expands certain division and
multiplication instructions to check for overflow and division by
zero. This option causes 'as' to generate code to take a trap
exception rather than a break exception when an error is detected.
The trap instructions are only supported at Instruction Set
Architecture level 2 and higher.
'--break'
'--no-trap'
Generate code to take a break exception rather than a trap
exception when an error is detected. This is the default.
'-mpdr'
'-mno-pdr'
Control generation of '.pdr' sections. Off by default on IRIX, on
elsewhere.
'-mshared'
'-mno-shared'
When generating code using the Unix calling conventions (selected
by '-KPIC' or '-mcall_shared'), gas will normally generate code
which can go into a shared library. The '-mno-shared' option tells
gas to generate code which uses the calling convention, but can not
go into a shared library. The resulting code is slightly more
efficient. This option only affects the handling of the '.cpload'
and '.cpsetup' pseudo-ops.

File: as.info, Node: MIPS Macros, Next: MIPS Symbol Sizes, Prev: MIPS Options, Up: MIPS-Dependent
9.27.2 High-level assembly macros
---------------------------------
MIPS assemblers have traditionally provided a wider range of
instructions than the MIPS architecture itself. These extra
instructions are usually referred to as "macro" instructions (1).
Some MIPS macro instructions extend an underlying architectural
instruction while others are entirely new. An example of the former
type is 'and', which allows the third operand to be either a register or
an arbitrary immediate value. Examples of the latter type include
'bgt', which branches to the third operand when the first operand is
greater than the second operand, and 'ulh', which implements an
unaligned 2-byte load.
One of the most common extensions provided by macros is to expand
memory offsets to the full address range (32 or 64 bits) and to allow
symbolic offsets such as 'my_data + 4' to be used in place of integer
constants. For example, the architectural instruction 'lbu' allows only
a signed 16-bit offset, whereas the macro 'lbu' allows code such as 'lbu
$4,array+32769($5)'. The implementation of these symbolic offsets
depends on several factors, such as whether the assembler is generating
SVR4-style PIC (selected by '-KPIC', *note Assembler options: MIPS
Options.), the size of symbols (*note Directives to override the size of
symbols: MIPS Symbol Sizes.), and the small data limit (*note
Controlling the use of small data accesses: MIPS Small Data.).
Sometimes it is undesirable to have one assembly instruction expand
to several machine instructions. The directive '.set nomacro' tells the
assembler to warn when this happens. '.set macro' restores the default
behavior.
Some macro instructions need a temporary register to store
intermediate results. This register is usually '$1', also known as
'$at', but it can be changed to any core register REG using '.set
at=REG'. Note that '$at' always refers to '$1' regardless of which
register is being used as the temporary register.
Implicit uses of the temporary register in macros could interfere
with explicit uses in the assembly code. The assembler therefore warns
whenever it sees an explicit use of the temporary register. The
directive '.set noat' silences this warning while '.set at' restores the
default behavior. It is safe to use '.set noat' while '.set nomacro' is
in effect since single-instruction macros never need a temporary
register.
Note that while the GNU assembler provides these macros for
compatibility, it does not make any attempt to optimize them with the
surrounding code.
---------- Footnotes ----------
(1) The term "macro" is somewhat overloaded here, since these macros
have no relation to those defined by '.macro', *note '.macro': Macro.

File: as.info, Node: MIPS Symbol Sizes, Next: MIPS Small Data, Prev: MIPS Macros, Up: MIPS-Dependent
9.27.3 Directives to override the size of symbols
-------------------------------------------------
The n64 ABI allows symbols to have any 64-bit value. Although this
provides a great deal of flexibility, it means that some macros have
much longer expansions than their 32-bit counterparts. For example, the
non-PIC expansion of 'dla $4,sym' is usually:
lui $4,%highest(sym)
lui $1,%hi(sym)
daddiu $4,$4,%higher(sym)
daddiu $1,$1,%lo(sym)
dsll32 $4,$4,0
daddu $4,$4,$1
whereas the 32-bit expansion is simply:
lui $4,%hi(sym)
daddiu $4,$4,%lo(sym)
n64 code is sometimes constructed in such a way that all symbolic
constants are known to have 32-bit values, and in such cases, it's
preferable to use the 32-bit expansion instead of the 64-bit expansion.
You can use the '.set sym32' directive to tell the assembler that,
from this point on, all expressions of the form 'SYMBOL' or 'SYMBOL +
OFFSET' have 32-bit values. For example:
.set sym32
dla $4,sym
lw $4,sym+16
sw $4,sym+0x8000($4)
will cause the assembler to treat 'sym', 'sym+16' and 'sym+0x8000' as
32-bit values. The handling of non-symbolic addresses is not affected.
The directive '.set nosym32' ends a '.set sym32' block and reverts to
the normal behavior. It is also possible to change the symbol size
using the command-line options '-msym32' and '-mno-sym32'.
These options and directives are always accepted, but at present,
they have no effect for anything other than n64.

File: as.info, Node: MIPS Small Data, Next: MIPS ISA, Prev: MIPS Symbol Sizes, Up: MIPS-Dependent
9.27.4 Controlling the use of small data accesses
-------------------------------------------------
It often takes several instructions to load the address of a symbol.
For example, when 'addr' is a 32-bit symbol, the non-PIC expansion of
'dla $4,addr' is usually:
lui $4,%hi(addr)
daddiu $4,$4,%lo(addr)
The sequence is much longer when 'addr' is a 64-bit symbol. *Note
Directives to override the size of symbols: MIPS Symbol Sizes.
In order to cut down on this overhead, most embedded MIPS systems set
aside a 64-kilobyte "small data" area and guarantee that all data of
size N and smaller will be placed in that area. The limit N is passed
to both the assembler and the linker using the command-line option '-G
N', *note Assembler options: MIPS Options. Note that the same value of
N must be used when linking and when assembling all input files to the
link; any inconsistency could cause a relocation overflow error.
The size of an object in the '.bss' section is set by the '.comm' or
'.lcomm' directive that defines it. The size of an external object may
be set with the '.extern' directive. For example, '.extern sym,4'
declares that the object at 'sym' is 4 bytes in length, while leaving
'sym' otherwise undefined.
When no '-G' option is given, the default limit is 8 bytes. The
option '-G 0' prevents any data from being automatically classified as
small.
It is also possible to mark specific objects as small by putting them
in the special sections '.sdata' and '.sbss', which are "small"
counterparts of '.data' and '.bss' respectively. The toolchain will
treat such data as small regardless of the '-G' setting.
On startup, systems that support a small data area are expected to
initialize register '$28', also known as '$gp', in such a way that small
data can be accessed using a 16-bit offset from that register. For
example, when 'addr' is small data, the 'dla $4,addr' instruction above
is equivalent to:
daddiu $4,$28,%gp_rel(addr)
Small data is not supported for SVR4-style PIC.

File: as.info, Node: MIPS ISA, Next: MIPS assembly options, Prev: MIPS Small Data, Up: MIPS-Dependent
9.27.5 Directives to override the ISA level
-------------------------------------------
GNU 'as' supports an additional directive to change the MIPS Instruction
Set Architecture level on the fly: '.set mipsN'. N should be a number
from 0 to 5, or 32, 32r2, 32r3, 32r5, 32r6, 64, 64r2, 64r3, 64r5 or
64r6. The values other than 0 make the assembler accept instructions
for the corresponding ISA level, from that point on in the assembly.
'.set mipsN' affects not only which instructions are permitted, but also
how certain macros are expanded. '.set mips0' restores the ISA level to
its original level: either the level you selected with command line
options, or the default for your configuration. You can use this
feature to permit specific MIPS III instructions while assembling in 32
bit mode. Use this directive with care!
The '.set arch=CPU' directive provides even finer control. It
changes the effective CPU target and allows the assembler to use
instructions specific to a particular CPU. All CPUs supported by the
'-march' command line option are also selectable by this directive. The
original value is restored by '.set arch=default'.
The directive '.set mips16' puts the assembler into MIPS 16 mode, in
which it will assemble instructions for the MIPS 16 processor. Use
'.set nomips16' to return to normal 32 bit mode.
Traditional MIPS assemblers do not support this directive.
The directive '.set micromips' puts the assembler into microMIPS
mode, in which it will assemble instructions for the microMIPS
processor. Use '.set nomicromips' to return to normal 32 bit mode.
Traditional MIPS assemblers do not support this directive.

File: as.info, Node: MIPS assembly options, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent
9.27.6 Directives to control code generation
--------------------------------------------
The '.module' directive allows command line options to be set directly
from assembly. The format of the directive matches the '.set' directive
but only those options which are relevant to a whole module are
supported. The effect of a '.module' directive is the same as the
corresponding command line option. Where '.set' directives support
returning to a default then the '.module' directives do not as they
define the defaults.
These module-level directives must appear first in assembly.
Traditional MIPS assemblers do not support this directive.
The directive '.set insn32' makes the assembler only use 32-bit
instruction encodings when generating code for the microMIPS processor.
This directive inhibits the use of any 16-bit instructions from that
point on in the assembly. The '.set noinsn32' directive allows 16-bit
instructions to be accepted.
Traditional MIPS assemblers do not support this directive.

File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS assembly options, Up: MIPS-Dependent
9.27.7 Directives for extending MIPS 16 bit instructions
--------------------------------------------------------
By default, MIPS 16 instructions are automatically extended to 32 bits
when necessary. The directive '.set noautoextend' will turn this off.
When '.set noautoextend' is in effect, any 32 bit instruction must be
explicitly extended with the '.e' modifier (e.g., 'li.e $4,1000'). The
directive '.set autoextend' may be used to once again automatically
extend instructions when necessary.
This directive is only meaningful when in MIPS 16 mode. Traditional
MIPS assemblers do not support this directive.

File: as.info, Node: MIPS insn, Next: MIPS FP ABIs, Prev: MIPS autoextend, Up: MIPS-Dependent
9.27.8 Directive to mark data as an instruction
-----------------------------------------------
The '.insn' directive tells 'as' that the following data is actually
instructions. This makes a difference in MIPS 16 and microMIPS modes:
when loading the address of a label which precedes instructions, 'as'
automatically adds 1 to the value, so that jumping to the loaded address
will do the right thing.
The '.global' and '.globl' directives supported by 'as' will by
default mark the symbol as pointing to a region of data not code. This
means that, for example, any instructions following such a symbol will
not be disassembled by 'objdump' as it will regard them as data. To
change this behavior an optional section name can be placed after the
symbol name in the '.global' directive. If this section exists and is
known to be a code section, then the symbol will be marked as pointing
at code not data. Ie the syntax for the directive is:
'.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...',
Here is a short example:
.global foo .text, bar, baz .data
foo:
nop
bar:
.word 0x0
baz:
.word 0x1

File: as.info, Node: MIPS FP ABIs, Next: MIPS NaN Encodings, Prev: MIPS insn, Up: MIPS-Dependent
9.27.9 Directives to control the FP ABI
---------------------------------------
* Menu:
* MIPS FP ABI History:: History of FP ABIs
* MIPS FP ABI Variants:: Supported FP ABIs
* MIPS FP ABI Selection:: Automatic selection of FP ABI
* MIPS FP ABI Compatibility:: Linking different FP ABI variants

File: as.info, Node: MIPS FP ABI History, Next: MIPS FP ABI Variants, Up: MIPS FP ABIs
9.27.9.1 History of FP ABIs
...........................
The MIPS ABIs support a variety of different floating-point extensions
where calling-convention and register sizes vary for floating-point
data. The extensions exist to support a wide variety of optional
architecture features. The resulting ABI variants are generally
incompatible with each other and must be tracked carefully.
Traditionally the use of an explicit '.gnu_attribute 4, N' directive
is used to indicate which ABI is in use by a specific module. It was
then left to the user to ensure that command line options and the
selected ABI were compatible with some potential for inconsistencies.

File: as.info, Node: MIPS FP ABI Variants, Next: MIPS FP ABI Selection, Prev: MIPS FP ABI History, Up: MIPS FP ABIs
9.27.9.2 Supported FP ABIs
..........................
The supported floating-point ABI variants are:
'0 - No floating-point'
This variant is used to indicate that floating-point is not used
within the module at all and therefore has no impact on the ABI.
This is the default.
'1 - Double-precision'
This variant indicates that double-precision support is used. For
64-bit ABIs this means that 64-bit wide floating-point registers
are required. For 32-bit ABIs this means that 32-bit wide
floating-point registers are required and double-precision
operations use pairs of registers.
'2 - Single-precision'
This variant indicates that single-precision support is used.
Double precision operations will be supported via soft-float
routines.
'3 - Soft-float'
This variant indicates that although floating-point support is used
all operations are emulated in software. This means the ABI is
modified to pass all floating-point data in general-purpose
registers.
'4 - Deprecated'
This variant existed as an initial attempt at supporting 64-bit
wide floating-point registers for O32 ABI on a MIPS32r2 CPU. This
has been superseded by 5, 6 and 7.
'5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU'
This variant is used by 32-bit ABIs to indicate that the
floating-point code in the module has been designed to operate
correctly with either 32-bit wide or 64-bit wide floating-point
registers. Double-precision support is used. Only O32 currently
supports this variant and requires a minimum architecture of MIPS
II.
'6 - Double-precision 32-bit FPU, 64-bit FPU'
This variant is used by 32-bit ABIs to indicate that the
floating-point code in the module requires 64-bit wide
floating-point registers. Double-precision support is used. Only
O32 currently supports this variant and requires a minimum
architecture of MIPS32r2.
'7 - Double-precision compat 32-bit FPU, 64-bit FPU'
This variant is used by 32-bit ABIs to indicate that the
floating-point code in the module requires 64-bit wide
floating-point registers. Double-precision support is used. This
differs from the previous ABI as it restricts use of odd-numbered
single-precision registers. Only O32 currently supports this
variant and requires a minimum architecture of MIPS32r2.

File: as.info, Node: MIPS FP ABI Selection, Next: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Variants, Up: MIPS FP ABIs
9.27.9.3 Automatic selection of FP ABI
......................................
In order to simplify and add safety to the process of selecting the
correct floating-point ABI, the assembler will automatically infer the
correct '.gnu_attribute 4, N' directive based on command line options
and '.module' overrides. Where an explicit '.gnu_attribute 4, N'
directive has been seen then a warning will be raised if it does not
match an inferred setting.
The floating-point ABI is inferred as follows. If '-msoft-float' has
been used the module will be marked as soft-float. If '-msingle-float'
has been used then the module will be marked as single-precision. The
remaining ABIs are then selected based on the FP register width.
Double-precision is selected if the width of GP and FP registers match
and the special double-precision variants for 32-bit ABIs are then
selected depending on '-mfpxx', '-mfp64' and '-mno-odd-spreg'.

File: as.info, Node: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Selection, Up: MIPS FP ABIs
9.27.9.4 Linking different FP ABI variants
..........................................
Modules using the default FP ABI (no floating-point) can be linked with
any other (singular) FP ABI variant.
Special compatibility support exists for O32 with the four
double-precision FP ABI variants. The '-mfpxx' FP ABI is specifically
designed to be compatible with the standard double-precision ABI and the
'-mfp64' FP ABIs. This makes it desirable for O32 modules to be built
as '-mfpxx' to ensure the maximum compatibility with other modules
produced for more specific needs. The only FP ABIs which cannot be
linked together are the standard double-precision ABI and the full
'-mfp64' ABI with '-modd-spreg'.

File: as.info, Node: MIPS NaN Encodings, Next: MIPS Option Stack, Prev: MIPS FP ABIs, Up: MIPS-Dependent
9.27.10 Directives to record which NaN encoding is being used
-------------------------------------------------------------
The IEEE 754 floating-point standard defines two types of not-a-number
(NaN) data: "signalling" NaNs and "quiet" NaNs. The original version of
the standard did not specify how these two types should be
distinguished. Most implementations followed the i387 model, in which
the first bit of the significand is set for quiet NaNs and clear for
signalling NaNs. However, the original MIPS implementation assigned the
opposite meaning to the bit, so that it was set for signalling NaNs and
clear for quiet NaNs.
The 2008 revision of the standard formally suggested the i387 choice
and as from Sep 2012 the current release of the MIPS architecture
therefore optionally supports that form. Code that uses one NaN
encoding would usually be incompatible with code that uses the other NaN
encoding, so MIPS ELF objects have a flag ('EF_MIPS_NAN2008') to record
which encoding is being used.
Assembly files can use the '.nan' directive to select between the two
encodings. '.nan 2008' says that the assembly file uses the IEEE
754-2008 encoding while '.nan legacy' says that the file uses the
original MIPS encoding. If several '.nan' directives are given, the
final setting is the one that is used.
The command-line options '-mnan=legacy' and '-mnan=2008' can be used
instead of '.nan legacy' and '.nan 2008' respectively. However, any
'.nan' directive overrides the command-line setting.
'.nan legacy' is the default if no '.nan' directive or '-mnan' option
is given.
Note that GNU 'as' does not produce NaNs itself and therefore these
directives do not affect code generation. They simply control the
setting of the 'EF_MIPS_NAN2008' flag.
Traditional MIPS assemblers do not support these directives.

File: as.info, Node: MIPS Option Stack, Next: MIPS ASE Instruction Generation Overrides, Prev: MIPS NaN Encodings, Up: MIPS-Dependent
9.27.11 Directives to save and restore options
----------------------------------------------
The directives '.set push' and '.set pop' may be used to save and
restore the current settings for all the options which are controlled by
'.set'. The '.set push' directive saves the current settings on a
stack. The '.set pop' directive pops the stack and restores the
settings.
These directives can be useful inside an macro which must change an
option such as the ISA level or instruction reordering but does not want
to change the state of the code which invoked the macro.
Traditional MIPS assemblers do not support these directives.

File: as.info, Node: MIPS ASE Instruction Generation Overrides, Next: MIPS Floating-Point, Prev: MIPS Option Stack, Up: MIPS-Dependent
9.27.12 Directives to control generation of MIPS ASE instructions
-----------------------------------------------------------------
The directive '.set mips3d' makes the assembler accept instructions from
the MIPS-3D Application Specific Extension from that point on in the
assembly. The '.set nomips3d' directive prevents MIPS-3D instructions
from being accepted.
The directive '.set smartmips' makes the assembler accept
instructions from the SmartMIPS Application Specific Extension to the
MIPS32 ISA from that point on in the assembly. The '.set nosmartmips'
directive prevents SmartMIPS instructions from being accepted.
The directive '.set mdmx' makes the assembler accept instructions
from the MDMX Application Specific Extension from that point on in the
assembly. The '.set nomdmx' directive prevents MDMX instructions from
being accepted.
The directive '.set dsp' makes the assembler accept instructions from
the DSP Release 1 Application Specific Extension from that point on in
the assembly. The '.set nodsp' directive prevents DSP Release 1
instructions from being accepted.
The directive '.set dspr2' makes the assembler accept instructions
from the DSP Release 2 Application Specific Extension from that point on
in the assembly. This directive implies '.set dsp'. The '.set nodspr2'
directive prevents DSP Release 2 instructions from being accepted.
The directive '.set mt' makes the assembler accept instructions from
the MT Application Specific Extension from that point on in the
assembly. The '.set nomt' directive prevents MT instructions from being
accepted.
The directive '.set mcu' makes the assembler accept instructions from
the MCU Application Specific Extension from that point on in the
assembly. The '.set nomcu' directive prevents MCU instructions from
being accepted.
The directive '.set msa' makes the assembler accept instructions from
the MIPS SIMD Architecture Extension from that point on in the assembly.
The '.set nomsa' directive prevents MSA instructions from being
accepted.
The directive '.set virt' makes the assembler accept instructions
from the Virtualization Application Specific Extension from that point
on in the assembly. The '.set novirt' directive prevents Virtualization
instructions from being accepted.
The directive '.set xpa' makes the assembler accept instructions from
the XPA Extension from that point on in the assembly. The '.set noxpa'
directive prevents XPA instructions from being accepted.
Traditional MIPS assemblers do not support these directives.

File: as.info, Node: MIPS Floating-Point, Next: MIPS Syntax, Prev: MIPS ASE Instruction Generation Overrides, Up: MIPS-Dependent
9.27.13 Directives to override floating-point options
-----------------------------------------------------
The directives '.set softfloat' and '.set hardfloat' provide finer
control of disabling and enabling float-point instructions. These
directives always override the default (that hard-float instructions are
accepted) or the command-line options ('-msoft-float' and
'-mhard-float').
The directives '.set singlefloat' and '.set doublefloat' provide
finer control of disabling and enabling double-precision float-point
operations. These directives always override the default (that
double-precision operations are accepted) or the command-line options
('-msingle-float' and '-mdouble-float').
Traditional MIPS assemblers do not support these directives.

File: as.info, Node: MIPS Syntax, Prev: MIPS Floating-Point, Up: MIPS-Dependent
9.27.14 Syntactical considerations for the MIPS assembler
---------------------------------------------------------
* Menu:
* MIPS-Chars:: Special Characters

File: as.info, Node: MIPS-Chars, Up: MIPS Syntax
9.27.14.1 Special Characters
............................
The presence of a '#' on a line indicates the start of a comment that
extends to the end of the current line.
If a '#' appears as the first character of a line, the whole line is
treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
The ';' character can be used to separate statements on the same
line.

File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies
9.28 MMIX Dependent Features
============================
* Menu:
* MMIX-Opts:: Command-line Options
* MMIX-Expand:: Instruction expansion
* MMIX-Syntax:: Syntax
* MMIX-mmixal:: Differences to 'mmixal' syntax and semantics

File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent
9.28.1 Command-line Options
---------------------------
The MMIX version of 'as' has some machine-dependent options.
When '--fixed-special-register-names' is specified, only the register
names specified in *note MMIX-Regs:: are recognized in the instructions
'PUT' and 'GET'.
You can use the '--globalize-symbols' to make all symbols global.
This option is useful when splitting up a 'mmixal' program into several
files.
The '--gnu-syntax' turns off most syntax compatibility with 'mmixal'.
Its usability is currently doubtful.
The '--relax' option is not fully supported, but will eventually make
the object file prepared for linker relaxation.
If you want to avoid inadvertently calling a predefined symbol and
would rather get an error, for example when using 'as' with a compiler
or other machine-generated code, specify '--no-predefined-syms'. This
turns off built-in predefined definitions of all such symbols, including
rounding-mode symbols, segment symbols, 'BIT' symbols, and 'TRAP'
symbols used in 'mmix' "system calls". It also turns off predefined
special-register names, except when used in 'PUT' and 'GET'
instructions.
By default, some instructions are expanded to fit the size of the
operand or an external symbol (*note MMIX-Expand::). By passing
'--no-expand', no such expansion will be done, instead causing errors at
link time if the operand does not fit.
The 'mmixal' documentation (*note mmixsite::) specifies that global
registers allocated with the 'GREG' directive (*note MMIX-greg::) and
initialized to the same non-zero value, will refer to the same global
register. This isn't strictly enforceable in 'as' since the final
addresses aren't known until link-time, but it will do an effort unless
the '--no-merge-gregs' option is specified. (Register merging isn't yet
implemented in 'ld'.)
'as' will warn every time it expands an instruction to fit an operand
unless the option '-x' is specified. It is believed that this behaviour
is more useful than just mimicking 'mmixal''s behaviour, in which
instructions are only expanded if the '-x' option is specified, and
assembly fails otherwise, when an instruction needs to be expanded. It
needs to be kept in mind that 'mmixal' is both an assembler and linker,
while 'as' will expand instructions that at link stage can be
contracted. (Though linker relaxation isn't yet implemented in 'ld'.)
The option '-x' also imples '--linker-allocated-gregs'.
If instruction expansion is enabled, 'as' can expand a 'PUSHJ'
instruction into a series of instructions. The shortest expansion is to
not expand it, but just mark the call as redirectable to a stub, which
'ld' creates at link-time, but only if the original 'PUSHJ' instruction
is found not to reach the target. The stub consists of the necessary
instructions to form a jump to the target. This happens if 'as' can
assert that the 'PUSHJ' instruction can reach such a stub. The option
'--no-pushj-stubs' disables this shorter expansion, and the longer
series of instructions is then created at assembly-time. The option
'--no-stubs' is a synonym, intended for compatibility with future
releases, where generation of stubs for other instructions may be
implemented.
Usually a two-operand-expression (*note GREG-base::) without a
matching 'GREG' directive is treated as an error by 'as'. When the
option '--linker-allocated-gregs' is in effect, they are instead passed
through to the linker, which will allocate as many global registers as
is needed.

File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent
9.28.2 Instruction expansion
----------------------------
When 'as' encounters an instruction with an operand that is either not
known or does not fit the operand size of the instruction, 'as' (and
'ld') will expand the instruction into a sequence of instructions
semantically equivalent to the operand fitting the instruction.
Expansion will take place for the following instructions:
'GETA'
Expands to a sequence of four instructions: 'SETL', 'INCML',
'INCMH' and 'INCH'. The operand must be a multiple of four.
Conditional branches
A branch instruction is turned into a branch with the complemented
condition and prediction bit over five instructions; four
instructions setting '$255' to the operand value, which like with
'GETA' must be a multiple of four, and a final 'GO $255,$255,0'.
'PUSHJ'
Similar to expansion for conditional branches; four instructions
set '$255' to the operand value, followed by a 'PUSHGO
$255,$255,0'.
'JMP'
Similar to conditional branches and 'PUSHJ'. The final instruction
is 'GO $255,$255,0'.
The linker 'ld' is expected to shrink these expansions for code
assembled with '--relax' (though not currently implemented).

File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent
9.28.3 Syntax
-------------
The assembly syntax is supposed to be upward compatible with that
described in Sections 1.3 and 1.4 of 'The Art of Computer Programming,
Volume 1'. Draft versions of those chapters as well as other MMIX
information is located at
<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>. Most code
examples from the mmixal package located there should work unmodified
when assembled and linked as single files, with a few noteworthy
exceptions (*note MMIX-mmixal::).
Before an instruction is emitted, the current location is aligned to
the next four-byte boundary. If a label is defined at the beginning of
the line, its value will be the aligned value.
In addition to the traditional hex-prefix '0x', a hexadecimal number
can also be specified by the prefix character '#'.
After all operands to an MMIX instruction or directive have been
specified, the rest of the line is ignored, treated as a comment.
* Menu:
* MMIX-Chars:: Special Characters
* MMIX-Symbols:: Symbols
* MMIX-Regs:: Register Names
* MMIX-Pseudos:: Assembler Directives

File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax
9.28.3.1 Special Characters
...........................
The characters '*' and '#' are line comment characters; each start a
comment at the beginning of a line, but only at the beginning of a line.
A '#' prefixes a hexadecimal number if found elsewhere on a line. If a
'#' appears at the start of a line the whole line is treated as a
comment, but the line can also act as a logical line number directive
(*note Comments::) or a preprocessor control command (*note
Preprocessing::).
Two other characters, '%' and '!', each start a comment anywhere on
the line. Thus you can't use the 'modulus' and 'not' operators in
expressions normally associated with these two characters.
A ';' is a line separator, treated as a new-line, so separate
instructions can be specified on a single line.

File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax
9.28.3.2 Symbols
................
The character ':' is permitted in identifiers. There are two exceptions
to it being treated as any other symbol character: if a symbol begins
with ':', it means that the symbol is in the global namespace and that
the current prefix should not be prepended to that symbol (*note
MMIX-prefix::). The ':' is then not considered part of the symbol. For
a symbol in the label position (first on a line), a ':' at the end of a
symbol is silently stripped off. A label is permitted, but not
required, to be followed by a ':', as with many other assembly formats.
The character '@' in an expression, is a synonym for '.', the current
location.
In addition to the common forward and backward local symbol formats
(*note Symbol Names::), they can be specified with upper-case 'B' and
'F', as in '8B' and '9F'. A local label defined for the current
position is written with a 'H' appended to the number:
3H LDB $0,$1,2
This and traditional local-label formats cannot be mixed: a label
must be defined and referred to using the same format.
There's a minor caveat: just as for the ordinary local symbols, the
local symbols are translated into ordinary symbols using control
characters are to hide the ordinal number of the symbol. Unfortunately,
these symbols are not translated back in error messages. Thus you may
see confusing error messages when local symbols are used. Control
characters '\003' (control-C) and '\004' (control-D) are used for the
MMIX-specific local-symbol syntax.
The symbol 'Main' is handled specially; it is always global.
By defining the symbols '__.MMIX.start..text' and
'__.MMIX.start..data', the address of respectively the '.text' and
'.data' segments of the final program can be defined, though when
linking more than one object file, the code or data in the object file
containing the symbol is not guaranteed to be start at that position;
just the final executable. *Note MMIX-loc::.

File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax
9.28.3.3 Register names
.......................
Local and global registers are specified as '$0' to '$255'. The
recognized special register names are 'rJ', 'rA', 'rB', 'rC', 'rD',
'rE', 'rF', 'rG', 'rH', 'rI', 'rK', 'rL', 'rM', 'rN', 'rO', 'rP', 'rQ',
'rR', 'rS', 'rT', 'rU', 'rV', 'rW', 'rX', 'rY', 'rZ', 'rBB', 'rTT',
'rWW', 'rXX', 'rYY' and 'rZZ'. A leading ':' is optional for special
register names.
Local and global symbols can be equated to register names and used in
place of ordinary registers.
Similarly for special registers, local and global symbols can be
used. Also, symbols equated from numbers and constant expressions are
allowed in place of a special register, except when either of the
options '--no-predefined-syms' and '--fixed-special-register-names' are
specified. Then only the special register names above are allowed for
the instructions having a special register operand; 'GET' and 'PUT'.

File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax
9.28.3.4 Assembler Directives
.............................
'LOC'
The 'LOC' directive sets the current location to the value of the
operand field, which may include changing sections. If the operand
is a constant, the section is set to either '.data' if the value is
'0x2000000000000000' or larger, else it is set to '.text'. Within
a section, the current location may only be changed to
monotonically higher addresses. A LOC expression must be a
previously defined symbol or a "pure" constant.
An example, which sets the label PREV to the current location, and
updates the current location to eight bytes forward:
prev LOC @+8
When a LOC has a constant as its operand, a symbol
'__.MMIX.start..text' or '__.MMIX.start..data' is defined depending
on the address as mentioned above. Each such symbol is interpreted
as special by the linker, locating the section at that address.
Note that if multiple files are linked, the first object file with
that section will be mapped to that address (not necessarily the
file with the LOC definition).
'LOCAL'
Example:
LOCAL external_symbol
LOCAL 42
.local asymbol
This directive-operation generates a link-time assertion that the
operand does not correspond to a global register. The operand is
an expression that at link-time resolves to a register symbol or a
number. A number is treated as the register having that number.
There is one restriction on the use of this directive: the
pseudo-directive must be placed in a section with contents, code or
data.
'IS'
The 'IS' directive:
asymbol IS an_expression
sets the symbol 'asymbol' to 'an_expression'. A symbol may not be
set more than once using this directive. Local labels may be set
using this directive, for example:
5H IS @+4
'GREG'
This directive reserves a global register, gives it an initial
value and optionally gives it a symbolic name. Some examples:
areg GREG
breg GREG data_value
GREG data_buffer
.greg creg, another_data_value
The symbolic register name can be used in place of a (non-special)
register. If a value isn't provided, it defaults to zero. Unless
the option '--no-merge-gregs' is specified, non-zero registers
allocated with this directive may be eliminated by 'as'; another
register with the same value used in its place. Any of the
instructions 'CSWAP', 'GO', 'LDA', 'LDBU', 'LDB', 'LDHT', 'LDOU',
'LDO', 'LDSF', 'LDTU', 'LDT', 'LDUNC', 'LDVTS', 'LDWU', 'LDW',
'PREGO', 'PRELD', 'PREST', 'PUSHGO', 'STBU', 'STB', 'STCO', 'STHT',
'STOU', 'STSF', 'STTU', 'STT', 'STUNC', 'SYNCD', 'SYNCID', can have
a value nearby an initial value in place of its second and third
operands. Here, "nearby" is defined as within the range 0...255
from the initial value of such an allocated register.
buffer1 BYTE 0,0,0,0,0
buffer2 BYTE 0,0,0,0,0
...
GREG buffer1
LDOU $42,buffer2
In the example above, the 'Y' field of the 'LDOUI' instruction
(LDOU with a constant Z) will be replaced with the global register
allocated for 'buffer1', and the 'Z' field will have the value 5,
the offset from 'buffer1' to 'buffer2'. The result is equivalent
to this code:
buffer1 BYTE 0,0,0,0,0
buffer2 BYTE 0,0,0,0,0
...
tmpreg GREG buffer1
LDOU $42,tmpreg,(buffer2-buffer1)
Global registers allocated with this directive are allocated in
order higher-to-lower within a file. Other than that, the exact
order of register allocation and elimination is undefined. For
example, the order is undefined when more than one file with such
directives are linked together. With the options '-x' and
'--linker-allocated-gregs', 'GREG' directives for two-operand cases
like the one mentioned above can be omitted. Sufficient global
registers will then be allocated by the linker.
'BYTE'
The 'BYTE' directive takes a series of operands separated by a
comma. If an operand is a string (*note Strings::), each character
of that string is emitted as a byte. Other operands must be
constant expressions without forward references, in the range
0...255. If you need operands having expressions with forward
references, use '.byte' (*note Byte::). An operand can be omitted,
defaulting to a zero value.
'WYDE'
'TETRA'
'OCTA'
The directives 'WYDE', 'TETRA' and 'OCTA' emit constants of two,
four and eight bytes size respectively. Before anything else
happens for the directive, the current location is aligned to the
respective constant-size boundary. If a label is defined at the
beginning of the line, its value will be that after the alignment.
A single operand can be omitted, defaulting to a zero value emitted
for the directive. Operands can be expressed as strings (*note
Strings::), in which case each character in the string is emitted
as a separate constant of the size indicated by the directive.
'PREFIX'
The 'PREFIX' directive sets a symbol name prefix to be prepended to
all symbols (except local symbols, *note MMIX-Symbols::), that are
not prefixed with ':', until the next 'PREFIX' directive. Such
prefixes accumulate. For example,
PREFIX a
PREFIX b
c IS 0
defines a symbol 'abc' with the value 0.
'BSPEC'
'ESPEC'
A pair of 'BSPEC' and 'ESPEC' directives delimit a section of
special contents (without specified semantics). Example:
BSPEC 42
TETRA 1,2,3
ESPEC
The single operand to 'BSPEC' must be number in the range 0...255.
The 'BSPEC' number 80 is used by the GNU binutils implementation.

File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent
9.28.4 Differences to 'mmixal'
------------------------------
The binutils 'as' and 'ld' combination has a few differences in function
compared to 'mmixal' (*note mmixsite::).
The replacement of a symbol with a GREG-allocated register (*note
GREG-base::) is not handled the exactly same way in 'as' as in 'mmixal'.
This is apparent in the 'mmixal' example file 'inout.mms', where
different registers with different offsets, eventually yielding the same
address, are used in the first instruction. This type of difference
should however not affect the function of any program unless it has
specific assumptions about the allocated register number.
Line numbers (in the 'mmo' object format) are currently not
supported.
Expression operator precedence is not that of mmixal: operator
precedence is that of the C programming language. It's recommended to
use parentheses to explicitly specify wanted operator precedence
whenever more than one type of operators are used.
The serialize unary operator '&', the fractional division operator
'//', the logical not operator '!' and the modulus operator '%' are not
available.
Symbols are not global by default, unless the option
'--globalize-symbols' is passed. Use the '.global' directive to
globalize symbols (*note Global::).
Operand syntax is a bit stricter with 'as' than 'mmixal'. For
example, you can't say 'addu 1,2,3', instead you must write 'addu
$1,$2,3'.
You can't LOC to a lower address than those already visited (i.e.,
"backwards").
A LOC directive must come before any emitted code.
Predefined symbols are visible as file-local symbols after use. (In
the ELF file, that is--the linked mmo file has no notion of a file-local
symbol.)
Some mapping of constant expressions to sections in LOC expressions
is attempted, but that functionality is easily confused and should be
avoided unless compatibility with 'mmixal' is required. A LOC
expression to '0x2000000000000000' or higher, maps to the '.data'
section and lower addresses map to the '.text' section (*note
MMIX-loc::).
The code and data areas are each contiguous. Sparse programs with
far-away LOC directives will take up the same amount of space as a
contiguous program with zeros filled in the gaps between the LOC
directives. If you need sparse programs, you might try and get the
wanted effect with a linker script and splitting up the code parts into
sections (*note Section::). Assembly code for this, to be compatible
with 'mmixal', would look something like:
.if 0
LOC away_expression
.else
.section away,"ax"
.fi
'as' will not execute the LOC directive and 'mmixal' ignores the
lines with '.'. This construct can be used generally to help
compatibility.
Symbols can't be defined twice-not even to the same value.
Instruction mnemonics are recognized case-insensitive, though the
'IS' and 'GREG' pseudo-operations must be specified in upper-case
characters.
There's no unicode support.
The following is a list of programs in 'mmix.tar.gz', available at
<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>, last checked
with the version dated 2001-08-25 (md5sum
c393470cfc86fac040487d22d2bf0172) that assemble with 'mmixal' but do not
assemble with 'as':
'silly.mms'
LOC to a previous address.
'sim.mms'
Redefines symbol 'Done'.
'test.mms'
Uses the serial operator '&'.

File: as.info, Node: MSP430-Dependent, Next: NDS32-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies
9.29 MSP 430 Dependent Features
===============================
* Menu:
* MSP430 Options:: Options
* MSP430 Syntax:: Syntax
* MSP430 Floating Point:: Floating Point
* MSP430 Directives:: MSP 430 Machine Directives
* MSP430 Opcodes:: Opcodes
* MSP430 Profiling Capability:: Profiling Capability

File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent
9.29.1 Options
--------------
'-mmcu'
selects the mcu architecture. If the architecture is 430Xv2 then
this also enables NOP generation unless the '-mN' is also
specified.
'-mcpu'
selects the cpu architecture. If the architecture is 430Xv2 then
this also enables NOP generation unless the '-mN' is also
specified.
'-mP'
enables polymorph instructions handler.
'-mQ'
enables relaxation at assembly time. DANGEROUS!
'-ml'
indicates that the input uses the large code model.
'-mn'
enables the generation of a NOP instruction following any
instruction that might change the interrupts enabled/disabled
state. The pipelined nature of the MSP430 core means that any
instruction that changes the interrupt state ('EINT', 'DINT', 'BIC
#8, SR', 'BIS #8, SR' or 'MOV.W <>, SR') must be followed by a NOP
instruction in order to ensure the correct processing of
interrupts. By default it is up to the programmer to supply these
NOP instructions, but this command line option enables the
automatic insertion by the assembler, if they are missing.
'-mN'
disables the generation of a NOP instruction following any
instruction that might change the interrupts enabled/disabled
state. This is the default behaviour.
'-my'
tells the assembler to generate a warning message if a NOP does not
immediately forllow an instruction that enables or disables
interrupts. This is the default.
Note that this option can be stacked with the '-mn' option so that
the assembler will both warn about missing NOP instructions and
then insert them automatically.
'-mY'
disables warnings about missing NOP instructions.
'-md'
mark the object file as one that requires data to copied from ROM
to RAM at execution startup. Disabled by default.

File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent
9.29.2 Syntax
-------------
* Menu:
* MSP430-Macros:: Macros
* MSP430-Chars:: Special Characters
* MSP430-Regs:: Register Names
* MSP430-Ext:: Assembler Extensions

File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax
9.29.2.1 Macros
...............
The macro syntax used on the MSP 430 is like that described in the MSP
430 Family Assembler Specification. Normal 'as' macros should still
work.
Additional built-in macros are:
'llo(exp)'
Extracts least significant word from 32-bit expression 'exp'.
'lhi(exp)'
Extracts most significant word from 32-bit expression 'exp'.
'hlo(exp)'
Extracts 3rd word from 64-bit expression 'exp'.
'hhi(exp)'
Extracts 4rd word from 64-bit expression 'exp'.
They normally being used as an immediate source operand.
mov #llo(1), r10 ; == mov #1, r10
mov #lhi(1), r10 ; == mov #0, r10

File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax
9.29.2.2 Special Characters
...........................
A semicolon (';') appearing anywhere on a line starts a comment that
extends to the end of that line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but it can also be a logical line number
directive (*note Comments::) or a preprocessor control command (*note
Preprocessing::).
Multiple statements can appear on the same line provided that they
are separated by the '{' character.
The character '$' in jump instructions indicates current location and
implemented only for TI syntax compatibility.

File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax
9.29.2.3 Register Names
.......................
General-purpose registers are represented by predefined symbols of the
form 'rN' (for global registers), where N represents a number between
'0' and '15'. The leading letters may be in either upper or lower case;
for example, 'r13' and 'R7' are both valid register names.
Register names 'PC', 'SP' and 'SR' cannot be used as register names
and will be treated as variables. Use 'r0', 'r1', and 'r2' instead.

File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax
9.29.2.4 Assembler Extensions
.............................
'@rN'
As destination operand being treated as '0(rn)'
'0(rN)'
As source operand being treated as '@rn'
'jCOND +N'
Skips next N bytes followed by jump instruction and equivalent to
'jCOND $+N+2'
Also, there are some instructions, which cannot be found in other
assemblers. These are branch instructions, which has different opcodes
upon jump distance. They all got PC relative addressing mode.
'beq label'
A polymorph instruction which is 'jeq label' in case if jump
distance within allowed range for cpu's jump instruction. If not,
this unrolls into a sequence of
jne $+6
br label
'bne label'
A polymorph instruction which is 'jne label' or 'jeq +4; br label'
'blt label'
A polymorph instruction which is 'jl label' or 'jge +4; br label'
'bltn label'
A polymorph instruction which is 'jn label' or 'jn +2; jmp +4; br
label'
'bltu label'
A polymorph instruction which is 'jlo label' or 'jhs +2; br label'
'bge label'
A polymorph instruction which is 'jge label' or 'jl +4; br label'
'bgeu label'
A polymorph instruction which is 'jhs label' or 'jlo +4; br label'
'bgt label'
A polymorph instruction which is 'jeq +2; jge label' or 'jeq +6; jl
+4; br label'
'bgtu label'
A polymorph instruction which is 'jeq +2; jhs label' or 'jeq +6;
jlo +4; br label'
'bleu label'
A polymorph instruction which is 'jeq label; jlo label' or 'jeq +2;
jhs +4; br label'
'ble label'
A polymorph instruction which is 'jeq label; jl label' or 'jeq +2;
jge +4; br label'
'jump label'
A polymorph instruction which is 'jmp label' or 'br label'

File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent
9.29.3 Floating Point
---------------------
The MSP 430 family uses IEEE 32-bit floating-point numbers.

File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent
9.29.4 MSP 430 Machine Directives
---------------------------------
'.file'
This directive is ignored; it is accepted for compatibility with
other MSP 430 assemblers.
_Warning:_ in other versions of the GNU assembler, '.file' is
used for the directive called '.app-file' in the MSP 430
support.
'.line'
This directive is ignored; it is accepted for compatibility with
other MSP 430 assemblers.
'.arch'
Sets the target microcontroller in the same way as the '-mmcu'
command line option.
'.cpu'
Sets the target architecture in the same way as the '-mcpu' command
line option.
'.profiler'
This directive instructs assembler to add new profile entry to the
object file.
'.refsym'
This directive instructs assembler to add an undefined reference to
the symbol following the directive. The maximum symbol name length
is 1023 characters. No relocation is created for this symbol; it
will exist purely for pulling in object files from archives. Note
that this reloc is not sufficient to prevent garbage collection;
use a KEEP() directive in the linker file to preserve such objects.

File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent
9.29.5 Opcodes
--------------
'as' implements all the standard MSP 430 opcodes. No additional
pseudo-instructions are needed on this family.
For information on the 430 machine instruction set, see 'MSP430
User's Manual, document slau049d', Texas Instrument, Inc.

File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent
9.29.6 Profiling Capability
---------------------------
It is a performance hit to use gcc's profiling approach for this tiny
target. Even more - jtag hardware facility does not perform any
profiling functions. However we've got gdb's built-in simulator where
we can do anything.
We define new section '.profiler' which holds all profiling
information. We define new pseudo operation '.profiler' which will
instruct assembler to add new profile entry to the object file. Profile
should take place at the present address.
Pseudo operation format:
'.profiler flags,function_to_profile [, cycle_corrector, extra]'
where:
'flags' is a combination of the following characters:
's'
function entry
'x'
function exit
'i'
function is in init section
'f'
function is in fini section
'l'
library call
'c'
libc standard call
'd'
stack value demand
'I'
interrupt service routine
'P'
prologue start
'p'
prologue end
'E'
epilogue start
'e'
epilogue end
'j'
long jump / sjlj unwind
'a'
an arbitrary code fragment
't'
extra parameter saved (a constant value like frame size)
'function_to_profile'
a function address
'cycle_corrector'
a value which should be added to the cycle counter, zero if
omitted.
'extra'
any extra parameter, zero if omitted.
For example:
.global fxx
.type fxx,@function
fxx:
.LFrameOffset_fxx=0x08
.profiler "scdP", fxx ; function entry.
; we also demand stack value to be saved
push r11
push r10
push r9
push r8
.profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point
; (this is a prologue end)
; note, that spare var filled with
; the farme size
mov r15,r8
...
.profiler cdE,fxx ; check stack
pop r8
pop r9
pop r10
pop r11
.profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
ret ; cause 'ret' insn takes 3 cycles

File: as.info, Node: NDS32-Dependent, Next: NiosII-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies
9.30 NDS32 Dependent Features
=============================
The NDS32 processors family includes high-performance and low-power
32-bit processors for high-end to low-end. GNU 'as' for NDS32
architectures supports NDS32 ISA version 3. For detail about NDS32
instruction set, please see the AndeStar ISA User Manual which is
availible at http://www.andestech.com/en/index/index.htm
* Menu:
* NDS32 Options:: Assembler options
* NDS32 Syntax:: High-level assembly macros

File: as.info, Node: NDS32 Options, Next: NDS32 Syntax, Up: NDS32-Dependent
9.30.1 NDS32 Options
--------------------
The NDS32 configurations of GNU 'as' support these special options:
'-O1'
Optimize for performance.
'-Os'
Optimize for space.
'-EL'
Produce little endian data output.
'-EB'
Produce little endian data output.
'-mpic'
Generate PIC.
'-mno-fp-as-gp-relax'
Suppress fp-as-gp relaxation for this file.
'-mb2bb-relax'
Back-to-back branch optimization.
'-mno-all-relax'
Suppress all relaxation for this file.
'-march=<arch name>'
Assemble for architecture <arch name> which could be v3, v3j, v3m,
v3f, v3s, v2, v2j, v2f, v2s.
'-mbaseline=<baseline>'
Assemble for baseline <baseline> which could be v2, v3, v3m.
'-mfpu-freg=FREG'
Specify a FPU configuration.
'0 8 SP / 4 DP registers'
'1 16 SP / 8 DP registers'
'2 32 SP / 16 DP registers'
'3 32 SP / 32 DP registers'
'-mabi=ABI'
Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
'-m[no-]mac'
Enable/Disable Multiply instructions support.
'-m[no-]div'
Enable/Disable Divide instructions support.
'-m[no-]16bit-ext'
Enable/Disable 16-bit extension
'-m[no-]dx-regs'
Enable/Disable d0/d1 registers
'-m[no-]perf-ext'
Enable/Disable Performance extension
'-m[no-]perf2-ext'
Enable/Disable Performance extension 2
'-m[no-]string-ext'
Enable/Disable String extension
'-m[no-]reduced-regs'
Enable/Disable Reduced Register configuration (GPR16) option
'-m[no-]audio-isa-ext'
Enable/Disable AUDIO ISA extension
'-m[no-]fpu-sp-ext'
Enable/Disable FPU SP extension
'-m[no-]fpu-dp-ext'
Enable/Disable FPU DP extension
'-m[no-]fpu-fma'
Enable/Disable FPU fused-multiply-add instructions
'-mall-ext'
Turn on all extensions and instructions support

File: as.info, Node: NDS32 Syntax, Prev: NDS32 Options, Up: NDS32-Dependent
9.30.2 Syntax
-------------
* Menu:
* NDS32-Chars:: Special Characters
* NDS32-Regs:: Register Names
* NDS32-Ops:: Pseudo Instructions

File: as.info, Node: NDS32-Chars, Next: NDS32-Regs, Up: NDS32 Syntax
9.30.2.1 Special Characters
...........................
Use '#' at column 1 and '!' anywhere in the line except inside quotes.
Multiple instructions in a line are allowed though not recommended
and should be separated by ';'.
Assembler is not case-sensitive in general except user defined label.
For example, 'jral F1' is different from 'jral f1' while it is the same
as 'JRAL F1'.

File: as.info, Node: NDS32-Regs, Next: NDS32-Ops, Prev: NDS32-Chars, Up: NDS32 Syntax
9.30.2.2 Register Names
.......................
'General purpose registers (GPR)'
There are 32 32-bit general purpose registers $r0 to $r31.
'Accumulators d0 and d1'
64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo.
'Assembler reserved register $ta'
Register $ta ($r15) is reserved for assembler using.
'Operating system reserved registers $p0 and $p1'
Registers $p0 ($r26) and $p1 ($r27) are used by operating system as
scratch registers.
'Frame pointer $fp'
Register $r28 is regarded as the frame pointer.
'Global pointer'
Register $r29 is regarded as the global pointer.
'Link pointer'
Register $r30 is regarded as the link pointer.
'Stack pointer'
Register $r31 is regarded as the stack pointer.

File: as.info, Node: NDS32-Ops, Prev: NDS32-Regs, Up: NDS32 Syntax
9.30.2.3 Pseudo Instructions
............................
'li rt5,imm32'
load 32-bit integer into register rt5. 'sethi rt5,hi20(imm32)' and
then 'ori rt5,reg,lo12(imm32)'.
'la rt5,var'
Load 32-bit address of var into register rt5. 'sethi
rt5,hi20(var)' and then 'ori reg,rt5,lo12(var)'
'l.[bhw] rt5,var'
Load value of var into register rt5. 'sethi $ta,hi20(var)' and
then 'l[bhw]i rt5,[$ta+lo12(var)]'
'l.[bh]s rt5,var'
Load value of var into register rt5. 'sethi $ta,hi20(var)' and
then 'l[bh]si rt5,[$ta+lo12(var)]'
'l.[bhw]p rt5,var,inc'
Load value of var into register rt5 and increment $ta by amount
inc. 'la $ta,var' and then 'l[bhw]i.bi rt5,[$ta],inc'
'l.[bhw]pc rt5,inc'
Continue loading value of var into register rt5 and increment $ta
by amount inc. 'l[bhw]i.bi rt5,[$ta],inc.'
'l.[bh]sp rt5,var,inc'
Load value of var into register rt5 and increment $ta by amount
inc. 'la $ta,var' and then 'l[bh]si.bi rt5,[$ta],inc'
'l.[bh]spc rt5,inc'
Continue loading value of var into register rt5 and increment $ta
by amount inc. 'l[bh]si.bi rt5,[$ta],inc.'
's.[bhw] rt5,var'
Store register rt5 to var. 'sethi $ta,hi20(var)' and then 's[bhw]i
rt5,[$ta+lo12(var)]'
's.[bhw]p rt5,var,inc'
Store register rt5 to var and increment $ta by amount inc. 'la
$ta,var' and then 's[bhw]i.bi rt5,[$ta],inc'
's.[bhw]pc rt5,inc'
Continue storing register rt5 to var and increment $ta by amount
inc. 's[bhw]i.bi rt5,[$ta],inc.'
'not rt5,ra5'
Alias of 'nor rt5,ra5,ra5'.
'neg rt5,ra5'
Alias of 'subri rt5,ra5,0'.
'br rb5'
Depending on how it is assembled, it is translated into 'r5 rb5' or
'jr rb5'.
'b label'
Branch to label depending on how it is assembled, it is translated
into 'j8 label', 'j label', or "'la $ta,label' 'br $ta'".
'bral rb5'
Alias of jral br5 depending on how it is assembled, it is
translated into 'jral5 rb5' or 'jral rb5'.
'bal fname'
Alias of jal fname depending on how it is assembled, it is
translated into 'jal fname' or "'la $ta,fname' 'bral $ta'".
'call fname'
Call function fname same as 'jal fname'.
'move rt5,ra5'
For 16-bit, this is 'mov55 rt5,ra5'. For no 16-bit, this is 'ori
rt5,ra5,0'.
'move rt5,var'
This is the same as 'l.w rt5,var'.
'move rt5,imm32'
This is the same as 'li rt5,imm32'.
'pushm ra5,rb5'
Push contents of registers from ra5 to rb5 into stack.
'push ra5'
Push content of register ra5 into stack. (same 'pushm ra5,ra5').
'push.d var'
Push value of double-word variable var into stack.
'push.w var'
Push value of word variable var into stack.
'push.h var'
Push value of half-word variable var into stack.
'push.b var'
Push value of byte variable var into stack.
'pusha var'
Push 32-bit address of variable var into stack.
'pushi imm32'
Push 32-bit immediate value into stack.
'popm ra5,rb5'
Pop top of stack values into registers ra5 to rb5.
'pop rt5'
Pop top of stack value into register. (same as 'popm rt5,rt5'.)
'pop.d var,ra5'
Pop value of double-word variable var from stack using register ra5
as 2nd scratch register. (1st is $ta)
'pop.w var,ra5'
Pop value of word variable var from stack using register ra5.
'pop.h var,ra5'
Pop value of half-word variable var from stack using register ra5.
'pop.b var,ra5'
Pop value of byte variable var from stack using register ra5.

File: as.info, Node: NiosII-Dependent, Next: NS32K-Dependent, Prev: NDS32-Dependent, Up: Machine Dependencies
9.31 Nios II Dependent Features
===============================
* Menu:
* Nios II Options:: Options
* Nios II Syntax:: Syntax
* Nios II Relocations:: Relocations
* Nios II Directives:: Nios II Machine Directives
* Nios II Opcodes:: Opcodes

File: as.info, Node: Nios II Options, Next: Nios II Syntax, Up: NiosII-Dependent
9.31.1 Options
--------------
'-relax-section'
Replace identified out-of-range branches with PC-relative 'jmp'
sequences when possible. The generated code sequences are suitable
for use in position-independent code, but there is a practical
limit on the extended branch range because of the length of the
sequences. This option is the default.
'-relax-all'
Replace branch instructions not determinable to be in range and all
call instructions with 'jmp' and 'callr' sequences (respectively).
This option generates absolute relocations against the target
symbols and is not appropriate for position-independent code.
'-no-relax'
Do not replace any branches or calls.
'-EB'
Generate big-endian output.
'-EL'
Generate little-endian output. This is the default.

File: as.info, Node: Nios II Syntax, Next: Nios II Relocations, Prev: Nios II Options, Up: NiosII-Dependent
9.31.2 Syntax
-------------
* Menu:
* Nios II Chars:: Special Characters

File: as.info, Node: Nios II Chars, Up: Nios II Syntax
9.31.2.1 Special Characters
...........................
'#' is the line comment character. ';' is the line separator character.

File: as.info, Node: Nios II Relocations, Next: Nios II Directives, Prev: Nios II Syntax, Up: NiosII-Dependent
9.31.3 Nios II Machine Relocations
----------------------------------
'%hiadj(EXPRESSION)'
Extract the upper 16 bits of EXPRESSION and add one if the 15th bit
is set.
The value of '%hiadj(EXPRESSION)' is:
((EXPRESSION >> 16) & 0xffff) + ((EXPRESSION >> 15) & 0x01)
The '%hiadj' relocation is intended to be used with the 'addi',
'ld' or 'st' instructions along with a '%lo', in order to load a
32-bit constant.
movhi r2, %hiadj(symbol)
addi r2, r2, %lo(symbol)
'%hi(EXPRESSION)'
Extract the upper 16 bits of EXPRESSION.
'%lo(EXPRESSION)'
Extract the lower 16 bits of EXPRESSION.
'%gprel(EXPRESSION)'
Subtract the value of the symbol '_gp' from EXPRESSION.
The intention of the '%gprel' relocation is to have a fast small
area of memory which only takes a 16-bit immediate to access.
.section .sdata
fastint:
.int 123
.section .text
ldw r4, %gprel(fastint)(gp)
'%call(EXPRESSION)'
'%call_lo(EXPRESSION)'
'%call_hiadj(EXPRESSION)'
'%got(EXPRESSION)'
'%got_lo(EXPRESSION)'
'%got_hiadj(EXPRESSION)'
'%gotoff(EXPRESSION)'
'%gotoff_lo(EXPRESSION)'
'%gotoff_hiadj(EXPRESSION)'
'%tls_gd(EXPRESSION)'
'%tls_ie(EXPRESSION)'
'%tls_le(EXPRESSION)'
'%tls_ldm(EXPRESSION)'
'%tls_ldo(EXPRESSION)'
These relocations support the ABI for Linux Systems documented in
the 'Nios II Processor Reference Handbook'.

File: as.info, Node: Nios II Directives, Next: Nios II Opcodes, Prev: Nios II Relocations, Up: NiosII-Dependent
9.31.4 Nios II Machine Directives
---------------------------------
'.align EXPRESSION [, EXPRESSION]'
This is the generic '.align' directive, however this aligns to a
power of two.
'.half EXPRESSION'
Create an aligned constant 2 bytes in size.
'.word EXPRESSION'
Create an aligned constant 4 bytes in size.
'.dword EXPRESSION'
Create an aligned constant 8 bytes in size.
'.2byte EXPRESSION'
Create an unaligned constant 2 bytes in size.
'.4byte EXPRESSION'
Create an unaligned constant 4 bytes in size.
'.8byte EXPRESSION'
Create an unaligned constant 8 bytes in size.
'.16byte EXPRESSION'
Create an unaligned constant 16 bytes in size.
'.set noat'
Allows assembly code to use 'at' register without warning. Macro
or relaxation expansions generate warnings.
'.set at'
Assembly code using 'at' register generates warnings, and macro
expansion and relaxation are enabled.
'.set nobreak'
Allows assembly code to use 'ba' and 'bt' registers without
warning.
'.set break'
Turns warnings back on for using 'ba' and 'bt' registers.
'.set norelax'
Do not replace any branches or calls.
'.set relaxsection'
Replace identified out-of-range branches with 'jmp' sequences
(default).
'.set relaxsection'
Replace all branch and call instructions with 'jmp' and 'callr'
sequences.
'.set ...'
All other '.set' are the normal use.

File: as.info, Node: Nios II Opcodes, Prev: Nios II Directives, Up: NiosII-Dependent
9.31.5 Opcodes
--------------
'as' implements all the standard Nios II opcodes documented in the 'Nios
II Processor Reference Handbook', including the assembler
pseudo-instructions.

File: as.info, Node: NS32K-Dependent, Next: PDP-11-Dependent, Prev: NiosII-Dependent, Up: Machine Dependencies
9.32 NS32K Dependent Features
=============================
* Menu:
* NS32K Syntax:: Syntax

File: as.info, Node: NS32K Syntax, Up: NS32K-Dependent
9.32.1 Syntax
-------------
* Menu:
* NS32K-Chars:: Special Characters

File: as.info, Node: NS32K-Chars, Up: NS32K Syntax
9.32.1.1 Special Characters
...........................
The presence of a '#' appearing anywhere on a line indicates the start
of a comment that extends to the end of that line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
If Sequent compatibility has been configured into the assembler then
the '|' character appearing as the first character on a line will also
indicate the start of a line comment.
The ';' character can be used to separate statements on the same
line.

File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: NS32K-Dependent, Up: Machine Dependencies
9.33 PDP-11 Dependent Features
==============================
* Menu:
* PDP-11-Options:: Options
* PDP-11-Pseudos:: Assembler Directives
* PDP-11-Syntax:: DEC Syntax versus BSD Syntax
* PDP-11-Mnemonics:: Instruction Naming
* PDP-11-Synthetic:: Synthetic Instructions

File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent
9.33.1 Options
--------------
The PDP-11 version of 'as' has a rich set of machine dependent options.
9.33.1.1 Code Generation Options
................................
'-mpic | -mno-pic'
Generate position-independent (or position-dependent) code.
The default is to generate position-independent code.
9.33.1.2 Instruction Set Extension Options
..........................................
These options enables or disables the use of extensions over the base
line instruction set as introduced by the first PDP-11 CPU: the KA11.
Most options come in two variants: a '-m'EXTENSION that enables
EXTENSION, and a '-mno-'EXTENSION that disables EXTENSION.
The default is to enable all extensions.
'-mall | -mall-extensions'
Enable all instruction set extensions.
'-mno-extensions'
Disable all instruction set extensions.
'-mcis | -mno-cis'
Enable (or disable) the use of the commercial instruction set,
which consists of these instructions: 'ADDNI', 'ADDN', 'ADDPI',
'ADDP', 'ASHNI', 'ASHN', 'ASHPI', 'ASHP', 'CMPCI', 'CMPC', 'CMPNI',
'CMPN', 'CMPPI', 'CMPP', 'CVTLNI', 'CVTLN', 'CVTLPI', 'CVTLP',
'CVTNLI', 'CVTNL', 'CVTNPI', 'CVTNP', 'CVTPLI', 'CVTPL', 'CVTPNI',
'CVTPN', 'DIVPI', 'DIVP', 'L2DR', 'L3DR', 'LOCCI', 'LOCC', 'MATCI',
'MATC', 'MOVCI', 'MOVC', 'MOVRCI', 'MOVRC', 'MOVTCI', 'MOVTC',
'MULPI', 'MULP', 'SCANCI', 'SCANC', 'SKPCI', 'SKPC', 'SPANCI',
'SPANC', 'SUBNI', 'SUBN', 'SUBPI', and 'SUBP'.
'-mcsm | -mno-csm'
Enable (or disable) the use of the 'CSM' instruction.
'-meis | -mno-eis'
Enable (or disable) the use of the extended instruction set, which
consists of these instructions: 'ASHC', 'ASH', 'DIV', 'MARK',
'MUL', 'RTT', 'SOB' 'SXT', and 'XOR'.
'-mfis | -mkev11'
'-mno-fis | -mno-kev11'
Enable (or disable) the use of the KEV11 floating-point
instructions: 'FADD', 'FDIV', 'FMUL', and 'FSUB'.
'-mfpp | -mfpu | -mfp-11'
'-mno-fpp | -mno-fpu | -mno-fp-11'
Enable (or disable) the use of FP-11 floating-point instructions:
'ABSF', 'ADDF', 'CFCC', 'CLRF', 'CMPF', 'DIVF', 'LDCFF', 'LDCIF',
'LDEXP', 'LDF', 'LDFPS', 'MODF', 'MULF', 'NEGF', 'SETD', 'SETF',
'SETI', 'SETL', 'STCFF', 'STCFI', 'STEXP', 'STF', 'STFPS', 'STST',
'SUBF', and 'TSTF'.
'-mlimited-eis | -mno-limited-eis'
Enable (or disable) the use of the limited extended instruction
set: 'MARK', 'RTT', 'SOB', 'SXT', and 'XOR'.
The -mno-limited-eis options also implies -mno-eis.
'-mmfpt | -mno-mfpt'
Enable (or disable) the use of the 'MFPT' instruction.
'-mmultiproc | -mno-multiproc'
Enable (or disable) the use of multiprocessor instructions:
'TSTSET' and 'WRTLCK'.
'-mmxps | -mno-mxps'
Enable (or disable) the use of the 'MFPS' and 'MTPS' instructions.
'-mspl | -mno-spl'
Enable (or disable) the use of the 'SPL' instruction.
Enable (or disable) the use of the microcode instructions: 'LDUB',
'MED', and 'XFC'.
9.33.1.3 CPU Model Options
..........................
These options enable the instruction set extensions supported by a
particular CPU, and disables all other extensions.
'-mka11'
KA11 CPU. Base line instruction set only.
'-mkb11'
KB11 CPU. Enable extended instruction set and 'SPL'.
'-mkd11a'
KD11-A CPU. Enable limited extended instruction set.
'-mkd11b'
KD11-B CPU. Base line instruction set only.
'-mkd11d'
KD11-D CPU. Base line instruction set only.
'-mkd11e'
KD11-E CPU. Enable extended instruction set, 'MFPS', and 'MTPS'.
'-mkd11f | -mkd11h | -mkd11q'
KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction
set, 'MFPS', and 'MTPS'.
'-mkd11k'
KD11-K CPU. Enable extended instruction set, 'LDUB', 'MED', 'MFPS',
'MFPT', 'MTPS', and 'XFC'.
'-mkd11z'
KD11-Z CPU. Enable extended instruction set, 'CSM', 'MFPS', 'MFPT',
'MTPS', and 'SPL'.
'-mf11'
F11 CPU. Enable extended instruction set, 'MFPS', 'MFPT', and
'MTPS'.
'-mj11'
J11 CPU. Enable extended instruction set, 'CSM', 'MFPS', 'MFPT',
'MTPS', 'SPL', 'TSTSET', and 'WRTLCK'.
'-mt11'
T11 CPU. Enable limited extended instruction set, 'MFPS', and
'MTPS'.
9.33.1.4 Machine Model Options
..............................
These options enable the instruction set extensions supported by a
particular machine model, and disables all other extensions.
'-m11/03'
Same as '-mkd11f'.
'-m11/04'
Same as '-mkd11d'.
'-m11/05 | -m11/10'
Same as '-mkd11b'.
'-m11/15 | -m11/20'
Same as '-mka11'.
'-m11/21'
Same as '-mt11'.
'-m11/23 | -m11/24'
Same as '-mf11'.
'-m11/34'
Same as '-mkd11e'.
'-m11/34a'
Ame as '-mkd11e' '-mfpp'.
'-m11/35 | -m11/40'
Same as '-mkd11a'.
'-m11/44'
Same as '-mkd11z'.
'-m11/45 | -m11/50 | -m11/55 | -m11/70'
Same as '-mkb11'.
'-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94'
Same as '-mj11'.
'-m11/60'
Same as '-mkd11k'.

File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent
9.33.2 Assembler Directives
---------------------------
The PDP-11 version of 'as' has a few machine dependent assembler
directives.
'.bss'
Switch to the 'bss' section.
'.even'
Align the location counter to an even number.

File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent
9.33.3 PDP-11 Assembly Language Syntax
--------------------------------------
'as' supports both DEC syntax and BSD syntax. The only difference is
that in DEC syntax, a '#' character is used to denote an immediate
constants, while in BSD syntax the character for this purpose is '$'.
general-purpose registers are named 'r0' through 'r7'. Mnemonic
alternatives for 'r6' and 'r7' are 'sp' and 'pc', respectively.
Floating-point registers are named 'ac0' through 'ac3', or
alternatively 'fr0' through 'fr3'.
Comments are started with a '#' or a '/' character, and extend to the
end of the line. (FIXME: clash with immediates?)
Multiple statements on the same line can be separated by the ';'
character.

File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent
9.33.4 Instruction Naming
-------------------------
Some instructions have alternative names.
'BCC'
'BHIS'
'BCS'
'BLO'
'L2DR'
'L2D'
'L3DR'
'L3D'
'SYS'
'TRAP'

File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent
9.33.5 Synthetic Instructions
-----------------------------
The 'JBR' and 'J'CC synthetic instructions are not supported yet.

File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies
9.34 picoJava Dependent Features
================================
* Menu:
* PJ Options:: Options
* PJ Syntax:: PJ Syntax

File: as.info, Node: PJ Options, Next: PJ Syntax, Up: PJ-Dependent
9.34.1 Options
--------------
'as' has two additional command-line options for the picoJava
architecture.
'-ml'
This option selects little endian data output.
'-mb'
This option selects big endian data output.

File: as.info, Node: PJ Syntax, Prev: PJ Options, Up: PJ-Dependent
9.34.2 PJ Syntax
----------------
* Menu:
* PJ-Chars:: Special Characters

File: as.info, Node: PJ-Chars, Up: PJ Syntax
9.34.2.1 Special Characters
...........................
The presence of a '!' or '/' on a line indicates the start of a comment
that extends to the end of the current line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line could also be a
logical line number directive (*note Comments::) or a preprocessor
control command (*note Preprocessing::).
The ';' character can be used to separate statements on the same
line.

File: as.info, Node: PPC-Dependent, Next: RL78-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies
9.35 PowerPC Dependent Features
===============================
* Menu:
* PowerPC-Opts:: Options
* PowerPC-Pseudo:: PowerPC Assembler Directives
* PowerPC-Syntax:: PowerPC Syntax

File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent
9.35.1 Options
--------------
The PowerPC chip family includes several successive levels, using the
same core instruction set, but including a few additional instructions
at each level. There are exceptions to this however. For details on
what instructions each variant supports, please see the chip's
architecture reference manual.
The following table lists all available PowerPC options.
'-a32'
Generate ELF32 or XCOFF32.
'-a64'
Generate ELF64 or XCOFF64.
'-K PIC'
Set EF_PPC_RELOCATABLE_LIB in ELF flags.
'-mpwrx | -mpwr2'
Generate code for POWER/2 (RIOS2).
'-mpwr'
Generate code for POWER (RIOS1)
'-m601'
Generate code for PowerPC 601.
'-mppc, -mppc32, -m603, -m604'
Generate code for PowerPC 603/604.
'-m403, -m405'
Generate code for PowerPC 403/405.
'-m440'
Generate code for PowerPC 440. BookE and some 405 instructions.
'-m464'
Generate code for PowerPC 464.
'-m476'
Generate code for PowerPC 476.
'-m7400, -m7410, -m7450, -m7455'
Generate code for PowerPC 7400/7410/7450/7455.
'-m750cl'
Generate code for PowerPC 750CL.
'-mppc64, -m620'
Generate code for PowerPC 620/625/630.
'-me500, -me500x2'
Generate code for Motorola e500 core complex.
'-me500mc'
Generate code for Freescale e500mc core complex.
'-me500mc64'
Generate code for Freescale e500mc64 core complex.
'-me5500'
Generate code for Freescale e5500 core complex.
'-me6500'
Generate code for Freescale e6500 core complex.
'-mspe'
Generate code for Motorola SPE instructions.
'-mtitan'
Generate code for AppliedMicro Titan core complex.
'-mppc64bridge'
Generate code for PowerPC 64, including bridge insns.
'-mbooke'
Generate code for 32-bit BookE.
'-ma2'
Generate code for A2 architecture.
'-me300'
Generate code for PowerPC e300 family.
'-maltivec'
Generate code for processors with AltiVec instructions.
'-mvle'
Generate code for Freescale PowerPC VLE instructions.
'-mvsx'
Generate code for processors with Vector-Scalar (VSX) instructions.
'-mhtm'
Generate code for processors with Hardware Transactional Memory
instructions.
'-mpower4, -mpwr4'
Generate code for Power4 architecture.
'-mpower5, -mpwr5, -mpwr5x'
Generate code for Power5 architecture.
'-mpower6, -mpwr6'
Generate code for Power6 architecture.
'-mpower7, -mpwr7'
Generate code for Power7 architecture.
'-mpower8, -mpwr8'
Generate code for Power8 architecture.
'-mcell'
'-mcell'
Generate code for Cell Broadband Engine architecture.
'-mcom'
Generate code Power/PowerPC common instructions.
'-many'
Generate code for any architecture (PWR/PWRX/PPC).
'-mregnames'
Allow symbolic names for registers.
'-mno-regnames'
Do not allow symbolic names for registers.
'-mrelocatable'
Support for GCC's -mrelocatable option.
'-mrelocatable-lib'
Support for GCC's -mrelocatable-lib option.
'-memb'
Set PPC_EMB bit in ELF flags.
'-mlittle, -mlittle-endian, -le'
Generate code for a little endian machine.
'-mbig, -mbig-endian, -be'
Generate code for a big endian machine.
'-msolaris'
Generate code for Solaris.
'-mno-solaris'
Do not generate code for Solaris.
'-nops=COUNT'
If an alignment directive inserts more than COUNT nops, put a
branch at the beginning to skip execution of the nops.

File: as.info, Node: PowerPC-Pseudo, Next: PowerPC-Syntax, Prev: PowerPC-Opts, Up: PPC-Dependent
9.35.2 PowerPC Assembler Directives
-----------------------------------
A number of assembler directives are available for PowerPC. The
following table is far from complete.
'.machine "string"'
This directive allows you to change the machine for which code is
generated. '"string"' may be any of the -m cpu selection options
(without the -m) enclosed in double quotes, '"push"', or '"pop"'.
'.machine "push"' saves the currently selected cpu, which may be
restored with '.machine "pop"'.

File: as.info, Node: PowerPC-Syntax, Prev: PowerPC-Pseudo, Up: PPC-Dependent
9.35.3 PowerPC Syntax
---------------------
* Menu:
* PowerPC-Chars:: Special Characters

File: as.info, Node: PowerPC-Chars, Up: PowerPC-Syntax
9.35.3.1 Special Characters
...........................
The presence of a '#' on a line indicates the start of a comment that
extends to the end of the current line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line could also be a
logical line number directive (*note Comments::) or a preprocessor
control command (*note Preprocessing::).
If the assembler has been configured for the ppc-*-solaris* target
then the '!' character also acts as a line comment character. This can
be disabled via the '-mno-solaris' command line option.
The ';' character can be used to separate statements on the same
line.

File: as.info, Node: RL78-Dependent, Next: RX-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies
9.36 RL78 Dependent Features
============================
* Menu:
* RL78-Opts:: RL78 Assembler Command Line Options
* RL78-Modifiers:: Symbolic Operand Modifiers
* RL78-Directives:: Assembler Directives
* RL78-Syntax:: Syntax

File: as.info, Node: RL78-Opts, Next: RL78-Modifiers, Up: RL78-Dependent
9.36.1 RL78 Options
-------------------
'relax'
Enable support for link-time relaxation.
'mg10'
Mark the generated binary as targeting the G10 variant of the RL78
architecture.
'm32bit-doubles'
Mark the generated binary as one that uses 32-bits to hold the
'double' floating point type. This is the default.
'm64bit-doubles'
Mark the generated binary as one that uses 64-bits to hold the
'double' floating point type.

File: as.info, Node: RL78-Modifiers, Next: RL78-Directives, Prev: RL78-Opts, Up: RL78-Dependent
9.36.2 Symbolic Operand Modifiers
---------------------------------
The RL78 has three modifiers that adjust the relocations used by the
linker:
'%lo16()'
When loading a 20-bit (or wider) address into registers, this
modifier selects the 16 least significant bits.
movw ax,#%lo16(_sym)
'%hi16()'
When loading a 20-bit (or wider) address into registers, this
modifier selects the 16 most significant bits.
movw ax,#%hi16(_sym)
'%hi8()'
When loading a 20-bit (or wider) address into registers, this
modifier selects the 8 bits that would go into CS or ES (i.e. bits
23..16).
mov es, #%hi8(_sym)

File: as.info, Node: RL78-Directives, Next: RL78-Syntax, Prev: RL78-Modifiers, Up: RL78-Dependent
9.36.3 Assembler Directives
---------------------------
In addition to the common directives, the RL78 adds these:
'.double'
Output a constant in "double" format, which is either a 32-bit or a
64-bit floating point value, depending upon the setting of the
'-m32bit-doubles'|'-m64bit-doubles' command line option.
'.bss'
Select the BSS section.
'.3byte'
Output a constant value in a three byte format.
'.int'
'.word'
Output a constant value in a four byte format.

File: as.info, Node: RL78-Syntax, Prev: RL78-Directives, Up: RL78-Dependent
9.36.4 Syntax for the RL78
--------------------------
* Menu:
* RL78-Chars:: Special Characters

File: as.info, Node: RL78-Chars, Up: RL78-Syntax
9.36.4.1 Special Characters
...........................
The presence of a ';' appearing anywhere on a line indicates the start
of a comment that extends to the end of that line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
The '|' character can be used to separate statements on the same
line.

File: as.info, Node: RX-Dependent, Next: S/390-Dependent, Prev: RL78-Dependent, Up: Machine Dependencies
9.37 RX Dependent Features
==========================
* Menu:
* RX-Opts:: RX Assembler Command Line Options
* RX-Modifiers:: Symbolic Operand Modifiers
* RX-Directives:: Assembler Directives
* RX-Float:: Floating Point
* RX-Syntax:: Syntax

File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent
9.37.1 RX Options
-----------------
The Renesas RX port of 'as' has a few target specfic command line
options:
'-m32bit-doubles'
This option controls the ABI and indicates to use a 32-bit float
ABI. It has no effect on the assembled instructions, but it does
influence the behaviour of the '.double' pseudo-op. This is the
default.
'-m64bit-doubles'
This option controls the ABI and indicates to use a 64-bit float
ABI. It has no effect on the assembled instructions, but it does
influence the behaviour of the '.double' pseudo-op.
'-mbig-endian'
This option controls the ABI and indicates to use a big-endian data
ABI. It has no effect on the assembled instructions, but it does
influence the behaviour of the '.short', '.hword', '.int', '.word',
'.long', '.quad' and '.octa' pseudo-ops.
'-mlittle-endian'
This option controls the ABI and indicates to use a little-endian
data ABI. It has no effect on the assembled instructions, but it
does influence the behaviour of the '.short', '.hword', '.int',
'.word', '.long', '.quad' and '.octa' pseudo-ops. This is the
default.
'-muse-conventional-section-names'
This option controls the default names given to the code (.text),
initialised data (.data) and uninitialised data sections (.bss).
'-muse-renesas-section-names'
This option controls the default names given to the code (.P),
initialised data (.D_1) and uninitialised data sections (.B_1).
This is the default.
'-msmall-data-limit'
This option tells the assembler that the small data limit feature
of the RX port of GCC is being used. This results in the assembler
generating an undefined reference to a symbol called '__gp' for use
by the relocations that are needed to support the small data limit
feature. This option is not enabled by default as it would
otherwise pollute the symbol table.
'-mpid'
This option tells the assembler that the position independent data
of the RX port of GCC is being used. This results in the assembler
generating an undefined reference to a symbol called '__pid_base',
and also setting the RX_PID flag bit in the e_flags field of the
ELF header of the object file.
'-mint-register=NUM'
This option tells the assembler how many registers have been
reserved for use by interrupt handlers. This is needed in order to
compute the correct values for the '%gpreg' and '%pidreg' meta
registers.
'-mgcc-abi'
This option tells the assembler that the old GCC ABI is being used
by the assembled code. With this version of the ABI function
arguments that are passed on the stack are aligned to a 32-bit
boundary.
'-mrx-abi'
This option tells the assembler that the official RX ABI is being
used by the assembled code. With this version of the ABI function
arguments that are passed on the stack are aligned to their natural
alignments. This option is the default.
'-mcpu=NAME'
This option tells the assembler the target CPU type. Currently the
'rx200', 'rx600' and 'rx610' are recognised as valid cpu names.
Attempting to assemble an instruction not supported by the
indicated cpu type will result in an error message being generated.

File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent
9.37.2 Symbolic Operand Modifiers
---------------------------------
The assembler supports one modifier when using symbol addresses in RX
instruction operands. The general syntax is the following:
%gp(symbol)
The modifier returns the offset from the __GP symbol to the specified
symbol as a 16-bit value. The intent is that this offset should be used
in a register+offset move instruction when generating references to
small data. Ie, like this:
mov.W %gp(_foo)[%gpreg], r1
The assembler also supports two meta register names which can be used
to refer to registers whose values may not be known to the programmer.
These meta register names are:
'%gpreg'
The small data address register.
'%pidreg'
The PID base address register.
Both registers normally have the value r13, but this can change if
some registers have been reserved for use by interrupt handlers or if
both the small data limit and position independent data features are
being used at the same time.

File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: RX-Dependent
9.37.3 Assembler Directives
---------------------------
The RX version of 'as' has the following specific assembler directives:
'.3byte'
Inserts a 3-byte value into the output file at the current
location.
'.fetchalign'
If the next opcode following this directive spans a fetch line
boundary (8 byte boundary), the opcode is aligned to that boundary.
If the next opcode does not span a fetch line, this directive has
no effect. Note that one or more labels may be between this
directive and the opcode; those labels are aligned as well. Any
inserted bytes due to alignment will form a NOP opcode.

File: as.info, Node: RX-Float, Next: RX-Syntax, Prev: RX-Directives, Up: RX-Dependent
9.37.4 Floating Point
---------------------
The floating point formats generated by directives are these.
'.float'
'Single' precision (32-bit) floating point constants.
'.double'
If the '-m64bit-doubles' command line option has been specified
then then 'double' directive generates 'double' precision (64-bit)
floating point constants, otherwise it generates 'single' precision
(32-bit) floating point constants. To force the generation of
64-bit floating point constants used the 'dc.d' directive instead.

File: as.info, Node: RX-Syntax, Prev: RX-Float, Up: RX-Dependent
9.37.5 Syntax for the RX
------------------------
* Menu:
* RX-Chars:: Special Characters

File: as.info, Node: RX-Chars, Up: RX-Syntax
9.37.5.1 Special Characters
...........................
The presence of a ';' appearing anywhere on a line indicates the start
of a comment that extends to the end of that line.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line can also be a logical
line number directive (*note Comments::) or a preprocessor control
command (*note Preprocessing::).
The '!' character can be used to separate statements on the same
line.

File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Dependent, Up: Machine Dependencies
9.38 IBM S/390 Dependent Features
=================================
The s390 version of 'as' supports two architectures modes and seven chip
levels. The architecture modes are the Enterprise System Architecture
(ESA) and the newer z/Architecture mode. The chip levels are g5, g6,
z900, z990, z9-109, z9-ec, z10, z196, and zEC12.
* Menu:
* s390 Options:: Command-line Options.
* s390 Characters:: Special Characters.
* s390 Syntax:: Assembler Instruction syntax.
* s390 Directives:: Assembler Directives.
* s390 Floating Point:: Floating Point.

File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent
9.38.1 Options
--------------
The following table lists all available s390 specific options:
'-m31 | -m64'
Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.
These options are only available with the ELF object file format,
and require that the necessary BFD support has been included (on a
31-bit platform you must add -enable-64-bit-bfd on the call to the
configure script to enable 64-bit usage and use s390x as target
platform).
'-mesa | -mzarch'
Select the architecture mode, either the Enterprise System
Architecture (esa) mode or the z/Architecture mode (zarch).
The 64-bit instructions are only available with the z/Architecture
mode. The combination of '-m64' and '-mesa' results in a warning
message.
'-march=CPU'
This option specifies the target processor. The following
processor names are recognized: 'g5', 'g6', 'z900', 'z990',
'z9-109', 'z9-ec', 'z10' and 'z196'. Assembling an instruction
that is not supported on the target processor results in an error
message. Do not specify 'g5' or 'g6' with '-mzarch'.
'-mregnames'
Allow symbolic names for registers.
'-mno-regnames'
Do not allow symbolic names for registers.
'-mwarn-areg-zero'
Warn whenever the operand for a base or index register has been
specified but evaluates to zero. This can indicate the misuse of
general purpose register 0 as an address register.

File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent
9.38.2 Special Characters
-------------------------
'#' is the line comment character.
If a '#' appears as the first character of a line then the whole line
is treated as a comment, but in this case the line could also be a
logical line number directive (*note Comments::) or a preprocessor
control command (*note Preprocessing::).
The ';' character can be used instead of a newline to separate
statements.