| /* |
| * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| |
| #include <arch.h> |
| #include <asm_macros.S> |
| #include <common/bl_common.h> |
| |
| .globl bl2u_entrypoint |
| |
| |
| func bl2u_entrypoint |
| /*--------------------------------------------- |
| * Store the extents of the tzram available to |
| * BL2U and other platform specific information |
| * for future use. x0 is currently not used. |
| * --------------------------------------------- |
| */ |
| mov x20, x1 |
| mov x21, x2 |
| |
| /* --------------------------------------------- |
| * Set the exception vector to something sane. |
| * --------------------------------------------- |
| */ |
| adr x0, early_exceptions |
| msr vbar_el1, x0 |
| isb |
| |
| /* --------------------------------------------- |
| * Enable the SError interrupt now that the |
| * exception vectors have been setup. |
| * --------------------------------------------- |
| */ |
| msr daifclr, #DAIF_ABT_BIT |
| |
| /* --------------------------------------------- |
| * Enable the instruction cache, stack pointer |
| * and data access alignment checks and disable |
| * speculative loads. |
| * --------------------------------------------- |
| */ |
| mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) |
| mrs x0, sctlr_el1 |
| orr x0, x0, x1 |
| bic x0, x0, #SCTLR_DSSBS_BIT |
| msr sctlr_el1, x0 |
| isb |
| |
| /* --------------------------------------------- |
| * Invalidate the RW memory used by the BL2U |
| * image. This includes the data and NOBITS |
| * sections. This is done to safeguard against |
| * possible corruption of this memory by dirty |
| * cache lines in a system cache as a result of |
| * use by an earlier boot loader stage. |
| * --------------------------------------------- |
| */ |
| adr x0, __RW_START__ |
| adr x1, __RW_END__ |
| sub x1, x1, x0 |
| bl inv_dcache_range |
| |
| /* --------------------------------------------- |
| * Zero out NOBITS sections. There are 2 of them: |
| * - the .bss section; |
| * - the coherent memory section. |
| * --------------------------------------------- |
| */ |
| adrp x0, __BSS_START__ |
| add x0, x0, :lo12:__BSS_START__ |
| adrp x1, __BSS_END__ |
| add x1, x1, :lo12:__BSS_END__ |
| sub x1, x1, x0 |
| bl zeromem |
| |
| /* -------------------------------------------- |
| * Allocate a stack whose memory will be marked |
| * as Normal-IS-WBWA when the MMU is enabled. |
| * There is no risk of reading stale stack |
| * memory after enabling the MMU as only the |
| * primary cpu is running at the moment. |
| * -------------------------------------------- |
| */ |
| bl plat_set_my_stack |
| |
| /* --------------------------------------------- |
| * Initialize the stack protector canary before |
| * any C code is called. |
| * --------------------------------------------- |
| */ |
| #if STACK_PROTECTOR_ENABLED |
| bl update_stack_protector_canary |
| #endif |
| |
| /* --------------------------------------------- |
| * Perform early platform setup & platform |
| * specific early arch. setup e.g. mmu setup |
| * --------------------------------------------- |
| */ |
| mov x0, x20 |
| mov x1, x21 |
| bl bl2u_early_platform_setup |
| bl bl2u_plat_arch_setup |
| |
| #if ENABLE_PAUTH |
| /* --------------------------------------------- |
| * Program APIAKey_EL1 |
| * and enable pointer authentication. |
| * --------------------------------------------- |
| */ |
| bl pauth_init_enable_el1 |
| #endif |
| |
| /* --------------------------------------------- |
| * Jump to bl2u_main function. |
| * --------------------------------------------- |
| */ |
| bl bl2u_main |
| |
| /* --------------------------------------------- |
| * Should never reach this point. |
| * --------------------------------------------- |
| */ |
| no_ret plat_panic_handler |
| |
| endfunc bl2u_entrypoint |
