| // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| /* |
| * Copyright (C) 2024, STMicroelectronics - All Rights Reserved |
| */ |
| |
| &ddr{ |
| st,mem-name = DDR_MEM_NAME; |
| st,mem-speed = <DDR_MEM_SPEED>; |
| st,mem-size = <(DDR_MEM_SIZE >> 32) (DDR_MEM_SIZE & 0xFFFFFFFF)>; |
| |
| st,ctl-reg = < |
| DDR_MSTR |
| DDR_MRCTRL0 |
| DDR_MRCTRL1 |
| DDR_MRCTRL2 |
| DDR_DERATEEN |
| DDR_DERATEINT |
| DDR_DERATECTL |
| DDR_PWRCTL |
| DDR_PWRTMG |
| DDR_HWLPCTL |
| DDR_RFSHCTL0 |
| DDR_RFSHCTL1 |
| DDR_RFSHCTL3 |
| DDR_CRCPARCTL0 |
| DDR_CRCPARCTL1 |
| DDR_INIT0 |
| DDR_INIT1 |
| DDR_INIT2 |
| DDR_INIT3 |
| DDR_INIT4 |
| DDR_INIT5 |
| DDR_INIT6 |
| DDR_INIT7 |
| DDR_DIMMCTL |
| DDR_RANKCTL |
| DDR_RANKCTL1 |
| DDR_ZQCTL0 |
| DDR_ZQCTL1 |
| DDR_ZQCTL2 |
| DDR_DFITMG0 |
| DDR_DFITMG1 |
| DDR_DFILPCFG0 |
| DDR_DFILPCFG1 |
| DDR_DFIUPD0 |
| DDR_DFIUPD1 |
| DDR_DFIUPD2 |
| DDR_DFIMISC |
| DDR_DFITMG2 |
| DDR_DFITMG3 |
| DDR_DBICTL |
| DDR_DFIPHYMSTR |
| DDR_DBG0 |
| DDR_DBG1 |
| DDR_DBGCMD |
| DDR_SWCTL |
| DDR_SWCTLSTATIC |
| DDR_POISONCFG |
| DDR_PCCFG |
| >; |
| |
| st,ctl-timing = < |
| DDR_RFSHTMG |
| DDR_RFSHTMG1 |
| DDR_DRAMTMG0 |
| DDR_DRAMTMG1 |
| DDR_DRAMTMG2 |
| DDR_DRAMTMG3 |
| DDR_DRAMTMG4 |
| DDR_DRAMTMG5 |
| DDR_DRAMTMG6 |
| DDR_DRAMTMG7 |
| DDR_DRAMTMG8 |
| DDR_DRAMTMG9 |
| DDR_DRAMTMG10 |
| DDR_DRAMTMG11 |
| DDR_DRAMTMG12 |
| DDR_DRAMTMG13 |
| DDR_DRAMTMG14 |
| DDR_DRAMTMG15 |
| DDR_ODTCFG |
| DDR_ODTMAP |
| >; |
| |
| st,ctl-map = < |
| DDR_ADDRMAP0 |
| DDR_ADDRMAP1 |
| DDR_ADDRMAP2 |
| DDR_ADDRMAP3 |
| DDR_ADDRMAP4 |
| DDR_ADDRMAP5 |
| DDR_ADDRMAP6 |
| DDR_ADDRMAP7 |
| DDR_ADDRMAP8 |
| DDR_ADDRMAP9 |
| DDR_ADDRMAP10 |
| DDR_ADDRMAP11 |
| >; |
| |
| st,ctl-perf = < |
| DDR_SCHED |
| DDR_SCHED1 |
| DDR_PERFHPR1 |
| DDR_PERFLPR1 |
| DDR_PERFWR1 |
| DDR_SCHED3 |
| DDR_SCHED4 |
| DDR_PCFGR_0 |
| DDR_PCFGW_0 |
| DDR_PCTRL_0 |
| DDR_PCFGQOS0_0 |
| DDR_PCFGQOS1_0 |
| DDR_PCFGWQOS0_0 |
| DDR_PCFGWQOS1_0 |
| DDR_PCFGR_1 |
| DDR_PCFGW_1 |
| DDR_PCTRL_1 |
| DDR_PCFGQOS0_1 |
| DDR_PCFGQOS1_1 |
| DDR_PCFGWQOS0_1 |
| DDR_PCFGWQOS1_1 |
| >; |
| |
| st,phy-basic = < |
| DDR_UIB_DRAMTYPE |
| DDR_UIB_DIMMTYPE |
| DDR_UIB_LP4XMODE |
| DDR_UIB_NUMDBYTE |
| DDR_UIB_NUMACTIVEDBYTEDFI0 |
| DDR_UIB_NUMACTIVEDBYTEDFI1 |
| DDR_UIB_NUMANIB |
| DDR_UIB_NUMRANK_DFI0 |
| DDR_UIB_NUMRANK_DFI1 |
| DDR_UIB_DRAMDATAWIDTH |
| DDR_UIB_NUMPSTATES |
| DDR_UIB_FREQUENCY_0 |
| DDR_UIB_PLLBYPASS_0 |
| DDR_UIB_DFIFREQRATIO_0 |
| DDR_UIB_DFI1EXISTS |
| DDR_UIB_TRAIN2D |
| DDR_UIB_HARDMACROVER |
| DDR_UIB_READDBIENABLE_0 |
| DDR_UIB_DFIMODE |
| >; |
| |
| st,phy-advanced = < |
| DDR_UIA_LP4RXPREAMBLEMODE_0 |
| DDR_UIA_LP4POSTAMBLEEXT_0 |
| DDR_UIA_D4RXPREAMBLELENGTH_0 |
| DDR_UIA_D4TXPREAMBLELENGTH_0 |
| DDR_UIA_EXTCALRESVAL |
| DDR_UIA_IS2TTIMING_0 |
| DDR_UIA_ODTIMPEDANCE_0 |
| DDR_UIA_TXIMPEDANCE_0 |
| DDR_UIA_ATXIMPEDANCE |
| DDR_UIA_MEMALERTEN |
| DDR_UIA_MEMALERTPUIMP |
| DDR_UIA_MEMALERTVREFLEVEL |
| DDR_UIA_MEMALERTSYNCBYPASS |
| DDR_UIA_DISDYNADRTRI_0 |
| DDR_UIA_PHYMSTRTRAININTERVAL_0 |
| DDR_UIA_PHYMSTRMAXREQTOACK_0 |
| DDR_UIA_WDQSEXT |
| DDR_UIA_CALINTERVAL |
| DDR_UIA_CALONCE |
| DDR_UIA_LP4RL_0 |
| DDR_UIA_LP4WL_0 |
| DDR_UIA_LP4WLS_0 |
| DDR_UIA_LP4DBIRD_0 |
| DDR_UIA_LP4DBIWR_0 |
| DDR_UIA_LP4NWR_0 |
| DDR_UIA_LP4LOWPOWERDRV |
| DDR_UIA_DRAMBYTESWAP |
| DDR_UIA_RXENBACKOFF |
| DDR_UIA_TRAINSEQUENCECTRL |
| DDR_UIA_SNPSUMCTLOPT |
| DDR_UIA_SNPSUMCTLF0RC5X_0 |
| DDR_UIA_TXSLEWRISEDQ_0 |
| DDR_UIA_TXSLEWFALLDQ_0 |
| DDR_UIA_TXSLEWRISEAC |
| DDR_UIA_TXSLEWFALLAC |
| DDR_UIA_DISABLERETRAINING |
| DDR_UIA_DISABLEPHYUPDATE |
| DDR_UIA_ENABLEHIGHCLKSKEWFIX |
| DDR_UIA_DISABLEUNUSEDADDRLNS |
| DDR_UIA_PHYINITSEQUENCENUM |
| DDR_UIA_ENABLEDFICSPOLARITYFIX |
| DDR_UIA_PHYVREF |
| DDR_UIA_SEQUENCECTRL_0 |
| >; |
| |
| st,phy-mr = < |
| DDR_UIM_MR0_0 |
| DDR_UIM_MR1_0 |
| DDR_UIM_MR2_0 |
| DDR_UIM_MR3_0 |
| DDR_UIM_MR4_0 |
| DDR_UIM_MR5_0 |
| DDR_UIM_MR6_0 |
| DDR_UIM_MR11_0 |
| DDR_UIM_MR12_0 |
| DDR_UIM_MR13_0 |
| DDR_UIM_MR14_0 |
| DDR_UIM_MR22_0 |
| >; |
| |
| st,phy-swizzle = < |
| DDR_UIS_SWIZZLE_0 |
| DDR_UIS_SWIZZLE_1 |
| DDR_UIS_SWIZZLE_2 |
| DDR_UIS_SWIZZLE_3 |
| DDR_UIS_SWIZZLE_4 |
| DDR_UIS_SWIZZLE_5 |
| DDR_UIS_SWIZZLE_6 |
| DDR_UIS_SWIZZLE_7 |
| DDR_UIS_SWIZZLE_8 |
| DDR_UIS_SWIZZLE_9 |
| DDR_UIS_SWIZZLE_10 |
| DDR_UIS_SWIZZLE_11 |
| DDR_UIS_SWIZZLE_12 |
| DDR_UIS_SWIZZLE_13 |
| DDR_UIS_SWIZZLE_14 |
| DDR_UIS_SWIZZLE_15 |
| DDR_UIS_SWIZZLE_16 |
| DDR_UIS_SWIZZLE_17 |
| DDR_UIS_SWIZZLE_18 |
| DDR_UIS_SWIZZLE_19 |
| DDR_UIS_SWIZZLE_20 |
| DDR_UIS_SWIZZLE_21 |
| DDR_UIS_SWIZZLE_22 |
| DDR_UIS_SWIZZLE_23 |
| DDR_UIS_SWIZZLE_24 |
| DDR_UIS_SWIZZLE_25 |
| DDR_UIS_SWIZZLE_26 |
| DDR_UIS_SWIZZLE_27 |
| DDR_UIS_SWIZZLE_28 |
| DDR_UIS_SWIZZLE_29 |
| DDR_UIS_SWIZZLE_30 |
| DDR_UIS_SWIZZLE_31 |
| DDR_UIS_SWIZZLE_32 |
| DDR_UIS_SWIZZLE_33 |
| DDR_UIS_SWIZZLE_34 |
| DDR_UIS_SWIZZLE_35 |
| DDR_UIS_SWIZZLE_36 |
| DDR_UIS_SWIZZLE_37 |
| DDR_UIS_SWIZZLE_38 |
| DDR_UIS_SWIZZLE_39 |
| DDR_UIS_SWIZZLE_40 |
| DDR_UIS_SWIZZLE_41 |
| DDR_UIS_SWIZZLE_42 |
| DDR_UIS_SWIZZLE_43 |
| >; |
| }; |
