blob: 08c014d8e21b0cf6815e8e6a3c1f3a7102cbe28e [file] [log] [blame]
Dan Handleyb4315302015-03-19 18:58:55 +00001/*
Manish V Badarkheef1daa42021-02-22 17:30:17 +00002 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
Dan Handleyb4315302015-03-19 18:58:55 +00003 *
dp-arm82cb2c12017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handleyb4315302015-03-19 18:58:55 +00005 */
6
Yatharth Kochara8aa7fe2016-09-13 17:07:57 +01007#include <assert.h>
Dan Handleyb4315302015-03-19 18:58:55 +00008#include <string.h>
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +00009
10#include <platform_def.h>
11
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -050012#include <arch_features.h>
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +000013#include <arch_helpers.h>
14#include <common/bl_common.h>
15#include <common/debug.h>
16#include <common/desc_image_load.h>
17#include <drivers/generic_delay_timer.h>
Manish V Badarkheef1daa42021-02-22 17:30:17 +000018#include <drivers/partition/partition.h>
Louis Mayencourt9814bfc2019-10-17 15:14:25 +010019#include <lib/fconf/fconf.h>
Manish V Badarkhe82869672020-06-11 22:32:11 +010020#include <lib/fconf/fconf_dyn_cfg_getter.h>
johpow01f19dc622021-06-16 17:57:28 -050021#if ENABLE_RME
22#include <lib/gpt_rme/gpt_rme.h>
23#endif /* ENABLE_RME */
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +000024#ifdef SPD_opteed
25#include <lib/optee_utils.h>
26#endif
27#include <lib/utils.h>
johpow01f19dc622021-06-16 17:57:28 -050028#if ENABLE_RME
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -050029#include <plat/arm/common/arm_pas_def.h>
johpow01f19dc622021-06-16 17:57:28 -050030#endif /* ENABLE_RME */
Antonio Nino Diazbd9344f2019-01-25 14:30:04 +000031#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +000032#include <plat/common/platform.h>
33
Dan Handleyb4315302015-03-19 18:58:55 +000034/* Data structure which holds the extents of the trusted SRAM for BL2 */
35static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
36
Manish V Badarkhea07c1012020-07-16 05:45:25 +010037/* Base address of fw_config received from BL1 */
Jimmy Brissond74c6b82020-08-05 14:05:53 -050038static uintptr_t config_base;
Manish V Badarkhea07c1012020-07-16 05:45:25 +010039
Soby Mathewcaf4eca2018-02-20 12:50:47 +000040/*
Manish V Badarkhe04e06972020-05-31 10:17:59 +010041 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
Soby Mathewc099cd32018-06-01 16:53:38 +010042 * for `meminfo_t` data structure and fw_configs passed from BL1.
Soby Mathewcaf4eca2018-02-20 12:50:47 +000043 */
Manish V Badarkhe04e06972020-05-31 10:17:59 +010044CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
Soby Mathewcaf4eca2018-02-20 12:50:47 +000045
Yatharth Kochara8aa7fe2016-09-13 17:07:57 +010046/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew0c306cc2018-01-10 15:59:31 +000047#pragma weak bl2_early_platform_setup2
Yatharth Kochara8aa7fe2016-09-13 17:07:57 +010048#pragma weak bl2_platform_setup
49#pragma weak bl2_plat_arch_setup
50#pragma weak bl2_plat_sec_mem_layout
51
Zelalem Aweke4bb72c42021-07-12 22:33:55 -050052#if ENABLE_RME
53#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
54 bl2_tzram_layout.total_base, \
55 bl2_tzram_layout.total_size, \
56 MT_MEMORY | MT_RW | MT_ROOT)
57#else
Daniel Boulbyd323af92018-07-06 16:54:44 +010058#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
59 bl2_tzram_layout.total_base, \
60 bl2_tzram_layout.total_size, \
61 MT_MEMORY | MT_RW | MT_SECURE)
Zelalem Aweke4bb72c42021-07-12 22:33:55 -050062#endif /* ENABLE_RME */
Dimitris Papastamos4a581b02018-06-08 13:17:26 +010063
Daniel Boulby490eeb02018-06-27 16:45:48 +010064#pragma weak arm_bl2_plat_handle_post_image_load
Dimitris Papastamos4a581b02018-06-08 13:17:26 +010065
Dan Handleyb4315302015-03-19 18:58:55 +000066/*******************************************************************************
67 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
68 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
69 * Copy it to a safe location before its reclaimed by later BL2 functionality.
70 ******************************************************************************/
Manish V Badarkhe04e06972020-05-31 10:17:59 +010071void arm_bl2_early_platform_setup(uintptr_t fw_config,
Sandrine Bailleux6c77e742018-07-11 12:44:22 +020072 struct meminfo *mem_layout)
Dan Handleyb4315302015-03-19 18:58:55 +000073{
74 /* Initialize the console to provide early debug support */
Antonio Nino Diaz88a05232018-06-19 09:29:36 +010075 arm_console_boot_init();
Dan Handleyb4315302015-03-19 18:58:55 +000076
77 /* Setup the BL2 memory layout */
78 bl2_tzram_layout = *mem_layout;
79
Jimmy Brissond74c6b82020-08-05 14:05:53 -050080 config_base = fw_config;
Louis Mayencourt9814bfc2019-10-17 15:14:25 +010081
Dan Handleyb4315302015-03-19 18:58:55 +000082 /* Initialise the IO layer and register platform IO devices */
83 plat_arm_io_setup();
Manish V Badarkheef1daa42021-02-22 17:30:17 +000084
85 /* Load partition table */
86#if ARM_GPT_SUPPORT
87 partition_init(GPT_IMAGE_ID);
88#endif /* ARM_GPT_SUPPORT */
89
Dan Handleyb4315302015-03-19 18:58:55 +000090}
91
Soby Mathew0c306cc2018-01-10 15:59:31 +000092void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
Dan Handleyb4315302015-03-19 18:58:55 +000093{
Soby Mathewcab0b5b2018-01-15 14:45:33 +000094 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
95
Soby Mathew18e279e2017-06-12 12:37:10 +010096 generic_delay_timer_init();
Dan Handleyb4315302015-03-19 18:58:55 +000097}
98
99/*
Soby Mathew6e79f9f2018-03-26 15:16:46 +0100100 * Perform BL2 preload setup. Currently we initialise the dynamic
101 * configuration here.
Dan Handleyb4315302015-03-19 18:58:55 +0000102 */
Soby Mathew6e79f9f2018-03-26 15:16:46 +0100103void bl2_plat_preload_setup(void)
Dan Handleyb4315302015-03-19 18:58:55 +0000104{
Soby Mathewcab0b5b2018-01-15 14:45:33 +0000105 arm_bl2_dyn_cfg_init();
Manish V Badarkheef1daa42021-02-22 17:30:17 +0000106
Manish V Badarkhe2f1177b2021-06-25 23:43:33 +0100107#if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT
108 /* Always use the FIP from bank 0 */
109 arm_set_fip_addr(0U);
110#endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */
Soby Mathew6e79f9f2018-03-26 15:16:46 +0100111}
Soby Mathewcab0b5b2018-01-15 14:45:33 +0000112
Soby Mathew6e79f9f2018-03-26 15:16:46 +0100113/*
114 * Perform ARM standard platform setup.
115 */
116void arm_bl2_platform_setup(void)
117{
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500118#if !ENABLE_RME
Dan Handleyb4315302015-03-19 18:58:55 +0000119 /* Initialize the secure environment */
120 plat_arm_security_setup();
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500121#endif
Roberto Vargasf1454032017-08-03 09:16:43 +0100122
123#if defined(PLAT_ARM_MEM_PROT_ADDR)
Roberto Vargas638b0342018-01-05 16:00:05 +0000124 arm_nor_psci_do_static_mem_protect();
Roberto Vargasf1454032017-08-03 09:16:43 +0100125#endif
Dan Handleyb4315302015-03-19 18:58:55 +0000126}
127
128void bl2_platform_setup(void)
129{
130 arm_bl2_platform_setup();
131}
132
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500133#if ENABLE_RME
johpow01f19dc622021-06-16 17:57:28 -0500134
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500135static void arm_bl2_plat_gpt_setup(void)
136{
137 /*
138 * The GPT library might modify the gpt regions structure to optimize
139 * the layout, so the array cannot be constant.
140 */
141 pas_region_t pas_regions[] = {
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500142 ARM_PAS_KERNEL,
johpow01f19dc622021-06-16 17:57:28 -0500143 ARM_PAS_SECURE,
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500144 ARM_PAS_REALM,
145 ARM_PAS_EL3_DRAM,
146 ARM_PAS_GPTS
147 };
148
johpow01f19dc622021-06-16 17:57:28 -0500149 /* Initialize entire protected space to GPT_GPI_ANY. */
150 if (gpt_init_l0_tables(GPCCR_PPS_4GB, ARM_L0_GPT_ADDR_BASE,
151 ARM_L0_GPT_SIZE) < 0) {
152 ERROR("gpt_init_l0_tables() failed!\n");
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500153 panic();
154 }
155
johpow01f19dc622021-06-16 17:57:28 -0500156 /* Carve out defined PAS ranges. */
157 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K,
158 ARM_L1_GPT_ADDR_BASE,
159 ARM_L1_GPT_SIZE,
160 pas_regions,
161 (unsigned int)(sizeof(pas_regions) /
162 sizeof(pas_region_t))) < 0) {
163 ERROR("gpt_init_pas_l1_tables() failed!\n");
164 panic();
165 }
166
167 INFO("Enabling Granule Protection Checks\n");
168 if (gpt_enable() < 0) {
169 ERROR("gpt_enable() failed!\n");
170 panic();
171 }
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500172}
johpow01f19dc622021-06-16 17:57:28 -0500173
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500174#endif /* ENABLE_RME */
175
Dan Handleyb4315302015-03-19 18:58:55 +0000176/*******************************************************************************
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500177 * Perform the very early platform specific architectural setup here.
178 * When RME is enabled the secure environment is initialised before
179 * initialising and enabling Granule Protection.
180 * This function initialises the MMU in a quick and dirty way.
Dan Handleyb4315302015-03-19 18:58:55 +0000181 ******************************************************************************/
182void arm_bl2_plat_arch_setup(void)
183{
Soby Mathew943bb7f2018-09-18 11:42:42 +0100184#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
185 /*
186 * Ensure ARM platforms don't use coherent memory in BL2 unless
187 * cryptocell integration is enabled.
188 */
Daniel Boulbyd323af92018-07-06 16:54:44 +0100189 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handleyb4315302015-03-19 18:58:55 +0000190#endif
Daniel Boulbyd323af92018-07-06 16:54:44 +0100191
192 const mmap_region_t bl_regions[] = {
193 MAP_BL2_TOTAL,
Daniel Boulby2ecaafd2018-07-16 14:09:15 +0100194 ARM_MAP_BL_RO,
Roberto Vargas1eb735d2018-05-23 09:27:06 +0100195#if USE_ROMLIB
196 ARM_MAP_ROMLIB_CODE,
197 ARM_MAP_ROMLIB_DATA,
198#endif
Soby Mathew943bb7f2018-09-18 11:42:42 +0100199#if ARM_CRYPTOCELL_INTEG
200 ARM_MAP_BL_COHERENT_RAM,
201#endif
Manish V Badarkhea07c1012020-07-16 05:45:25 +0100202 ARM_MAP_BL_CONFIG_REGION,
Zelalem Awekec8720722021-07-12 23:41:05 -0500203#if ENABLE_RME
204 ARM_MAP_L0_GPT_REGION,
205#endif
Daniel Boulbyd323af92018-07-06 16:54:44 +0100206 {0}
207 };
208
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500209#if ENABLE_RME
210 /* Initialise the secure environment */
211 plat_arm_security_setup();
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500212#endif
Roberto Vargas0916c382018-10-19 16:44:18 +0100213 setup_page_tables(bl_regions, plat_arm_get_mmap());
Yatharth Kochar6fe8aa22016-07-04 11:26:14 +0100214
Julius Werner402b3cf2019-07-09 14:02:43 -0700215#ifdef __aarch64__
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500216#if ENABLE_RME
217 /* BL2 runs in EL3 when RME enabled. */
218 assert(get_armv9_2_feat_rme_support() != 0U);
219 enable_mmu_el3(0);
johpow01f19dc622021-06-16 17:57:28 -0500220
221 /* Initialise and enable granule protection after MMU. */
222 arm_bl2_plat_gpt_setup();
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500223#else
Sandrine Bailleuxb5fa6562016-05-18 16:11:47 +0100224 enable_mmu_el1(0);
Zelalem Awekedeb4b3a2021-07-13 17:19:54 -0500225#endif
Julius Werner402b3cf2019-07-09 14:02:43 -0700226#else
227 enable_mmu_svc_mon(0);
Yatharth Kochar6fe8aa22016-07-04 11:26:14 +0100228#endif
Roberto Vargas1eb735d2018-05-23 09:27:06 +0100229
230 arm_setup_romlib();
Dan Handleyb4315302015-03-19 18:58:55 +0000231}
232
233void bl2_plat_arch_setup(void)
234{
Manish V Badarkhea07c1012020-07-16 05:45:25 +0100235 const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
236
Dan Handleyb4315302015-03-19 18:58:55 +0000237 arm_bl2_plat_arch_setup();
Manish V Badarkhea07c1012020-07-16 05:45:25 +0100238
239 /* Fill the properties struct with the info from the config dtb */
Jimmy Brissond74c6b82020-08-05 14:05:53 -0500240 fconf_populate("FW_CONFIG", config_base);
Manish V Badarkhea07c1012020-07-16 05:45:25 +0100241
242 /* TB_FW_CONFIG was also loaded by BL1 */
243 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID);
244 assert(tb_fw_config_info != NULL);
245
246 fconf_populate("TB_FW", tb_fw_config_info->config_addr);
Dan Handleyb4315302015-03-19 18:58:55 +0000247}
248
Yatharth Kochar07570d52016-11-14 12:01:04 +0000249int arm_bl2_handle_post_image_load(unsigned int image_id)
Yatharth Kochara8aa7fe2016-09-13 17:07:57 +0100250{
251 int err = 0;
252 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Summer Qin54661cd2017-04-24 16:49:28 +0100253#ifdef SPD_opteed
254 bl_mem_params_node_t *pager_mem_params = NULL;
255 bl_mem_params_node_t *paged_mem_params = NULL;
256#endif
Zelalem466bb282020-02-05 14:12:39 -0600257 assert(bl_mem_params != NULL);
Yatharth Kochara8aa7fe2016-09-13 17:07:57 +0100258
259 switch (image_id) {
Julius Werner402b3cf2019-07-09 14:02:43 -0700260#ifdef __aarch64__
Yatharth Kochara8aa7fe2016-09-13 17:07:57 +0100261 case BL32_IMAGE_ID:
Summer Qin54661cd2017-04-24 16:49:28 +0100262#ifdef SPD_opteed
263 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
264 assert(pager_mem_params);
265
266 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
267 assert(paged_mem_params);
268
269 err = parse_optee_header(&bl_mem_params->ep_info,
270 &pager_mem_params->image_info,
271 &paged_mem_params->image_info);
272 if (err != 0) {
273 WARN("OPTEE header parse error.\n");
274 }
275#endif
Yatharth Kochara8aa7fe2016-09-13 17:07:57 +0100276 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
277 break;
Yatharth Kochar6fe8aa22016-07-04 11:26:14 +0100278#endif
Yatharth Kochara8aa7fe2016-09-13 17:07:57 +0100279
280 case BL33_IMAGE_ID:
281 /* BL33 expects to receive the primary CPU MPID (through r0) */
282 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
283 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
284 break;
285
286#ifdef SCP_BL2_BASE
287 case SCP_BL2_IMAGE_ID:
288 /* The subsequent handling of SCP_BL2 is platform specific */
289 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
290 if (err) {
291 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
292 }
293 break;
294#endif
Jonathan Wright649c48f2018-03-14 15:24:00 +0000295 default:
296 /* Do nothing in default case */
297 break;
Yatharth Kochara8aa7fe2016-09-13 17:07:57 +0100298 }
299
300 return err;
301}
302
Yatharth Kochar07570d52016-11-14 12:01:04 +0000303/*******************************************************************************
304 * This function can be used by the platforms to update/use image
305 * information for given `image_id`.
306 ******************************************************************************/
Daniel Boulby490eeb02018-06-27 16:45:48 +0100307int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
Yatharth Kochar07570d52016-11-14 12:01:04 +0000308{
Balint Dobszay46789a72021-03-26 16:23:18 +0100309#if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD
Manish Pandeycb3b5342020-02-25 11:38:19 +0000310 /* For Secure Partitions we don't need post processing */
311 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) &&
312 (image_id < MAX_NUMBER_IDS)) {
313 return 0;
314 }
315#endif
Yatharth Kochar07570d52016-11-14 12:01:04 +0000316 return arm_bl2_handle_post_image_load(image_id);
317}
318
Daniel Boulby490eeb02018-06-27 16:45:48 +0100319int bl2_plat_handle_post_image_load(unsigned int image_id)
320{
321 return arm_bl2_plat_handle_post_image_load(image_id);
322}