Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Manish Pandey | b30646a | 2019-10-18 11:01:03 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | 82cb2c1 | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 7 | #include <platform_def.h> |
| 8 | |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <arch.h> |
Antonio Nino Diaz | bd9344f | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 10 | #include <plat/arm/common/plat_arm.h> |
Antonio Nino Diaz | 09d40e0 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | |
Soby Mathew | 38dce70 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 12 | /******************************************************************************* |
| 13 | * This function validates an MPIDR by checking whether it falls within the |
| 14 | * acceptable bounds. An error code (-1) is returned if an incorrect mpidr |
| 15 | * is passed. |
| 16 | ******************************************************************************/ |
| 17 | int arm_check_mpidr(u_register_t mpidr) |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 18 | { |
Soby Mathew | 38dce70 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 19 | unsigned int cluster_id, cpu_id; |
Summer Qin | d8d6cf2 | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 20 | uint64_t valid_mask; |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 21 | |
Summer Qin | d8d6cf2 | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 22 | #if ARM_PLAT_MT |
| 23 | unsigned int pe_id; |
Soby Mathew | 38dce70 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 24 | |
Summer Qin | d8d6cf2 | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 25 | valid_mask = ~(MPIDR_AFFLVL_MASK | |
| 26 | (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | |
Manish Pandey | b30646a | 2019-10-18 11:01:03 +0100 | [diff] [blame] | 27 | (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | |
| 28 | (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT)); |
Summer Qin | d8d6cf2 | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 29 | cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; |
| 30 | cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; |
| 31 | pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; |
| 32 | #else |
| 33 | valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK); |
Sathees Balya | 8950990 | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 34 | cluster_id = (unsigned int) ((mpidr >> MPIDR_AFF1_SHIFT) & |
| 35 | MPIDR_AFFLVL_MASK); |
| 36 | cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) & |
| 37 | MPIDR_AFFLVL_MASK); |
Summer Qin | d8d6cf2 | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 38 | #endif /* ARM_PLAT_MT */ |
| 39 | |
| 40 | mpidr &= MPIDR_AFFINITY_MASK; |
Sathees Balya | 8950990 | 2018-09-27 14:41:02 +0100 | [diff] [blame] | 41 | if ((mpidr & valid_mask) != 0U) |
Summer Qin | d8d6cf2 | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 42 | return -1; |
Soby Mathew | 38dce70 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 43 | |
Soby Mathew | 0108047 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 44 | if (cluster_id >= PLAT_ARM_CLUSTER_COUNT) |
Soby Mathew | 38dce70 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 45 | return -1; |
| 46 | |
| 47 | /* Validate cpu_id by checking whether it represents a CPU in |
| 48 | one of the two clusters present on the platform. */ |
Soby Mathew | 0108047 | 2016-02-01 14:04:34 +0000 | [diff] [blame] | 49 | if (cpu_id >= plat_arm_get_cluster_core_count(mpidr)) |
Soby Mathew | 38dce70 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 50 | return -1; |
| 51 | |
Summer Qin | d8d6cf2 | 2017-02-28 16:46:17 +0000 | [diff] [blame] | 52 | #if ARM_PLAT_MT |
| 53 | if (pe_id >= plat_arm_get_cpu_pe_count(mpidr)) |
| 54 | return -1; |
| 55 | #endif /* ARM_PLAT_MT */ |
| 56 | |
Soby Mathew | 38dce70 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 57 | return 0; |
Dan Handley | b431530 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 58 | } |