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Dan Handleyb4315302015-03-19 18:58:55 +00001/*
Manish Pandeyb30646a2019-10-18 11:01:03 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Dan Handleyb4315302015-03-19 18:58:55 +00003 *
dp-arm82cb2c12017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handleyb4315302015-03-19 18:58:55 +00005 */
6
Dan Handleyb4315302015-03-19 18:58:55 +00007#include <platform_def.h>
8
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +00009#include <arch.h>
Antonio Nino Diazbd9344f2019-01-25 14:30:04 +000010#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +000011
Soby Mathew38dce702015-07-01 16:16:20 +010012/*******************************************************************************
13 * This function validates an MPIDR by checking whether it falls within the
14 * acceptable bounds. An error code (-1) is returned if an incorrect mpidr
15 * is passed.
16 ******************************************************************************/
17int arm_check_mpidr(u_register_t mpidr)
Dan Handleyb4315302015-03-19 18:58:55 +000018{
Soby Mathew38dce702015-07-01 16:16:20 +010019 unsigned int cluster_id, cpu_id;
Summer Qind8d6cf22017-02-28 16:46:17 +000020 uint64_t valid_mask;
Dan Handleyb4315302015-03-19 18:58:55 +000021
Summer Qind8d6cf22017-02-28 16:46:17 +000022#if ARM_PLAT_MT
23 unsigned int pe_id;
Soby Mathew38dce702015-07-01 16:16:20 +010024
Summer Qind8d6cf22017-02-28 16:46:17 +000025 valid_mask = ~(MPIDR_AFFLVL_MASK |
26 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) |
Manish Pandeyb30646a2019-10-18 11:01:03 +010027 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) |
28 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT));
Summer Qind8d6cf22017-02-28 16:46:17 +000029 cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK;
30 cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
31 pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
32#else
33 valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK);
Sathees Balya89509902018-09-27 14:41:02 +010034 cluster_id = (unsigned int) ((mpidr >> MPIDR_AFF1_SHIFT) &
35 MPIDR_AFFLVL_MASK);
36 cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) &
37 MPIDR_AFFLVL_MASK);
Summer Qind8d6cf22017-02-28 16:46:17 +000038#endif /* ARM_PLAT_MT */
39
40 mpidr &= MPIDR_AFFINITY_MASK;
Sathees Balya89509902018-09-27 14:41:02 +010041 if ((mpidr & valid_mask) != 0U)
Summer Qind8d6cf22017-02-28 16:46:17 +000042 return -1;
Soby Mathew38dce702015-07-01 16:16:20 +010043
Soby Mathew01080472016-02-01 14:04:34 +000044 if (cluster_id >= PLAT_ARM_CLUSTER_COUNT)
Soby Mathew38dce702015-07-01 16:16:20 +010045 return -1;
46
47 /* Validate cpu_id by checking whether it represents a CPU in
48 one of the two clusters present on the platform. */
Soby Mathew01080472016-02-01 14:04:34 +000049 if (cpu_id >= plat_arm_get_cluster_core_count(mpidr))
Soby Mathew38dce702015-07-01 16:16:20 +010050 return -1;
51
Summer Qind8d6cf22017-02-28 16:46:17 +000052#if ARM_PLAT_MT
53 if (pe_id >= plat_arm_get_cpu_pe_count(mpidr))
54 return -1;
55#endif /* ARM_PLAT_MT */
56
Soby Mathew38dce702015-07-01 16:16:20 +010057 return 0;
Dan Handleyb4315302015-03-19 18:58:55 +000058}