| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DCORE0_EDMA1_CORE_CTX_AXUSER_REGS_H_ |
| #define ASIC_REG_DCORE0_EDMA1_CORE_CTX_AXUSER_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DCORE0_EDMA1_CORE_CTX_AXUSER |
| * (Prototype: AXUSER) |
| ***************************************** |
| */ |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_ASID 0x41DB800 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_MMU_BP 0x41DB804 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_STRONG_ORDER 0x41DB808 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_NO_SNOOP 0x41DB80C |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_WR_REDUCTION 0x41DB810 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RD_ATOMIC 0x41DB814 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_QOS 0x41DB818 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RSVD 0x41DB81C |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_EMEM_CPAGE 0x41DB820 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_CORE 0x41DB824 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_E2E_COORD 0x41DB828 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_LO 0x41DB830 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_WR_OVRD_HI 0x41DB834 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_LO 0x41DB838 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_RD_OVRD_HI 0x41DB83C |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_COORD 0x41DB840 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_LOCK 0x41DB844 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_RSVD 0x41DB848 |
| |
| #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_LB_OVRD 0x41DB84C |
| |
| #endif /* ASIC_REG_DCORE0_EDMA1_CORE_CTX_AXUSER_REGS_H_ */ |
