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android-kvm / linux / 5e74df2f8f15eaa1ebbdfc1f6fef27a26d789de8 / . / drivers / accel / habanalabs / include / gaudi2 / asic_reg
tree: 85cb2cb18d3aac263a60b0c789f1f7a6b152878b [path history] [tgz]
  1. arc_farm_arc0_acp_eng_regs.h
  2. arc_farm_arc0_aux_masks.h
  3. arc_farm_arc0_aux_regs.h
  4. arc_farm_arc0_dup_eng_axuser_regs.h
  5. arc_farm_arc0_dup_eng_regs.h
  6. arc_farm_kdma_ctx_axuser_masks.h
  7. arc_farm_kdma_ctx_axuser_regs.h
  8. arc_farm_kdma_ctx_masks.h
  9. arc_farm_kdma_ctx_regs.h
  10. arc_farm_kdma_kdma_cgm_regs.h
  11. arc_farm_kdma_masks.h
  12. arc_farm_kdma_regs.h
  13. cpu_if_regs.h
  14. dcore0_dec0_cmd_masks.h
  15. dcore0_dec0_cmd_regs.h
  16. dcore0_edma0_core_ctx_axuser_regs.h
  17. dcore0_edma0_core_ctx_regs.h
  18. dcore0_edma0_core_masks.h
  19. dcore0_edma0_core_regs.h
  20. dcore0_edma0_qm_arc_aux_regs.h
  21. dcore0_edma0_qm_axuser_nonsecured_regs.h
  22. dcore0_edma0_qm_cgm_regs.h
  23. dcore0_edma0_qm_masks.h
  24. dcore0_edma0_qm_regs.h
  25. dcore0_edma1_core_ctx_axuser_regs.h
  26. dcore0_edma1_qm_axuser_nonsecured_regs.h
  27. dcore0_hmmu0_mmu_masks.h
  28. dcore0_hmmu0_mmu_regs.h
  29. dcore0_hmmu0_stlb_masks.h
  30. dcore0_hmmu0_stlb_regs.h
  31. dcore0_mme_acc_regs.h
  32. dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h
  33. dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h
  34. dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h
  35. dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h
  36. dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h
  37. dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h
  38. dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h
  39. dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h
  40. dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h
  41. dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h
  42. dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h
  43. dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h
  44. dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h
  45. dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h
  46. dcore0_mme_ctrl_lo_arch_base_addr_regs.h
  47. dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h
  48. dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h
  49. dcore0_mme_ctrl_lo_arch_tensor_a_regs.h
  50. dcore0_mme_ctrl_lo_arch_tensor_b_regs.h
  51. dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h
  52. dcore0_mme_ctrl_lo_masks.h
  53. dcore0_mme_ctrl_lo_mme_axuser_regs.h
  54. dcore0_mme_ctrl_lo_regs.h
  55. dcore0_mme_qm_arc_acp_eng_regs.h
  56. dcore0_mme_qm_arc_aux_regs.h
  57. dcore0_mme_qm_arc_dup_eng_axuser_regs.h
  58. dcore0_mme_qm_arc_dup_eng_regs.h
  59. dcore0_mme_qm_axuser_nonsecured_regs.h
  60. dcore0_mme_qm_axuser_secured_regs.h
  61. dcore0_mme_qm_cgm_regs.h
  62. dcore0_mme_qm_regs.h
  63. dcore0_mme_sbte0_masks.h
  64. dcore0_mme_sbte0_mstr_if_axuser_regs.h
  65. dcore0_mme_wb0_mstr_if_axuser_regs.h
  66. dcore0_rtr0_ctrl_regs.h
  67. dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h
  68. dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h
  69. dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h
  70. dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h
  71. dcore0_sync_mngr_glbl_masks.h
  72. dcore0_sync_mngr_glbl_regs.h
  73. dcore0_sync_mngr_mstr_if_axuser_masks.h
  74. dcore0_sync_mngr_mstr_if_axuser_regs.h
  75. dcore0_sync_mngr_objs_masks.h
  76. dcore0_sync_mngr_objs_regs.h
  77. dcore0_tpc0_cfg_axuser_regs.h
  78. dcore0_tpc0_cfg_kernel_regs.h
  79. dcore0_tpc0_cfg_kernel_tensor_0_regs.h
  80. dcore0_tpc0_cfg_masks.h
  81. dcore0_tpc0_cfg_qm_regs.h
  82. dcore0_tpc0_cfg_qm_sync_object_regs.h
  83. dcore0_tpc0_cfg_qm_tensor_0_regs.h
  84. dcore0_tpc0_cfg_regs.h
  85. dcore0_tpc0_cfg_special_regs.h
  86. dcore0_tpc0_eml_busmon_0_regs.h
  87. dcore0_tpc0_eml_etf_regs.h
  88. dcore0_tpc0_eml_funnel_regs.h
  89. dcore0_tpc0_eml_spmu_regs.h
  90. dcore0_tpc0_eml_stm_regs.h
  91. dcore0_tpc0_qm_arc_aux_regs.h
  92. dcore0_tpc0_qm_axuser_nonsecured_regs.h
  93. dcore0_tpc0_qm_cgm_regs.h
  94. dcore0_tpc0_qm_regs.h
  95. dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h
  96. dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h
  97. dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h
  98. dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h
  99. dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h
  100. dcore0_vdec0_brdg_ctrl_masks.h
  101. dcore0_vdec0_brdg_ctrl_regs.h
  102. dcore0_vdec0_ctrl_special_regs.h
  103. dcore1_mme_ctrl_lo_regs.h
  104. dcore1_sync_mngr_glbl_regs.h
  105. dcore3_mme_ctrl_lo_regs.h
  106. gaudi2_blocks_linux_driver.h
  107. gaudi2_regs.h
  108. nic0_qm0_cgm_regs.h
  109. nic0_qm0_regs.h
  110. nic0_qm_arc_aux0_regs.h
  111. nic0_qpc0_regs.h
  112. nic0_umr0_0_completion_queue_ci_1_regs.h
  113. nic0_umr0_0_unsecure_doorbell0_regs.h
  114. pcie_aux_regs.h
  115. pcie_dbi_regs.h
  116. pcie_dec0_cmd_masks.h
  117. pcie_dec0_cmd_regs.h
  118. pcie_vdec0_brdg_ctrl_axuser_dec_regs.h
  119. pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h
  120. pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h
  121. pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h
  122. pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h
  123. pcie_vdec0_brdg_ctrl_masks.h
  124. pcie_vdec0_brdg_ctrl_regs.h
  125. pcie_vdec0_ctrl_special_regs.h
  126. pcie_wrap_regs.h
  127. pcie_wrap_special_regs.h
  128. pdma0_core_ctx_axuser_regs.h
  129. pdma0_core_ctx_regs.h
  130. pdma0_core_masks.h
  131. pdma0_core_regs.h
  132. pdma0_core_special_masks.h
  133. pdma0_qm_arc_aux_regs.h
  134. pdma0_qm_axuser_nonsecured_regs.h
  135. pdma0_qm_axuser_secured_regs.h
  136. pdma0_qm_cgm_regs.h
  137. pdma0_qm_masks.h
  138. pdma0_qm_regs.h
  139. pdma1_core_ctx_axuser_regs.h
  140. pdma1_qm_axuser_nonsecured_regs.h
  141. pmmu_hbw_stlb_masks.h
  142. pmmu_hbw_stlb_regs.h
  143. pmmu_pif_regs.h
  144. psoc_etr_masks.h
  145. psoc_etr_regs.h
  146. psoc_global_conf_masks.h
  147. psoc_global_conf_regs.h
  148. psoc_reset_conf_masks.h
  149. psoc_reset_conf_regs.h
  150. psoc_timestamp_regs.h
  151. rot0_desc_regs.h
  152. rot0_masks.h
  153. rot0_qm_arc_aux_regs.h
  154. rot0_qm_axuser_nonsecured_regs.h
  155. rot0_qm_cgm_regs.h
  156. rot0_qm_regs.h
  157. rot0_regs.h
  158. xbar_edge_0_regs.h
  159. xbar_mid_0_regs.h