drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_tensor_a_regs.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_REGS_H_
#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_REGS_H_

/*
 *****************************************
 *   DCORE0_MME_CTRL_LO_ARCH_TENSOR_A
 *   (Prototype: MME_TENSOR)
 *****************************************
 */

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0 0x40CB040

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1 0x40CB044

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2 0x40CB048

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3 0x40CB04C

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4 0x40CB050

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0 0x40CB054

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1 0x40CB058

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2 0x40CB05C

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3 0x40CB060

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4 0x40CB064

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0 0x40CB068

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1 0x40CB06C

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2 0x40CB070

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3 0x40CB074

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0 0x40CB078

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1 0x40CB07C

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2 0x40CB080

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3 0x40CB084

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0 0x40CB088

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1 0x40CB08C

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2 0x40CB090

#define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3 0x40CB094

#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_REGS_H_ */